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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=x86-64 < %s | FileCheck %s3 4; This file checks the reassociation of ADD instruction.5; The two ADD instructions add v0,v1,t2 together. t2 has a long dependence6; chain, v0 and v1 has a short dependence chain, in order to get the shortest7; latency, v0 and v1 should be added first, and its result is added to t28; later.9 10define void @add8(i8 %x0, i8 %x1, i8 %x2, ptr %p) {11; CHECK-LABEL: add8:12; CHECK: # %bb.0:13; CHECK-NEXT: orb $16, %dil14; CHECK-NEXT: orb $32, %sil15; CHECK-NEXT: addb %dil, %sil16; CHECK-NEXT: addb $-8, %dl17; CHECK-NEXT: orb $7, %dl18; CHECK-NEXT: movzbl %dl, %eax19; CHECK-NEXT: imull $100, %eax, %eax20; CHECK-NEXT: addb %sil, %al21; CHECK-NEXT: movb %al, (%rcx)22; CHECK-NEXT: retq23 %v0 = or i8 %x0, 1624 %v1 = or i8 %x1, 3225 %t0 = sub i8 %x2, 826 %t1 = or i8 %t0, 727 %t2 = mul i8 %t1, 10028 %t3 = add i8 %t2, %v129 %t4 = add i8 %t3, %v030 store i8 %t4, ptr %p, align 431 ret void32}33 34define void @add16(i16 %x0, i16 %x1, i16 %x2, ptr %p) {35; CHECK-LABEL: add16:36; CHECK: # %bb.0:37; CHECK-NEXT: orl $16, %edi38; CHECK-NEXT: orl $32, %esi39; CHECK-NEXT: addl %edi, %esi40; CHECK-NEXT: addl $-8, %edx41; CHECK-NEXT: orl $7, %edx42; CHECK-NEXT: imull $100, %edx, %eax43; CHECK-NEXT: addl %esi, %eax44; CHECK-NEXT: movw %ax, (%rcx)45; CHECK-NEXT: retq46 %v0 = or i16 %x0, 1647 %v1 = or i16 %x1, 3248 %t0 = sub i16 %x2, 849 %t1 = or i16 %t0, 750 %t2 = mul i16 %t1, 10051 %t3 = add i16 %t2, %v152 %t4 = add i16 %t3, %v053 store i16 %t4, ptr %p, align 454 ret void55}56 57define void @add32(i32 %x0, i32 %x1, i32 %x2, ptr %p) {58; CHECK-LABEL: add32:59; CHECK: # %bb.0:60; CHECK-NEXT: orl $16, %edi61; CHECK-NEXT: orl $32, %esi62; CHECK-NEXT: addl %edi, %esi63; CHECK-NEXT: addl $-8, %edx64; CHECK-NEXT: orl $7, %edx65; CHECK-NEXT: imull $100, %edx, %eax66; CHECK-NEXT: addl %esi, %eax67; CHECK-NEXT: movl %eax, (%rcx)68; CHECK-NEXT: retq69 %v0 = or i32 %x0, 1670 %v1 = or i32 %x1, 3271 %t0 = sub i32 %x2, 872 %t1 = or i32 %t0, 773 %t2 = mul i32 %t1, 10074 %t3 = add i32 %t2, %v175 %t4 = add i32 %t3, %v076 store i32 %t4, ptr %p, align 477 ret void78}79 80define void @add64(i64 %x0, i64 %x1, i64 %x2, ptr %p) {81; CHECK-LABEL: add64:82; CHECK: # %bb.0:83; CHECK-NEXT: orq $16, %rdi84; CHECK-NEXT: orq $32, %rsi85; CHECK-NEXT: addq %rdi, %rsi86; CHECK-NEXT: addq $-8, %rdx87; CHECK-NEXT: orq $7, %rdx88; CHECK-NEXT: imulq $100, %rdx, %rax89; CHECK-NEXT: addq %rsi, %rax90; CHECK-NEXT: movq %rax, (%rcx)91; CHECK-NEXT: retq92 %v0 = or i64 %x0, 1693 %v1 = or i64 %x1, 3294 %t0 = sub i64 %x2, 895 %t1 = or i64 %t0, 796 %t2 = mul i64 %t1, 10097 %t3 = add i64 %t2, %v198 %t4 = add i64 %t3, %v099 store i64 %t4, ptr %p, align 4100 ret void101}102 103; Negative test. Original sequence has shorter latency, don't transform it.104define void @add64_negative(i64 %x0, i64 %x1, i64 %x2, ptr %p) {105; CHECK-LABEL: add64_negative:106; CHECK: # %bb.0:107; CHECK-NEXT: orq $16, %rdi108; CHECK-NEXT: orq $32, %rsi109; CHECK-NEXT: addq %rdi, %rsi110; CHECK-NEXT: addq $-8, %rdx111; CHECK-NEXT: orq $7, %rdx112; CHECK-NEXT: imulq $100, %rdx, %rax113; CHECK-NEXT: addq %rsi, %rax114; CHECK-NEXT: movq %rax, (%rcx)115; CHECK-NEXT: retq116 %v0 = or i64 %x0, 16117 %v1 = or i64 %x1, 32118 %t0 = sub i64 %x2, 8119 %t1 = or i64 %t0, 7120 %t2 = mul i64 %t1, 100121 %t3 = add i64 %v0, %v1122 %t4 = add i64 %t3, %t2123 store i64 %t4, ptr %p, align 4124 ret void125}126