776 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; Context:3; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s4define i32 @check_none() "frame-pointer"="none" {5; CHECK-LABEL: check_none:6; CHECK: # %bb.0: # %entry7; CHECK-NEXT: pushq %rbp8; CHECK-NEXT: .cfi_def_cfa_offset 169; CHECK-NEXT: pushq %r1510; CHECK-NEXT: .cfi_def_cfa_offset 2411; CHECK-NEXT: pushq %r1412; CHECK-NEXT: .cfi_def_cfa_offset 3213; CHECK-NEXT: pushq %r1314; CHECK-NEXT: .cfi_def_cfa_offset 4015; CHECK-NEXT: pushq %r1216; CHECK-NEXT: .cfi_def_cfa_offset 4817; CHECK-NEXT: pushq %rbx18; CHECK-NEXT: .cfi_def_cfa_offset 5619; CHECK-NEXT: .cfi_offset %rbx, -5620; CHECK-NEXT: .cfi_offset %r12, -4821; CHECK-NEXT: .cfi_offset %r13, -4022; CHECK-NEXT: .cfi_offset %r14, -3223; CHECK-NEXT: .cfi_offset %r15, -2424; CHECK-NEXT: .cfi_offset %rbp, -1625; CHECK-NEXT: movl $0, -{{[0-9]+}}(%rsp)26; CHECK-NEXT: movl $1, -{{[0-9]+}}(%rsp)27; CHECK-NEXT: movl $2, -{{[0-9]+}}(%rsp)28; CHECK-NEXT: movl $3, -{{[0-9]+}}(%rsp)29; CHECK-NEXT: movl $4, -{{[0-9]+}}(%rsp)30; CHECK-NEXT: movl $5, -{{[0-9]+}}(%rsp)31; CHECK-NEXT: movl $6, -{{[0-9]+}}(%rsp)32; CHECK-NEXT: movl $7, -{{[0-9]+}}(%rsp)33; CHECK-NEXT: movl $8, -{{[0-9]+}}(%rsp)34; CHECK-NEXT: movl $9, -{{[0-9]+}}(%rsp)35; CHECK-NEXT: movl $16, -{{[0-9]+}}(%rsp)36; CHECK-NEXT: movl $17, -{{[0-9]+}}(%rsp)37; CHECK-NEXT: movl $18, -{{[0-9]+}}(%rsp)38; CHECK-NEXT: movl $19, -{{[0-9]+}}(%rsp)39; CHECK-NEXT: movl $20, -{{[0-9]+}}(%rsp)40; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax41; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %ecx42; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %edx43; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %esi44; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %edi45; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %r8d46; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %r9d47; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %r10d48; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %r11d49; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %ebx50; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %ebp51; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %r14d52; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %r15d53; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %r12d54; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %r13d55; CHECK-NEXT: #APP56; CHECK-NEXT: nop57; CHECK-NEXT: #NO_APP58; CHECK-NEXT: movl %eax, -{{[0-9]+}}(%rsp)59; CHECK-NEXT: movl %ecx, -{{[0-9]+}}(%rsp)60; CHECK-NEXT: movl %edx, -{{[0-9]+}}(%rsp)61; CHECK-NEXT: movl %esi, -{{[0-9]+}}(%rsp)62; CHECK-NEXT: movl %edi, -{{[0-9]+}}(%rsp)63; CHECK-NEXT: movl %r8d, -{{[0-9]+}}(%rsp)64; CHECK-NEXT: movl %r9d, -{{[0-9]+}}(%rsp)65; CHECK-NEXT: movl %r10d, -{{[0-9]+}}(%rsp)66; CHECK-NEXT: movl %r11d, -{{[0-9]+}}(%rsp)67; CHECK-NEXT: movl %ebx, -{{[0-9]+}}(%rsp)68; CHECK-NEXT: movl %ebp, -{{[0-9]+}}(%rsp)69; CHECK-NEXT: movl %r14d, -{{[0-9]+}}(%rsp)70; CHECK-NEXT: movl %r15d, -{{[0-9]+}}(%rsp)71; CHECK-NEXT: movl %r12d, -{{[0-9]+}}(%rsp)72; CHECK-NEXT: movl %r13d, -{{[0-9]+}}(%rsp)73; CHECK-NEXT: xorl %eax, %eax74; CHECK-NEXT: popq %rbx75; CHECK-NEXT: .cfi_def_cfa_offset 4876; CHECK-NEXT: popq %r1277; CHECK-NEXT: .cfi_def_cfa_offset 4078; CHECK-NEXT: popq %r1379; CHECK-NEXT: .cfi_def_cfa_offset 3280; CHECK-NEXT: popq %r1481; CHECK-NEXT: .cfi_def_cfa_offset 2482; CHECK-NEXT: popq %r1583; CHECK-NEXT: .cfi_def_cfa_offset 1684; CHECK-NEXT: popq %rbp85; CHECK-NEXT: .cfi_def_cfa_offset 886; CHECK-NEXT: retq87entry:88 %reg0 = alloca i32, align 489 %reg1 = alloca i32, align 490 %reg2 = alloca i32, align 491 %reg3 = alloca i32, align 492 %reg4 = alloca i32, align 493 %reg5 = alloca i32, align 494 %reg6 = alloca i32, align 495 %reg7 = alloca i32, align 496 %reg8 = alloca i32, align 497 %reg9 = alloca i32, align 498 %reg10 = alloca i32, align 499 %reg11 = alloca i32, align 4100 %reg12 = alloca i32, align 4101 %reg13 = alloca i32, align 4102 %reg14 = alloca i32, align 4103 store volatile i32 0, ptr %reg0, align 4104 store volatile i32 1, ptr %reg1, align 4105 store volatile i32 2, ptr %reg2, align 4106 store volatile i32 3, ptr %reg3, align 4107 store volatile i32 4, ptr %reg4, align 4108 store volatile i32 5, ptr %reg5, align 4109 store volatile i32 6, ptr %reg6, align 4110 store volatile i32 7, ptr %reg7, align 4111 store volatile i32 8, ptr %reg8, align 4112 store volatile i32 9, ptr %reg9, align 4113 store volatile i32 16, ptr %reg10, align 4114 store volatile i32 17, ptr %reg11, align 4115 store volatile i32 18, ptr %reg12, align 4116 store volatile i32 19, ptr %reg13, align 4117 store volatile i32 20, ptr %reg14, align 4118 %0 = load volatile i32, ptr %reg0, align 4119 %1 = load volatile i32, ptr %reg1, align 4120 %2 = load volatile i32, ptr %reg2, align 4121 %3 = load volatile i32, ptr %reg3, align 4122 %4 = load volatile i32, ptr %reg4, align 4123 %5 = load volatile i32, ptr %reg5, align 4124 %6 = load volatile i32, ptr %reg6, align 4125 %7 = load volatile i32, ptr %reg7, align 4126 %8 = load volatile i32, ptr %reg8, align 4127 %9 = load volatile i32, ptr %reg9, align 4128 %10 = load volatile i32, ptr %reg10, align 4129 %11 = load volatile i32, ptr %reg11, align 4130 %12 = load volatile i32, ptr %reg12, align 4131 %13 = load volatile i32, ptr %reg13, align 4132 %14 = load volatile i32, ptr %reg14, align 4133 %15 = call { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } asm "nop", "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,~{dirflag},~{fpsr},~{flags}"(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, i32 %8, i32 %9, i32 %10, i32 %11, i32 %12, i32 %13, i32 %14) #1134 %asmresult = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %15, 0135 %asmresult1 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %15, 1136 %asmresult2 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %15, 2137 %asmresult3 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %15, 3138 %asmresult4 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %15, 4139 %asmresult5 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %15, 5140 %asmresult6 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %15, 6141 %asmresult7 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %15, 7142 %asmresult8 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %15, 8143 %asmresult9 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %15, 9144 %asmresult10 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %15, 10145 %asmresult11 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %15, 11146 %asmresult12 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %15, 12147 %asmresult13 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %15, 13148 %asmresult14 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %15, 14149 store volatile i32 %asmresult, ptr %reg0, align 4150 store volatile i32 %asmresult1, ptr %reg1, align 4151 store volatile i32 %asmresult2, ptr %reg2, align 4152 store volatile i32 %asmresult3, ptr %reg3, align 4153 store volatile i32 %asmresult4, ptr %reg4, align 4154 store volatile i32 %asmresult5, ptr %reg5, align 4155 store volatile i32 %asmresult6, ptr %reg6, align 4156 store volatile i32 %asmresult7, ptr %reg7, align 4157 store volatile i32 %asmresult8, ptr %reg8, align 4158 store volatile i32 %asmresult9, ptr %reg9, align 4159 store volatile i32 %asmresult10, ptr %reg10, align 4160 store volatile i32 %asmresult11, ptr %reg11, align 4161 store volatile i32 %asmresult12, ptr %reg12, align 4162 store volatile i32 %asmresult13, ptr %reg13, align 4163 store volatile i32 %asmresult14, ptr %reg14, align 4164 ret i32 0165}166 167define i32 @test_non_leaf_no_reserve() "frame-pointer"="non-leaf-no-reserve" {168; CHECK-LABEL: test_non_leaf_no_reserve:169; CHECK: # %bb.0: # %entry170; CHECK-NEXT: pushq %rbp171; CHECK-NEXT: .cfi_def_cfa_offset 16172; CHECK-NEXT: pushq %r15173; CHECK-NEXT: .cfi_def_cfa_offset 24174; CHECK-NEXT: pushq %r14175; CHECK-NEXT: .cfi_def_cfa_offset 32176; CHECK-NEXT: pushq %r13177; CHECK-NEXT: .cfi_def_cfa_offset 40178; CHECK-NEXT: pushq %r12179; CHECK-NEXT: .cfi_def_cfa_offset 48180; CHECK-NEXT: pushq %rbx181; CHECK-NEXT: .cfi_def_cfa_offset 56182; CHECK-NEXT: .cfi_offset %rbx, -56183; CHECK-NEXT: .cfi_offset %r12, -48184; CHECK-NEXT: .cfi_offset %r13, -40185; CHECK-NEXT: .cfi_offset %r14, -32186; CHECK-NEXT: .cfi_offset %r15, -24187; CHECK-NEXT: .cfi_offset %rbp, -16188; CHECK-NEXT: movl $0, -{{[0-9]+}}(%rsp)189; CHECK-NEXT: movl $1, -{{[0-9]+}}(%rsp)190; CHECK-NEXT: movl $2, -{{[0-9]+}}(%rsp)191; CHECK-NEXT: movl $3, -{{[0-9]+}}(%rsp)192; CHECK-NEXT: movl $4, -{{[0-9]+}}(%rsp)193; CHECK-NEXT: movl $5, -{{[0-9]+}}(%rsp)194; CHECK-NEXT: movl $6, -{{[0-9]+}}(%rsp)195; CHECK-NEXT: movl $7, -{{[0-9]+}}(%rsp)196; CHECK-NEXT: movl $8, -{{[0-9]+}}(%rsp)197; CHECK-NEXT: movl $9, -{{[0-9]+}}(%rsp)198; CHECK-NEXT: movl $16, -{{[0-9]+}}(%rsp)199; CHECK-NEXT: movl $17, -{{[0-9]+}}(%rsp)200; CHECK-NEXT: movl $18, -{{[0-9]+}}(%rsp)201; CHECK-NEXT: movl $19, -{{[0-9]+}}(%rsp)202; CHECK-NEXT: movl $20, -{{[0-9]+}}(%rsp)203; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax204; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %ecx205; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %edx206; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %esi207; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %edi208; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %r8d209; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %r9d210; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %r10d211; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %r11d212; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %ebx213; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %ebp214; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %r14d215; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %r15d216; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %r12d217; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %r13d218; CHECK-NEXT: #APP219; CHECK-NEXT: nop220; CHECK-NEXT: #NO_APP221; CHECK-NEXT: movl %eax, -{{[0-9]+}}(%rsp)222; CHECK-NEXT: movl %ecx, -{{[0-9]+}}(%rsp)223; CHECK-NEXT: movl %edx, -{{[0-9]+}}(%rsp)224; CHECK-NEXT: movl %esi, -{{[0-9]+}}(%rsp)225; CHECK-NEXT: movl %edi, -{{[0-9]+}}(%rsp)226; CHECK-NEXT: movl %r8d, -{{[0-9]+}}(%rsp)227; CHECK-NEXT: movl %r9d, -{{[0-9]+}}(%rsp)228; CHECK-NEXT: movl %r10d, -{{[0-9]+}}(%rsp)229; CHECK-NEXT: movl %r11d, -{{[0-9]+}}(%rsp)230; CHECK-NEXT: movl %ebx, -{{[0-9]+}}(%rsp)231; CHECK-NEXT: movl %ebp, -{{[0-9]+}}(%rsp)232; CHECK-NEXT: movl %r14d, -{{[0-9]+}}(%rsp)233; CHECK-NEXT: movl %r15d, -{{[0-9]+}}(%rsp)234; CHECK-NEXT: movl %r12d, -{{[0-9]+}}(%rsp)235; CHECK-NEXT: movl %r13d, -{{[0-9]+}}(%rsp)236; CHECK-NEXT: xorl %eax, %eax237; CHECK-NEXT: popq %rbx238; CHECK-NEXT: .cfi_def_cfa_offset 48239; CHECK-NEXT: popq %r12240; CHECK-NEXT: .cfi_def_cfa_offset 40241; CHECK-NEXT: popq %r13242; CHECK-NEXT: .cfi_def_cfa_offset 32243; CHECK-NEXT: popq %r14244; CHECK-NEXT: .cfi_def_cfa_offset 24245; CHECK-NEXT: popq %r15246; CHECK-NEXT: .cfi_def_cfa_offset 16247; CHECK-NEXT: popq %rbp248; CHECK-NEXT: .cfi_def_cfa_offset 8249; CHECK-NEXT: retq250entry:251 %reg0 = alloca i32, align 4252 %reg1 = alloca i32, align 4253 %reg2 = alloca i32, align 4254 %reg3 = alloca i32, align 4255 %reg4 = alloca i32, align 4256 %reg5 = alloca i32, align 4257 %reg6 = alloca i32, align 4258 %reg7 = alloca i32, align 4259 %reg8 = alloca i32, align 4260 %reg9 = alloca i32, align 4261 %reg10 = alloca i32, align 4262 %reg11 = alloca i32, align 4263 %reg12 = alloca i32, align 4264 %reg13 = alloca i32, align 4265 %reg14 = alloca i32, align 4266 store volatile i32 0, ptr %reg0, align 4267 store volatile i32 1, ptr %reg1, align 4268 store volatile i32 2, ptr %reg2, align 4269 store volatile i32 3, ptr %reg3, align 4270 store volatile i32 4, ptr %reg4, align 4271 store volatile i32 5, ptr %reg5, align 4272 store volatile i32 6, ptr %reg6, align 4273 store volatile i32 7, ptr %reg7, align 4274 store volatile i32 8, ptr %reg8, align 4275 store volatile i32 9, ptr %reg9, align 4276 store volatile i32 16, ptr %reg10, align 4277 store volatile i32 17, ptr %reg11, align 4278 store volatile i32 18, ptr %reg12, align 4279 store volatile i32 19, ptr %reg13, align 4280 store volatile i32 20, ptr %reg14, align 4281 %0 = load volatile i32, ptr %reg0, align 4282 %1 = load volatile i32, ptr %reg1, align 4283 %2 = load volatile i32, ptr %reg2, align 4284 %3 = load volatile i32, ptr %reg3, align 4285 %4 = load volatile i32, ptr %reg4, align 4286 %5 = load volatile i32, ptr %reg5, align 4287 %6 = load volatile i32, ptr %reg6, align 4288 %7 = load volatile i32, ptr %reg7, align 4289 %8 = load volatile i32, ptr %reg8, align 4290 %9 = load volatile i32, ptr %reg9, align 4291 %10 = load volatile i32, ptr %reg10, align 4292 %11 = load volatile i32, ptr %reg11, align 4293 %12 = load volatile i32, ptr %reg12, align 4294 %13 = load volatile i32, ptr %reg13, align 4295 %14 = load volatile i32, ptr %reg14, align 4296 %15 = call { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } asm "nop", "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,~{dirflag},~{fpsr},~{flags}"(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, i32 %8, i32 %9, i32 %10, i32 %11, i32 %12, i32 %13, i32 %14) #1297 %asmresult = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %15, 0298 %asmresult1 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %15, 1299 %asmresult2 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %15, 2300 %asmresult3 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %15, 3301 %asmresult4 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %15, 4302 %asmresult5 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %15, 5303 %asmresult6 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %15, 6304 %asmresult7 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %15, 7305 %asmresult8 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %15, 8306 %asmresult9 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %15, 9307 %asmresult10 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %15, 10308 %asmresult11 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %15, 11309 %asmresult12 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %15, 12310 %asmresult13 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %15, 13311 %asmresult14 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %15, 14312 store volatile i32 %asmresult, ptr %reg0, align 4313 store volatile i32 %asmresult1, ptr %reg1, align 4314 store volatile i32 %asmresult2, ptr %reg2, align 4315 store volatile i32 %asmresult3, ptr %reg3, align 4316 store volatile i32 %asmresult4, ptr %reg4, align 4317 store volatile i32 %asmresult5, ptr %reg5, align 4318 store volatile i32 %asmresult6, ptr %reg6, align 4319 store volatile i32 %asmresult7, ptr %reg7, align 4320 store volatile i32 %asmresult8, ptr %reg8, align 4321 store volatile i32 %asmresult9, ptr %reg9, align 4322 store volatile i32 %asmresult10, ptr %reg10, align 4323 store volatile i32 %asmresult11, ptr %reg11, align 4324 store volatile i32 %asmresult12, ptr %reg12, align 4325 store volatile i32 %asmresult13, ptr %reg13, align 4326 store volatile i32 %asmresult14, ptr %reg14, align 4327 ret i32 0328}329 330define i32 @test_non_leaf() "frame-pointer"="non-leaf" {331; CHECK-LABEL: test_non_leaf:332; CHECK: # %bb.0: # %entry333; CHECK-NEXT: pushq %r15334; CHECK-NEXT: .cfi_def_cfa_offset 16335; CHECK-NEXT: pushq %r14336; CHECK-NEXT: .cfi_def_cfa_offset 24337; CHECK-NEXT: pushq %r13338; CHECK-NEXT: .cfi_def_cfa_offset 32339; CHECK-NEXT: pushq %r12340; CHECK-NEXT: .cfi_def_cfa_offset 40341; CHECK-NEXT: pushq %rbx342; CHECK-NEXT: .cfi_def_cfa_offset 48343; CHECK-NEXT: .cfi_offset %rbx, -48344; CHECK-NEXT: .cfi_offset %r12, -40345; CHECK-NEXT: .cfi_offset %r13, -32346; CHECK-NEXT: .cfi_offset %r14, -24347; CHECK-NEXT: .cfi_offset %r15, -16348; CHECK-NEXT: movl $0, -{{[0-9]+}}(%rsp)349; CHECK-NEXT: movl $1, -{{[0-9]+}}(%rsp)350; CHECK-NEXT: movl $2, -{{[0-9]+}}(%rsp)351; CHECK-NEXT: movl $3, -{{[0-9]+}}(%rsp)352; CHECK-NEXT: movl $4, -{{[0-9]+}}(%rsp)353; CHECK-NEXT: movl $5, -{{[0-9]+}}(%rsp)354; CHECK-NEXT: movl $6, -{{[0-9]+}}(%rsp)355; CHECK-NEXT: movl $7, -{{[0-9]+}}(%rsp)356; CHECK-NEXT: movl $8, -{{[0-9]+}}(%rsp)357; CHECK-NEXT: movl $9, -{{[0-9]+}}(%rsp)358; CHECK-NEXT: movl $16, -{{[0-9]+}}(%rsp)359; CHECK-NEXT: movl $17, -{{[0-9]+}}(%rsp)360; CHECK-NEXT: movl $18, -{{[0-9]+}}(%rsp)361; CHECK-NEXT: movl $19, -{{[0-9]+}}(%rsp)362; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax363; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %ecx364; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %edx365; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %esi366; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %edi367; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %r8d368; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %r9d369; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %r10d370; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %r11d371; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %ebx372; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %r14d373; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %r15d374; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %r12d375; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %r13d376; CHECK-NEXT: #APP377; CHECK-NEXT: nop378; CHECK-NEXT: #NO_APP379; CHECK-NEXT: movl %eax, -{{[0-9]+}}(%rsp)380; CHECK-NEXT: movl %ecx, -{{[0-9]+}}(%rsp)381; CHECK-NEXT: movl %edx, -{{[0-9]+}}(%rsp)382; CHECK-NEXT: movl %esi, -{{[0-9]+}}(%rsp)383; CHECK-NEXT: movl %edi, -{{[0-9]+}}(%rsp)384; CHECK-NEXT: movl %r8d, -{{[0-9]+}}(%rsp)385; CHECK-NEXT: movl %r9d, -{{[0-9]+}}(%rsp)386; CHECK-NEXT: movl %r10d, -{{[0-9]+}}(%rsp)387; CHECK-NEXT: movl %r11d, -{{[0-9]+}}(%rsp)388; CHECK-NEXT: movl %ebx, -{{[0-9]+}}(%rsp)389; CHECK-NEXT: movl %r14d, -{{[0-9]+}}(%rsp)390; CHECK-NEXT: movl %r15d, -{{[0-9]+}}(%rsp)391; CHECK-NEXT: movl %r12d, -{{[0-9]+}}(%rsp)392; CHECK-NEXT: movl %r13d, -{{[0-9]+}}(%rsp)393; CHECK-NEXT: xorl %eax, %eax394; CHECK-NEXT: popq %rbx395; CHECK-NEXT: .cfi_def_cfa_offset 40396; CHECK-NEXT: popq %r12397; CHECK-NEXT: .cfi_def_cfa_offset 32398; CHECK-NEXT: popq %r13399; CHECK-NEXT: .cfi_def_cfa_offset 24400; CHECK-NEXT: popq %r14401; CHECK-NEXT: .cfi_def_cfa_offset 16402; CHECK-NEXT: popq %r15403; CHECK-NEXT: .cfi_def_cfa_offset 8404; CHECK-NEXT: retq405entry:406 %reg0 = alloca i32, align 4407 %reg1 = alloca i32, align 4408 %reg2 = alloca i32, align 4409 %reg3 = alloca i32, align 4410 %reg4 = alloca i32, align 4411 %reg5 = alloca i32, align 4412 %reg6 = alloca i32, align 4413 %reg7 = alloca i32, align 4414 %reg8 = alloca i32, align 4415 %reg9 = alloca i32, align 4416 %reg10 = alloca i32, align 4417 %reg11 = alloca i32, align 4418 %reg12 = alloca i32, align 4419 %reg13 = alloca i32, align 4420 store volatile i32 0, ptr %reg0, align 4421 store volatile i32 1, ptr %reg1, align 4422 store volatile i32 2, ptr %reg2, align 4423 store volatile i32 3, ptr %reg3, align 4424 store volatile i32 4, ptr %reg4, align 4425 store volatile i32 5, ptr %reg5, align 4426 store volatile i32 6, ptr %reg6, align 4427 store volatile i32 7, ptr %reg7, align 4428 store volatile i32 8, ptr %reg8, align 4429 store volatile i32 9, ptr %reg9, align 4430 store volatile i32 16, ptr %reg10, align 4431 store volatile i32 17, ptr %reg11, align 4432 store volatile i32 18, ptr %reg12, align 4433 store volatile i32 19, ptr %reg13, align 4434 %0 = load volatile i32, ptr %reg0, align 4435 %1 = load volatile i32, ptr %reg1, align 4436 %2 = load volatile i32, ptr %reg2, align 4437 %3 = load volatile i32, ptr %reg3, align 4438 %4 = load volatile i32, ptr %reg4, align 4439 %5 = load volatile i32, ptr %reg5, align 4440 %6 = load volatile i32, ptr %reg6, align 4441 %7 = load volatile i32, ptr %reg7, align 4442 %8 = load volatile i32, ptr %reg8, align 4443 %9 = load volatile i32, ptr %reg9, align 4444 %10 = load volatile i32, ptr %reg10, align 4445 %11 = load volatile i32, ptr %reg11, align 4446 %12 = load volatile i32, ptr %reg12, align 4447 %13 = load volatile i32, ptr %reg13, align 4448 %14 = call { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } asm "nop", "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,0,1,2,3,4,5,6,7,8,9,10,11,12,13,~{dirflag},~{fpsr},~{flags}"(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, i32 %8, i32 %9, i32 %10, i32 %11, i32 %12, i32 %13) #1449 %asmresult = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %14, 0450 %asmresult1 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %14, 1451 %asmresult2 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %14, 2452 %asmresult3 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %14, 3453 %asmresult4 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %14, 4454 %asmresult5 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %14, 5455 %asmresult6 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %14, 6456 %asmresult7 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %14, 7457 %asmresult8 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %14, 8458 %asmresult9 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %14, 9459 %asmresult10 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %14, 10460 %asmresult11 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %14, 11461 %asmresult12 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %14, 12462 %asmresult13 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %14, 13463 store volatile i32 %asmresult, ptr %reg0, align 4464 store volatile i32 %asmresult1, ptr %reg1, align 4465 store volatile i32 %asmresult2, ptr %reg2, align 4466 store volatile i32 %asmresult3, ptr %reg3, align 4467 store volatile i32 %asmresult4, ptr %reg4, align 4468 store volatile i32 %asmresult5, ptr %reg5, align 4469 store volatile i32 %asmresult6, ptr %reg6, align 4470 store volatile i32 %asmresult7, ptr %reg7, align 4471 store volatile i32 %asmresult8, ptr %reg8, align 4472 store volatile i32 %asmresult9, ptr %reg9, align 4473 store volatile i32 %asmresult10, ptr %reg10, align 4474 store volatile i32 %asmresult11, ptr %reg11, align 4475 store volatile i32 %asmresult12, ptr %reg12, align 4476 store volatile i32 %asmresult13, ptr %reg13, align 4477 ret i32 0478}479 480define i32 @test_reserved() "frame-pointer"="reserved" {481; CHECK-LABEL: test_reserved:482; CHECK: # %bb.0: # %entry483; CHECK-NEXT: pushq %r15484; CHECK-NEXT: .cfi_def_cfa_offset 16485; CHECK-NEXT: pushq %r14486; CHECK-NEXT: .cfi_def_cfa_offset 24487; CHECK-NEXT: pushq %r13488; CHECK-NEXT: .cfi_def_cfa_offset 32489; CHECK-NEXT: pushq %r12490; CHECK-NEXT: .cfi_def_cfa_offset 40491; CHECK-NEXT: pushq %rbx492; CHECK-NEXT: .cfi_def_cfa_offset 48493; CHECK-NEXT: .cfi_offset %rbx, -48494; CHECK-NEXT: .cfi_offset %r12, -40495; CHECK-NEXT: .cfi_offset %r13, -32496; CHECK-NEXT: .cfi_offset %r14, -24497; CHECK-NEXT: .cfi_offset %r15, -16498; CHECK-NEXT: movl $0, -{{[0-9]+}}(%rsp)499; CHECK-NEXT: movl $1, -{{[0-9]+}}(%rsp)500; CHECK-NEXT: movl $2, -{{[0-9]+}}(%rsp)501; CHECK-NEXT: movl $3, -{{[0-9]+}}(%rsp)502; CHECK-NEXT: movl $4, -{{[0-9]+}}(%rsp)503; CHECK-NEXT: movl $5, -{{[0-9]+}}(%rsp)504; CHECK-NEXT: movl $6, -{{[0-9]+}}(%rsp)505; CHECK-NEXT: movl $7, -{{[0-9]+}}(%rsp)506; CHECK-NEXT: movl $8, -{{[0-9]+}}(%rsp)507; CHECK-NEXT: movl $9, -{{[0-9]+}}(%rsp)508; CHECK-NEXT: movl $16, -{{[0-9]+}}(%rsp)509; CHECK-NEXT: movl $17, -{{[0-9]+}}(%rsp)510; CHECK-NEXT: movl $18, -{{[0-9]+}}(%rsp)511; CHECK-NEXT: movl $19, -{{[0-9]+}}(%rsp)512; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax513; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %ecx514; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %edx515; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %esi516; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %edi517; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %r8d518; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %r9d519; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %r10d520; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %r11d521; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %ebx522; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %r14d523; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %r15d524; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %r12d525; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %r13d526; CHECK-NEXT: #APP527; CHECK-NEXT: nop528; CHECK-NEXT: #NO_APP529; CHECK-NEXT: movl %eax, -{{[0-9]+}}(%rsp)530; CHECK-NEXT: movl %ecx, -{{[0-9]+}}(%rsp)531; CHECK-NEXT: movl %edx, -{{[0-9]+}}(%rsp)532; CHECK-NEXT: movl %esi, -{{[0-9]+}}(%rsp)533; CHECK-NEXT: movl %edi, -{{[0-9]+}}(%rsp)534; CHECK-NEXT: movl %r8d, -{{[0-9]+}}(%rsp)535; CHECK-NEXT: movl %r9d, -{{[0-9]+}}(%rsp)536; CHECK-NEXT: movl %r10d, -{{[0-9]+}}(%rsp)537; CHECK-NEXT: movl %r11d, -{{[0-9]+}}(%rsp)538; CHECK-NEXT: movl %ebx, -{{[0-9]+}}(%rsp)539; CHECK-NEXT: movl %r14d, -{{[0-9]+}}(%rsp)540; CHECK-NEXT: movl %r15d, -{{[0-9]+}}(%rsp)541; CHECK-NEXT: movl %r12d, -{{[0-9]+}}(%rsp)542; CHECK-NEXT: movl %r13d, -{{[0-9]+}}(%rsp)543; CHECK-NEXT: xorl %eax, %eax544; CHECK-NEXT: popq %rbx545; CHECK-NEXT: .cfi_def_cfa_offset 40546; CHECK-NEXT: popq %r12547; CHECK-NEXT: .cfi_def_cfa_offset 32548; CHECK-NEXT: popq %r13549; CHECK-NEXT: .cfi_def_cfa_offset 24550; CHECK-NEXT: popq %r14551; CHECK-NEXT: .cfi_def_cfa_offset 16552; CHECK-NEXT: popq %r15553; CHECK-NEXT: .cfi_def_cfa_offset 8554; CHECK-NEXT: retq555entry:556 %reg0 = alloca i32, align 4557 %reg1 = alloca i32, align 4558 %reg2 = alloca i32, align 4559 %reg3 = alloca i32, align 4560 %reg4 = alloca i32, align 4561 %reg5 = alloca i32, align 4562 %reg6 = alloca i32, align 4563 %reg7 = alloca i32, align 4564 %reg8 = alloca i32, align 4565 %reg9 = alloca i32, align 4566 %reg10 = alloca i32, align 4567 %reg11 = alloca i32, align 4568 %reg12 = alloca i32, align 4569 %reg13 = alloca i32, align 4570 store volatile i32 0, ptr %reg0, align 4571 store volatile i32 1, ptr %reg1, align 4572 store volatile i32 2, ptr %reg2, align 4573 store volatile i32 3, ptr %reg3, align 4574 store volatile i32 4, ptr %reg4, align 4575 store volatile i32 5, ptr %reg5, align 4576 store volatile i32 6, ptr %reg6, align 4577 store volatile i32 7, ptr %reg7, align 4578 store volatile i32 8, ptr %reg8, align 4579 store volatile i32 9, ptr %reg9, align 4580 store volatile i32 16, ptr %reg10, align 4581 store volatile i32 17, ptr %reg11, align 4582 store volatile i32 18, ptr %reg12, align 4583 store volatile i32 19, ptr %reg13, align 4584 %0 = load volatile i32, ptr %reg0, align 4585 %1 = load volatile i32, ptr %reg1, align 4586 %2 = load volatile i32, ptr %reg2, align 4587 %3 = load volatile i32, ptr %reg3, align 4588 %4 = load volatile i32, ptr %reg4, align 4589 %5 = load volatile i32, ptr %reg5, align 4590 %6 = load volatile i32, ptr %reg6, align 4591 %7 = load volatile i32, ptr %reg7, align 4592 %8 = load volatile i32, ptr %reg8, align 4593 %9 = load volatile i32, ptr %reg9, align 4594 %10 = load volatile i32, ptr %reg10, align 4595 %11 = load volatile i32, ptr %reg11, align 4596 %12 = load volatile i32, ptr %reg12, align 4597 %13 = load volatile i32, ptr %reg13, align 4598 %14 = call { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } asm "nop", "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,0,1,2,3,4,5,6,7,8,9,10,11,12,13,~{dirflag},~{fpsr},~{flags}"(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, i32 %8, i32 %9, i32 %10, i32 %11, i32 %12, i32 %13) #1599 %asmresult = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %14, 0600 %asmresult1 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %14, 1601 %asmresult2 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %14, 2602 %asmresult3 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %14, 3603 %asmresult4 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %14, 4604 %asmresult5 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %14, 5605 %asmresult6 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %14, 6606 %asmresult7 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %14, 7607 %asmresult8 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %14, 8608 %asmresult9 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %14, 9609 %asmresult10 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %14, 10610 %asmresult11 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %14, 11611 %asmresult12 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %14, 12612 %asmresult13 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %14, 13613 store volatile i32 %asmresult, ptr %reg0, align 4614 store volatile i32 %asmresult1, ptr %reg1, align 4615 store volatile i32 %asmresult2, ptr %reg2, align 4616 store volatile i32 %asmresult3, ptr %reg3, align 4617 store volatile i32 %asmresult4, ptr %reg4, align 4618 store volatile i32 %asmresult5, ptr %reg5, align 4619 store volatile i32 %asmresult6, ptr %reg6, align 4620 store volatile i32 %asmresult7, ptr %reg7, align 4621 store volatile i32 %asmresult8, ptr %reg8, align 4622 store volatile i32 %asmresult9, ptr %reg9, align 4623 store volatile i32 %asmresult10, ptr %reg10, align 4624 store volatile i32 %asmresult11, ptr %reg11, align 4625 store volatile i32 %asmresult12, ptr %reg12, align 4626 store volatile i32 %asmresult13, ptr %reg13, align 4627 ret i32 0628}629 630define i32 @test_all() "frame-pointer"="all" {631; CHECK-LABEL: test_all:632; CHECK: # %bb.0: # %entry633; CHECK-NEXT: pushq %rbp634; CHECK-NEXT: .cfi_def_cfa_offset 16635; CHECK-NEXT: .cfi_offset %rbp, -16636; CHECK-NEXT: movq %rsp, %rbp637; CHECK-NEXT: .cfi_def_cfa_register %rbp638; CHECK-NEXT: pushq %r15639; CHECK-NEXT: pushq %r14640; CHECK-NEXT: pushq %r13641; CHECK-NEXT: pushq %r12642; CHECK-NEXT: pushq %rbx643; CHECK-NEXT: .cfi_offset %rbx, -56644; CHECK-NEXT: .cfi_offset %r12, -48645; CHECK-NEXT: .cfi_offset %r13, -40646; CHECK-NEXT: .cfi_offset %r14, -32647; CHECK-NEXT: .cfi_offset %r15, -24648; CHECK-NEXT: movl $0, -96(%rbp)649; CHECK-NEXT: movl $1, -92(%rbp)650; CHECK-NEXT: movl $2, -88(%rbp)651; CHECK-NEXT: movl $3, -84(%rbp)652; CHECK-NEXT: movl $4, -80(%rbp)653; CHECK-NEXT: movl $5, -76(%rbp)654; CHECK-NEXT: movl $6, -72(%rbp)655; CHECK-NEXT: movl $7, -68(%rbp)656; CHECK-NEXT: movl $8, -64(%rbp)657; CHECK-NEXT: movl $9, -60(%rbp)658; CHECK-NEXT: movl $16, -56(%rbp)659; CHECK-NEXT: movl $17, -52(%rbp)660; CHECK-NEXT: movl $18, -48(%rbp)661; CHECK-NEXT: movl $19, -44(%rbp)662; CHECK-NEXT: movl -96(%rbp), %eax663; CHECK-NEXT: movl -92(%rbp), %ecx664; CHECK-NEXT: movl -88(%rbp), %edx665; CHECK-NEXT: movl -84(%rbp), %esi666; CHECK-NEXT: movl -80(%rbp), %edi667; CHECK-NEXT: movl -76(%rbp), %r8d668; CHECK-NEXT: movl -72(%rbp), %r9d669; CHECK-NEXT: movl -68(%rbp), %r10d670; CHECK-NEXT: movl -64(%rbp), %r11d671; CHECK-NEXT: movl -60(%rbp), %ebx672; CHECK-NEXT: movl -56(%rbp), %r14d673; CHECK-NEXT: movl -52(%rbp), %r15d674; CHECK-NEXT: movl -48(%rbp), %r12d675; CHECK-NEXT: movl -44(%rbp), %r13d676; CHECK-NEXT: #APP677; CHECK-NEXT: nop678; CHECK-NEXT: #NO_APP679; CHECK-NEXT: movl %eax, -96(%rbp)680; CHECK-NEXT: movl %ecx, -92(%rbp)681; CHECK-NEXT: movl %edx, -88(%rbp)682; CHECK-NEXT: movl %esi, -84(%rbp)683; CHECK-NEXT: movl %edi, -80(%rbp)684; CHECK-NEXT: movl %r8d, -76(%rbp)685; CHECK-NEXT: movl %r9d, -72(%rbp)686; CHECK-NEXT: movl %r10d, -68(%rbp)687; CHECK-NEXT: movl %r11d, -64(%rbp)688; CHECK-NEXT: movl %ebx, -60(%rbp)689; CHECK-NEXT: movl %r14d, -56(%rbp)690; CHECK-NEXT: movl %r15d, -52(%rbp)691; CHECK-NEXT: movl %r12d, -48(%rbp)692; CHECK-NEXT: movl %r13d, -44(%rbp)693; CHECK-NEXT: xorl %eax, %eax694; CHECK-NEXT: popq %rbx695; CHECK-NEXT: popq %r12696; CHECK-NEXT: popq %r13697; CHECK-NEXT: popq %r14698; CHECK-NEXT: popq %r15699; CHECK-NEXT: popq %rbp700; CHECK-NEXT: .cfi_def_cfa %rsp, 8701; CHECK-NEXT: retq702entry:703 %reg0 = alloca i32, align 4704 %reg1 = alloca i32, align 4705 %reg2 = alloca i32, align 4706 %reg3 = alloca i32, align 4707 %reg4 = alloca i32, align 4708 %reg5 = alloca i32, align 4709 %reg6 = alloca i32, align 4710 %reg7 = alloca i32, align 4711 %reg8 = alloca i32, align 4712 %reg9 = alloca i32, align 4713 %reg10 = alloca i32, align 4714 %reg11 = alloca i32, align 4715 %reg12 = alloca i32, align 4716 %reg13 = alloca i32, align 4717 store volatile i32 0, ptr %reg0, align 4718 store volatile i32 1, ptr %reg1, align 4719 store volatile i32 2, ptr %reg2, align 4720 store volatile i32 3, ptr %reg3, align 4721 store volatile i32 4, ptr %reg4, align 4722 store volatile i32 5, ptr %reg5, align 4723 store volatile i32 6, ptr %reg6, align 4724 store volatile i32 7, ptr %reg7, align 4725 store volatile i32 8, ptr %reg8, align 4726 store volatile i32 9, ptr %reg9, align 4727 store volatile i32 16, ptr %reg10, align 4728 store volatile i32 17, ptr %reg11, align 4729 store volatile i32 18, ptr %reg12, align 4730 store volatile i32 19, ptr %reg13, align 4731 %0 = load volatile i32, ptr %reg0, align 4732 %1 = load volatile i32, ptr %reg1, align 4733 %2 = load volatile i32, ptr %reg2, align 4734 %3 = load volatile i32, ptr %reg3, align 4735 %4 = load volatile i32, ptr %reg4, align 4736 %5 = load volatile i32, ptr %reg5, align 4737 %6 = load volatile i32, ptr %reg6, align 4738 %7 = load volatile i32, ptr %reg7, align 4739 %8 = load volatile i32, ptr %reg8, align 4740 %9 = load volatile i32, ptr %reg9, align 4741 %10 = load volatile i32, ptr %reg10, align 4742 %11 = load volatile i32, ptr %reg11, align 4743 %12 = load volatile i32, ptr %reg12, align 4744 %13 = load volatile i32, ptr %reg13, align 4745 %14 = call { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } asm "nop", "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,0,1,2,3,4,5,6,7,8,9,10,11,12,13,~{dirflag},~{fpsr},~{flags}"(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, i32 %8, i32 %9, i32 %10, i32 %11, i32 %12, i32 %13) #1746 %asmresult = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %14, 0747 %asmresult1 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %14, 1748 %asmresult2 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %14, 2749 %asmresult3 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %14, 3750 %asmresult4 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %14, 4751 %asmresult5 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %14, 5752 %asmresult6 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %14, 6753 %asmresult7 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %14, 7754 %asmresult8 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %14, 8755 %asmresult9 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %14, 9756 %asmresult10 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %14, 10757 %asmresult11 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %14, 11758 %asmresult12 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %14, 12759 %asmresult13 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %14, 13760 store volatile i32 %asmresult, ptr %reg0, align 4761 store volatile i32 %asmresult1, ptr %reg1, align 4762 store volatile i32 %asmresult2, ptr %reg2, align 4763 store volatile i32 %asmresult3, ptr %reg3, align 4764 store volatile i32 %asmresult4, ptr %reg4, align 4765 store volatile i32 %asmresult5, ptr %reg5, align 4766 store volatile i32 %asmresult6, ptr %reg6, align 4767 store volatile i32 %asmresult7, ptr %reg7, align 4768 store volatile i32 %asmresult8, ptr %reg8, align 4769 store volatile i32 %asmresult9, ptr %reg9, align 4770 store volatile i32 %asmresult10, ptr %reg10, align 4771 store volatile i32 %asmresult11, ptr %reg11, align 4772 store volatile i32 %asmresult12, ptr %reg12, align 4773 store volatile i32 %asmresult13, ptr %reg13, align 4774 ret i32 0775}776