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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=x86_64-- < %s | FileCheck %s3 4; OR of two rotates of %a0(edi).5define i32 @f0(i32 %a0) #0 {6; CHECK-LABEL: f0:7; CHECK: # %bb.0: # %b08; CHECK-NEXT: movl %edi, %eax9; CHECK-NEXT: roll $7, %eax10; CHECK-NEXT: roll $9, %edi11; CHECK-NEXT: orl %edi, %eax12; CHECK-NEXT: retq13b0:14 %v0 = shl i32 %a0, 715 %v1 = lshr i32 %a0, 2516 %v2 = or i32 %v0, %v117 %v3 = shl i32 %a0, 918 %v4 = lshr i32 %a0, 2319 %v5 = or i32 %v3, %v420 %v6 = or i32 %v2, %v521 ret i32 %v622}23 24; OR of two rotates of %a0(edi) with an extra input %a1(esi).25define i32 @f1(i32 %a0, i32 %a1) #0 {26; CHECK-LABEL: f1:27; CHECK: # %bb.0: # %b028; CHECK-NEXT: movl %edi, %eax29; CHECK-NEXT: shll $7, %eax30; CHECK-NEXT: orl %esi, %eax31; CHECK-NEXT: roll $9, %edi32; CHECK-NEXT: orl %edi, %eax33; CHECK-NEXT: retq34b0:35 %v0 = shl i32 %a0, 736 %v1 = lshr i32 %a0, 2537 %v2 = or i32 %v0, %a138 %v3 = shl i32 %a0, 939 %v4 = lshr i32 %a0, 2340 %v5 = or i32 %v3, %v441 %v6 = or i32 %v2, %v542 %v7 = or i32 %v6, %v143 ret i32 %v644}45 46; OR of two rotates of two different inputs: %a0(edi) and %a1(esi).47define i32 @f2(i32 %a0, i32 %a1) #0 {48; CHECK-LABEL: f2:49; CHECK: # %bb.0:50; CHECK-NEXT: movl %edi, %ecx51; CHECK-NEXT: shll $11, %ecx52; CHECK-NEXT: shrl $21, %edi53; CHECK-NEXT: movl %esi, %eax54; CHECK-NEXT: shll $19, %eax55; CHECK-NEXT: orl %ecx, %eax56; CHECK-NEXT: shrl $13, %esi57; CHECK-NEXT: orl %edi, %esi58; CHECK-NEXT: orl %esi, %eax59; CHECK-NEXT: retq60 %v0 = shl i32 %a0, 1161 %v1 = lshr i32 %a0, 2162 %v2 = shl i32 %a1, 1963 %v3 = lshr i32 %a1, 1364 %v4 = or i32 %v0, %v265 %v5 = or i32 %v1, %v366 %v6 = or i32 %v4, %v567 ret i32 %v668}69 70; ORs of multiple shifts of the same value with only one pair actually71; matching a rotate.72define i32 @f3(i32 %a0) #0 {73; CHECK-LABEL: f3:74; CHECK: # %bb.0: # %b075; CHECK-NEXT: # kill: def $edi killed $edi def $rdi76; CHECK-NEXT: leal (,%rdi,8), %eax77; CHECK-NEXT: movl %edi, %ecx78; CHECK-NEXT: shll $5, %ecx79; CHECK-NEXT: orl %eax, %ecx80; CHECK-NEXT: movl %edi, %eax81; CHECK-NEXT: shll $7, %eax82; CHECK-NEXT: movl %edi, %edx83; CHECK-NEXT: shll $13, %edx84; CHECK-NEXT: orl %eax, %edx85; CHECK-NEXT: orl %ecx, %edx86; CHECK-NEXT: movl %edi, %eax87; CHECK-NEXT: shll $19, %eax88; CHECK-NEXT: movl %edi, %ecx89; CHECK-NEXT: shrl $2, %ecx90; CHECK-NEXT: orl %eax, %ecx91; CHECK-NEXT: movl %edi, %esi92; CHECK-NEXT: shrl $15, %esi93; CHECK-NEXT: orl %ecx, %esi94; CHECK-NEXT: orl %edx, %esi95; CHECK-NEXT: movl %edi, %ecx96; CHECK-NEXT: shrl $23, %ecx97; CHECK-NEXT: movl %edi, %eax98; CHECK-NEXT: shrl $25, %eax99; CHECK-NEXT: orl %ecx, %eax100; CHECK-NEXT: shrl $30, %edi101; CHECK-NEXT: orl %edi, %eax102; CHECK-NEXT: orl %esi, %eax103; CHECK-NEXT: retq104b0:105 %v0 = shl i32 %a0, 3106 %v1 = shl i32 %a0, 5107 %v2 = shl i32 %a0, 7 ; rotate108 %v3 = shl i32 %a0, 13109 %v4 = shl i32 %a0, 19110 %v5 = lshr i32 %a0, 2111 %v6 = lshr i32 %a0, 15112 %v7 = lshr i32 %a0, 23113 %v8 = lshr i32 %a0, 25 ; rotate114 %v9 = lshr i32 %a0, 30115 %v10 = or i32 %v0, %v1116 %v11 = or i32 %v10, %v2117 %v12 = or i32 %v11, %v3118 %v13 = or i32 %v12, %v4119 %v14 = or i32 %v13, %v5120 %v15 = or i32 %v14, %v6121 %v16 = or i32 %v15, %v7122 %v17 = or i32 %v16, %v8123 %v18 = or i32 %v17, %v9124 ret i32 %v18125}126 127attributes #0 = { readnone nounwind }128