232 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver2 | FileCheck %s --check-prefixes=CHECK,XOP,XOPAVX13; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver4 | FileCheck %s --check-prefixes=CHECK,XOP,XOPAVX24; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 | FileCheck %s --check-prefixes=CHECK,AVX5125 6define <4 x i32> @rot_v4i32_splat(<4 x i32> %x) {7; XOP-LABEL: rot_v4i32_splat:8; XOP: # %bb.0:9; XOP-NEXT: vprotd $31, %xmm0, %xmm010; XOP-NEXT: retq11;12; AVX512-LABEL: rot_v4i32_splat:13; AVX512: # %bb.0:14; AVX512-NEXT: vprold $31, %xmm0, %xmm015; AVX512-NEXT: retq16 %1 = lshr <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1>17 %2 = shl <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>18 %3 = or <4 x i32> %1, %219 ret <4 x i32> %320}21 22define <4 x i32> @rot_v4i32_non_splat(<4 x i32> %x) {23; XOP-LABEL: rot_v4i32_non_splat:24; XOP: # %bb.0:25; XOP-NEXT: vprotd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm026; XOP-NEXT: retq27;28; AVX512-LABEL: rot_v4i32_non_splat:29; AVX512: # %bb.0:30; AVX512-NEXT: vprolvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm031; AVX512-NEXT: retq32 %1 = lshr <4 x i32> %x, <i32 1, i32 2, i32 3, i32 4>33 %2 = shl <4 x i32> %x, <i32 31, i32 30, i32 29, i32 28>34 %3 = or <4 x i32> %1, %235 ret <4 x i32> %336}37 38define <4 x i32> @rot_v4i32_splat_2masks(<4 x i32> %x) {39; XOP-LABEL: rot_v4i32_splat_2masks:40; XOP: # %bb.0:41; XOP-NEXT: vprotd $31, %xmm0, %xmm042; XOP-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm043; XOP-NEXT: retq44;45; AVX512-LABEL: rot_v4i32_splat_2masks:46; AVX512: # %bb.0:47; AVX512-NEXT: vprold $31, %xmm0, %xmm048; AVX512-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm049; AVX512-NEXT: retq50 %1 = lshr <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1>51 %2 = and <4 x i32> %1, <i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760>52 53 %3 = shl <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>54 %4 = and <4 x i32> %3, <i32 0, i32 4294901760, i32 0, i32 4294901760>55 %5 = or <4 x i32> %2, %456 ret <4 x i32> %557}58 59define <4 x i32> @rot_v4i32_non_splat_2masks(<4 x i32> %x) {60; XOP-LABEL: rot_v4i32_non_splat_2masks:61; XOP: # %bb.0:62; XOP-NEXT: vprotd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm063; XOP-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm064; XOP-NEXT: retq65;66; AVX512-LABEL: rot_v4i32_non_splat_2masks:67; AVX512: # %bb.0:68; AVX512-NEXT: vprolvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm069; AVX512-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm070; AVX512-NEXT: retq71 %1 = lshr <4 x i32> %x, <i32 1, i32 2, i32 3, i32 4>72 %2 = and <4 x i32> %1, <i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760>73 74 %3 = shl <4 x i32> %x, <i32 31, i32 30, i32 29, i32 28>75 %4 = and <4 x i32> %3, <i32 0, i32 4294901760, i32 0, i32 4294901760>76 %5 = or <4 x i32> %2, %477 ret <4 x i32> %578}79 80define <4 x i32> @rot_v4i32_zero_non_splat(<4 x i32> %x) {81; XOPAVX1-LABEL: rot_v4i32_zero_non_splat:82; XOPAVX1: # %bb.0:83; XOPAVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0,0,0]84; XOPAVX1-NEXT: retq85;86; XOPAVX2-LABEL: rot_v4i32_zero_non_splat:87; XOPAVX2: # %bb.0:88; XOPAVX2-NEXT: vbroadcastss %xmm0, %xmm089; XOPAVX2-NEXT: retq90;91; AVX512-LABEL: rot_v4i32_zero_non_splat:92; AVX512: # %bb.0:93; AVX512-NEXT: vbroadcastss %xmm0, %xmm094; AVX512-NEXT: retq95 %1 = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 0, i32 1, i32 2, i32 3>)96 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> zeroinitializer97 ret <4 x i32> %298}99 100define <4 x i32> @rot_v4i32_allsignbits(<4 x i32> %x, <4 x i32> %y) {101; CHECK-LABEL: rot_v4i32_allsignbits:102; CHECK: # %bb.0:103; CHECK-NEXT: vpsrad $31, %xmm0, %xmm0104; CHECK-NEXT: retq105 %1 = ashr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>106 %2 = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %1, <4 x i32> %1, <4 x i32> %y)107 ret <4 x i32> %2108}109 110define <4 x i32> @rot_v4i32_mask_ashr0(<4 x i32> %a0) {111; XOPAVX1-LABEL: rot_v4i32_mask_ashr0:112; XOPAVX1: # %bb.0:113; XOPAVX1-NEXT: vpshad {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0114; XOPAVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0115; XOPAVX1-NEXT: retq116;117; XOPAVX2-LABEL: rot_v4i32_mask_ashr0:118; XOPAVX2: # %bb.0:119; XOPAVX2-NEXT: vpsravd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0120; XOPAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0121; XOPAVX2-NEXT: retq122;123; AVX512-LABEL: rot_v4i32_mask_ashr0:124; AVX512: # %bb.0:125; AVX512-NEXT: vpsravd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0126; AVX512-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0127; AVX512-NEXT: retq128 %1 = ashr <4 x i32> %a0, <i32 25, i32 26, i32 27, i32 28>129 %2 = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %1, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)130 %3 = ashr <4 x i32> %2, <i32 1, i32 2, i32 3, i32 4>131 %4 = and <4 x i32> %3, <i32 -32768, i32 -65536, i32 -32768, i32 -65536>132 ret <4 x i32> %4133}134 135define <4 x i32> @rot_v4i32_mask_ashr1(<4 x i32> %a0) {136; XOPAVX1-LABEL: rot_v4i32_mask_ashr1:137; XOPAVX1: # %bb.0:138; XOPAVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]139; XOPAVX1-NEXT: vpsrad $25, %xmm0, %xmm0140; XOPAVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0141; XOPAVX1-NEXT: retq142;143; XOPAVX2-LABEL: rot_v4i32_mask_ashr1:144; XOPAVX2: # %bb.0:145; XOPAVX2-NEXT: vpsrad $25, %xmm0, %xmm0146; XOPAVX2-NEXT: vpbroadcastd %xmm0, %xmm0147; XOPAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0148; XOPAVX2-NEXT: retq149;150; AVX512-LABEL: rot_v4i32_mask_ashr1:151; AVX512: # %bb.0:152; AVX512-NEXT: vpsrad $25, %xmm0, %xmm0153; AVX512-NEXT: vpbroadcastd %xmm0, %xmm0154; AVX512-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0155; AVX512-NEXT: retq156 %1 = ashr <4 x i32> %a0, <i32 25, i32 26, i32 27, i32 28>157 %2 = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %1, <4 x i32> %1, <4 x i32> <i32 1, i32 2, i32 3, i32 4>)158 %3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> zeroinitializer159 %4 = ashr <4 x i32> %3, <i32 1, i32 2, i32 3, i32 4>160 %5 = and <4 x i32> %4, <i32 -4096, i32 -8192, i32 -4096, i32 -8192>161 ret <4 x i32> %5162}163 164define <8 x i16> @or_fshl_v8i16(<8 x i16> %x, <8 x i16> %y) {165; XOP-LABEL: or_fshl_v8i16:166; XOP: # %bb.0:167; XOP-NEXT: vpor %xmm0, %xmm1, %xmm1168; XOP-NEXT: vpsrlw $11, %xmm0, %xmm0169; XOP-NEXT: vpsllw $5, %xmm1, %xmm1170; XOP-NEXT: vpor %xmm0, %xmm1, %xmm0171; XOP-NEXT: retq172;173; AVX512-LABEL: or_fshl_v8i16:174; AVX512: # %bb.0:175; AVX512-NEXT: vpor %xmm0, %xmm1, %xmm1176; AVX512-NEXT: vpsllw $5, %xmm1, %xmm1177; AVX512-NEXT: vpsrlw $11, %xmm0, %xmm0178; AVX512-NEXT: vpor %xmm0, %xmm1, %xmm0179; AVX512-NEXT: retq180 %or1 = or <8 x i16> %y, %x181 %sh1 = shl <8 x i16> %or1, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>182 %sh2 = lshr <8 x i16> %x, <i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11>183 %r = or <8 x i16> %sh2, %sh1184 ret <8 x i16> %r185}186 187define <4 x i32> @or_fshl_v4i32(<4 x i32> %x, <4 x i32> %y) {188; XOP-LABEL: or_fshl_v4i32:189; XOP: # %bb.0:190; XOP-NEXT: vpor %xmm0, %xmm1, %xmm1191; XOP-NEXT: vpsrld $11, %xmm0, %xmm0192; XOP-NEXT: vpslld $21, %xmm1, %xmm1193; XOP-NEXT: vpor %xmm0, %xmm1, %xmm0194; XOP-NEXT: retq195;196; AVX512-LABEL: or_fshl_v4i32:197; AVX512: # %bb.0:198; AVX512-NEXT: vpor %xmm0, %xmm1, %xmm1199; AVX512-NEXT: vpslld $21, %xmm1, %xmm1200; AVX512-NEXT: vpsrld $11, %xmm0, %xmm0201; AVX512-NEXT: vpor %xmm0, %xmm1, %xmm0202; AVX512-NEXT: retq203 %or1 = or <4 x i32> %y, %x204 %sh1 = shl <4 x i32> %or1, <i32 21, i32 21, i32 21, i32 21>205 %sh2 = lshr <4 x i32> %x, <i32 11, i32 11, i32 11, i32 11>206 %r = or <4 x i32> %sh2, %sh1207 ret <4 x i32> %r208}209 210define <2 x i64> @or_fshr_v2i64(<2 x i64> %x, <2 x i64> %y) {211; XOP-LABEL: or_fshr_v2i64:212; XOP: # %bb.0:213; XOP-NEXT: vpsrlq $22, %xmm1, %xmm1214; XOP-NEXT: vprotq $42, %xmm0, %xmm0215; XOP-NEXT: vpor %xmm1, %xmm0, %xmm0216; XOP-NEXT: retq217;218; AVX512-LABEL: or_fshr_v2i64:219; AVX512: # %bb.0:220; AVX512-NEXT: vpsrlq $22, %xmm1, %xmm1221; AVX512-NEXT: vprolq $42, %xmm0, %xmm0222; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0223; AVX512-NEXT: retq224 %or1 = or <2 x i64> %x, %y225 %sh1 = shl <2 x i64> %x, <i64 42, i64 42>226 %sh2 = lshr <2 x i64> %or1, <i64 22, i64 22>227 %r = or <2 x i64> %sh1, %sh2228 ret <2 x i64> %r229}230 231declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)232