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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=corei7-avx | FileCheck %s3 4define void @wideloads(ptr %a, ptr %b, ptr %c) nounwind {5; CHECK-LABEL: wideloads:6; CHECK: # %bb.0:7; CHECK-NEXT: vmovaps (%rdi), %xmm08; CHECK-NEXT: vinsertf128 $1, 16(%rdi), %ymm0, %ymm09; CHECK-NEXT: vmovaps (%rsi), %ymm110; CHECK-NEXT: vcmpltps %ymm0, %ymm1, %ymm111; CHECK-NEXT: vmovaps (%rdx), %ymm212; CHECK-NEXT: vcmpltps %ymm0, %ymm2, %ymm013; CHECK-NEXT: vandps %ymm1, %ymm0, %ymm014; CHECK-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm015; CHECK-NEXT: vmovaps %ymm0, (%rax)16; CHECK-NEXT: vzeroupper17; CHECK-NEXT: retq18 %v0 = load <8 x float>, ptr %a, align 16 ; <---- unaligned!19 %v1 = load <8 x float>, ptr %b, align 32 ; <---- aligned!20 %m0 = fcmp olt <8 x float> %v1, %v021 %v2 = load <8 x float>, ptr %c, align 32 ; <---- aligned!22 %m1 = fcmp olt <8 x float> %v2, %v023 %mand = and <8 x i1> %m1, %m024 %r = zext <8 x i1> %mand to <8 x i32>25 store <8 x i32> %r, ptr undef, align 3226 ret void27}28 29define void @widestores(ptr %a, ptr %b, ptr %c) nounwind {30; CHECK-LABEL: widestores:31; CHECK: # %bb.0:32; CHECK-NEXT: vmovaps (%rdi), %ymm033; CHECK-NEXT: vmovaps (%rsi), %ymm134; CHECK-NEXT: vmovaps %ymm0, (%rsi)35; CHECK-NEXT: vextractf128 $1, %ymm1, 16(%rdi)36; CHECK-NEXT: vmovaps %xmm1, (%rdi)37; CHECK-NEXT: vzeroupper38; CHECK-NEXT: retq39 %v0 = load <8 x float>, ptr %a, align 3240 %v1 = load <8 x float>, ptr %b, align 3241 store <8 x float> %v0, ptr %b, align 32 ; <--- aligned42 store <8 x float> %v1, ptr %a, align 16 ; <--- unaligned43 ret void44}45 46define void @widestores_unaligned_load(ptr %a, ptr %b, ptr %c) nounwind {47; CHECK-LABEL: widestores_unaligned_load:48; CHECK: # %bb.0:49; CHECK-NEXT: vmovaps (%rdi), %ymm050; CHECK-NEXT: vmovaps (%rsi), %xmm151; CHECK-NEXT: vmovaps 16(%rsi), %xmm252; CHECK-NEXT: vmovaps %ymm0, (%rsi)53; CHECK-NEXT: vmovaps %xmm2, 16(%rdi)54; CHECK-NEXT: vmovaps %xmm1, (%rdi)55; CHECK-NEXT: vzeroupper56; CHECK-NEXT: retq57 %v0 = load <8 x float>, ptr %a, align 32 ; <--- aligned58 %v1 = load <8 x float>, ptr %b, align 16 ; <--- unaligned59 store <8 x float> %v0, ptr %b, align 32 ; <--- aligned60 store <8 x float> %v1, ptr %a, align 16 ; <--- unaligned61 ret void62}63