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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=CHECK,SSE3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX14; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX25 6define i32 @shl48sar47(i64 %a) #0 {7; CHECK-LABEL: shl48sar47:8; CHECK: # %bb.0:9; CHECK-NEXT: movswl %di, %eax10; CHECK-NEXT: addl %eax, %eax11; CHECK-NEXT: retq12 %1 = shl i64 %a, 4813 %2 = ashr exact i64 %1, 4714 %3 = trunc i64 %2 to i3215 ret i32 %316}17 18define i32 @shl48sar49(i64 %a) #0 {19; CHECK-LABEL: shl48sar49:20; CHECK: # %bb.0:21; CHECK-NEXT: movswq %di, %rax22; CHECK-NEXT: shrq %rax23; CHECK-NEXT: # kill: def $eax killed $eax killed $rax24; CHECK-NEXT: retq25 %1 = shl i64 %a, 4826 %2 = ashr exact i64 %1, 4927 %3 = trunc i64 %2 to i3228 ret i32 %329}30 31define i32 @shl56sar55(i64 %a) #0 {32; CHECK-LABEL: shl56sar55:33; CHECK: # %bb.0:34; CHECK-NEXT: movsbl %dil, %eax35; CHECK-NEXT: addl %eax, %eax36; CHECK-NEXT: retq37 %1 = shl i64 %a, 5638 %2 = ashr exact i64 %1, 5539 %3 = trunc i64 %2 to i3240 ret i32 %341}42 43define i32 @shl56sar57(i64 %a) #0 {44; CHECK-LABEL: shl56sar57:45; CHECK: # %bb.0:46; CHECK-NEXT: movsbq %dil, %rax47; CHECK-NEXT: shrq %rax48; CHECK-NEXT: # kill: def $eax killed $eax killed $rax49; CHECK-NEXT: retq50 %1 = shl i64 %a, 5651 %2 = ashr exact i64 %1, 5752 %3 = trunc i64 %2 to i3253 ret i32 %354}55 56define i8 @all_sign_bit_ashr(i8 %x) {57; CHECK-LABEL: all_sign_bit_ashr:58; CHECK: # %bb.0:59; CHECK-NEXT: movl %edi, %eax60; CHECK-NEXT: andb $1, %al61; CHECK-NEXT: negb %al62; CHECK-NEXT: # kill: def $al killed $al killed $eax63; CHECK-NEXT: retq64 %and = and i8 %x, 165 %neg = sub i8 0, %and66 %sar = ashr i8 %neg, 667 ret i8 %sar68}69 70define <4 x i32> @all_sign_bit_ashr_vec0(<4 x i32> %x) {71; SSE-LABEL: all_sign_bit_ashr_vec0:72; SSE: # %bb.0:73; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm074; SSE-NEXT: pxor %xmm1, %xmm175; SSE-NEXT: psubd %xmm0, %xmm176; SSE-NEXT: movdqa %xmm1, %xmm077; SSE-NEXT: retq78;79; AVX1-LABEL: all_sign_bit_ashr_vec0:80; AVX1: # %bb.0:81; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm082; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm183; AVX1-NEXT: vpsubd %xmm0, %xmm1, %xmm084; AVX1-NEXT: retq85;86; AVX2-LABEL: all_sign_bit_ashr_vec0:87; AVX2: # %bb.0:88; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [1,1,1,1]89; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm090; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm191; AVX2-NEXT: vpsubd %xmm0, %xmm1, %xmm092; AVX2-NEXT: retq93 %and = and <4 x i32> %x, <i32 1, i32 1, i32 1 , i32 1>94 %neg = sub <4 x i32> zeroinitializer, %and95 %sar = ashr <4 x i32> %neg, <i32 1, i32 31, i32 5, i32 0>96 ret <4 x i32> %sar97}98 99define <4 x i32> @all_sign_bit_ashr_vec1(<4 x i32> %x) {100; SSE-LABEL: all_sign_bit_ashr_vec1:101; SSE: # %bb.0:102; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,0,0,0]103; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1104; SSE-NEXT: pxor %xmm0, %xmm0105; SSE-NEXT: psubd %xmm1, %xmm0106; SSE-NEXT: retq107;108; AVX1-LABEL: all_sign_bit_ashr_vec1:109; AVX1: # %bb.0:110; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]111; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0112; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1113; AVX1-NEXT: vpsubd %xmm0, %xmm1, %xmm0114; AVX1-NEXT: retq115;116; AVX2-LABEL: all_sign_bit_ashr_vec1:117; AVX2: # %bb.0:118; AVX2-NEXT: vpbroadcastd %xmm0, %xmm0119; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [1,1,1,1]120; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0121; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1122; AVX2-NEXT: vpsubd %xmm0, %xmm1, %xmm0123; AVX2-NEXT: retq124 %and = and <4 x i32> %x, <i32 1, i32 1, i32 1 , i32 1>125 %sub = sub <4 x i32> <i32 0, i32 1, i32 2, i32 3>, %and126 %shf = shufflevector <4 x i32> %sub, <4 x i32> undef, <4 x i32> zeroinitializer127 %sar = ashr <4 x i32> %shf, <i32 1, i32 31, i32 5, i32 0>128 ret <4 x i32> %sar129}130 131define <4 x i32> @all_sign_bit_ashr_vec2(<4 x i32> %x) {132; SSE-LABEL: all_sign_bit_ashr_vec2:133; SSE: # %bb.0:134; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0135; SSE-NEXT: pcmpeqd %xmm1, %xmm1136; SSE-NEXT: paddd %xmm1, %xmm0137; SSE-NEXT: retq138;139; AVX1-LABEL: all_sign_bit_ashr_vec2:140; AVX1: # %bb.0:141; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0142; AVX1-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1143; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0144; AVX1-NEXT: retq145;146; AVX2-LABEL: all_sign_bit_ashr_vec2:147; AVX2: # %bb.0:148; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [1,1,1,1]149; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0150; AVX2-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1151; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0152; AVX2-NEXT: retq153 %and = and <4 x i32> %x, <i32 1, i32 1, i32 1 , i32 1>154 %add = add <4 x i32> %and, <i32 -1, i32 -1, i32 -1, i32 -1>155 %sar = ashr <4 x i32> %add, <i32 1, i32 31, i32 5, i32 0>156 ret <4 x i32> %sar157}158 159define <4 x i32> @all_sign_bit_ashr_vec3(<4 x i32> %x) {160; SSE-LABEL: all_sign_bit_ashr_vec3:161; SSE: # %bb.0:162; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,0,0,0]163; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1164; SSE-NEXT: pcmpeqd %xmm0, %xmm0165; SSE-NEXT: paddd %xmm1, %xmm0166; SSE-NEXT: retq167;168; AVX1-LABEL: all_sign_bit_ashr_vec3:169; AVX1: # %bb.0:170; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]171; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0172; AVX1-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1173; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0174; AVX1-NEXT: retq175;176; AVX2-LABEL: all_sign_bit_ashr_vec3:177; AVX2: # %bb.0:178; AVX2-NEXT: vpbroadcastd %xmm0, %xmm0179; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [1,1,1,1]180; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0181; AVX2-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1182; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0183; AVX2-NEXT: retq184 %and = and <4 x i32> %x, <i32 1, i32 1, i32 1 , i32 1>185 %add = add <4 x i32> %and, <i32 -1, i32 1, i32 2, i32 3>186 %shf = shufflevector <4 x i32> %add, <4 x i32> undef, <4 x i32> zeroinitializer187 %sar = ashr <4 x i32> %shf, <i32 1, i32 31, i32 5, i32 0>188 ret <4 x i32> %sar189}190 191attributes #0 = { nounwind }192