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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=i686-- | FileCheck %s --check-prefixes=X863; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s --check-prefixes=X644 5; Fold and(sextinreg(v0,i5),sextinreg(v1,i5)) -> sextinreg(and(v0,v1),i5)6define i32 @sextinreg_i32(ptr %p0, ptr %p1) {7; X86-LABEL: sextinreg_i32:8; X86: # %bb.0:9; X86-NEXT: movl {{[0-9]+}}(%esp), %eax10; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx11; X86-NEXT: movzbl (%ecx), %ecx12; X86-NEXT: movzbl (%eax), %eax13; X86-NEXT: andl %ecx, %eax14; X86-NEXT: shll $27, %eax15; X86-NEXT: sarl $27, %eax16; X86-NEXT: retl17;18; X64-LABEL: sextinreg_i32:19; X64: # %bb.0:20; X64-NEXT: movzbl (%rdi), %ecx21; X64-NEXT: movzbl (%rsi), %eax22; X64-NEXT: andl %ecx, %eax23; X64-NEXT: shll $27, %eax24; X64-NEXT: sarl $27, %eax25; X64-NEXT: retq26 %v0 = load i8, ptr %p0, align 127 %v1 = load i8, ptr %p1, align 128 %x0 = zext i8 %v0 to i3229 %x1 = zext i8 %v1 to i3230 %l0 = shl i32 %x0, 2731 %l1 = shl i32 %x1, 2732 %a0 = ashr exact i32 %l0, 2733 %a1 = ashr exact i32 %l1, 2734 %and = and i32 %a0, %a135 ret i32 %and36}37 38; MISMATCH and(sextinreg(v0,i2),sextinreg(v1,i5)) != sextinreg(and(v0,v1),i2)39define i32 @sextinreg_i32_mismatch(ptr %p0, ptr %p1) {40; X86-LABEL: sextinreg_i32_mismatch:41; X86: # %bb.0:42; X86-NEXT: movl {{[0-9]+}}(%esp), %eax43; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx44; X86-NEXT: movzbl (%ecx), %ecx45; X86-NEXT: movzbl (%eax), %eax46; X86-NEXT: shll $30, %ecx47; X86-NEXT: sarl $30, %ecx48; X86-NEXT: shll $27, %eax49; X86-NEXT: sarl $27, %eax50; X86-NEXT: andl %ecx, %eax51; X86-NEXT: retl52;53; X64-LABEL: sextinreg_i32_mismatch:54; X64: # %bb.0:55; X64-NEXT: movzbl (%rdi), %ecx56; X64-NEXT: movzbl (%rsi), %eax57; X64-NEXT: shll $30, %ecx58; X64-NEXT: sarl $30, %ecx59; X64-NEXT: shll $27, %eax60; X64-NEXT: sarl $27, %eax61; X64-NEXT: andl %ecx, %eax62; X64-NEXT: retq63 %v0 = load i8, ptr %p0, align 164 %v1 = load i8, ptr %p1, align 165 %x0 = zext i8 %v0 to i3266 %x1 = zext i8 %v1 to i3267 %l0 = shl i32 %x0, 3068 %l1 = shl i32 %x1, 2769 %a0 = ashr exact i32 %l0, 3070 %a1 = ashr exact i32 %l1, 2771 %and = and i32 %a0, %a172 ret i32 %and73}74