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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2 | FileCheck %s --check-prefixes=SSE3; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX14; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=AVX,AVX5125 6define <4 x float> @fadd_op1_constant_v4f32(float %x) nounwind {7; SSE-LABEL: fadd_op1_constant_v4f32:8; SSE: # %bb.0:9; SSE-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm010; SSE-NEXT: retq11;12; AVX-LABEL: fadd_op1_constant_v4f32:13; AVX: # %bb.0:14; AVX-NEXT: vaddss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm015; AVX-NEXT: retq16 %v = insertelement <4 x float> undef, float %x, i32 017 %b = fadd <4 x float> %v, <float 42.0, float undef, float undef, float undef>18 ret <4 x float> %b19}20 21define <4 x float> @load_fadd_op1_constant_v4f32(ptr %p) nounwind {22; SSE-LABEL: load_fadd_op1_constant_v4f32:23; SSE: # %bb.0:24; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero25; SSE-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm026; SSE-NEXT: retq27;28; AVX-LABEL: load_fadd_op1_constant_v4f32:29; AVX: # %bb.0:30; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero31; AVX-NEXT: vaddss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm032; AVX-NEXT: retq33 %x = load float, ptr %p34 %v = insertelement <4 x float> undef, float %x, i32 035 %b = fadd <4 x float> %v, <float 42.0, float undef, float undef, float undef>36 ret <4 x float> %b37}38 39define <4 x float> @fsub_op0_constant_v4f32(float %x) nounwind {40; SSE-LABEL: fsub_op0_constant_v4f32:41; SSE: # %bb.0:42; SSE-NEXT: movss {{.*#+}} xmm1 = [4.2E+1,0.0E+0,0.0E+0,0.0E+0]43; SSE-NEXT: subss %xmm0, %xmm144; SSE-NEXT: movaps %xmm1, %xmm045; SSE-NEXT: retq46;47; AVX-LABEL: fsub_op0_constant_v4f32:48; AVX: # %bb.0:49; AVX-NEXT: vmovss {{.*#+}} xmm1 = [4.2E+1,0.0E+0,0.0E+0,0.0E+0]50; AVX-NEXT: vsubss %xmm0, %xmm1, %xmm051; AVX-NEXT: retq52 %v = insertelement <4 x float> undef, float %x, i32 053 %b = fsub <4 x float> <float 42.0, float undef, float undef, float undef>, %v54 ret <4 x float> %b55}56 57define <4 x float> @load_fsub_op0_constant_v4f32(ptr %p) nounwind {58; SSE-LABEL: load_fsub_op0_constant_v4f32:59; SSE: # %bb.0:60; SSE-NEXT: movss {{.*#+}} xmm0 = [4.2E+1,0.0E+0,0.0E+0,0.0E+0]61; SSE-NEXT: subss (%rdi), %xmm062; SSE-NEXT: retq63;64; AVX-LABEL: load_fsub_op0_constant_v4f32:65; AVX: # %bb.0:66; AVX-NEXT: vmovss {{.*#+}} xmm0 = [4.2E+1,0.0E+0,0.0E+0,0.0E+0]67; AVX-NEXT: vsubss (%rdi), %xmm0, %xmm068; AVX-NEXT: retq69 %x = load float, ptr %p70 %v = insertelement <4 x float> undef, float %x, i32 071 %b = fsub <4 x float> <float 42.0, float undef, float undef, float undef>, %v72 ret <4 x float> %b73}74 75define <4 x float> @fmul_op1_constant_v4f32(float %x) nounwind {76; SSE-LABEL: fmul_op1_constant_v4f32:77; SSE: # %bb.0:78; SSE-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm079; SSE-NEXT: retq80;81; AVX-LABEL: fmul_op1_constant_v4f32:82; AVX: # %bb.0:83; AVX-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm084; AVX-NEXT: retq85 %v = insertelement <4 x float> undef, float %x, i32 086 %b = fmul <4 x float> %v, <float 42.0, float undef, float undef, float undef>87 ret <4 x float> %b88}89 90define <4 x float> @load_fmul_op1_constant_v4f32(ptr %p) nounwind {91; SSE-LABEL: load_fmul_op1_constant_v4f32:92; SSE: # %bb.0:93; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero94; SSE-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm095; SSE-NEXT: retq96;97; AVX-LABEL: load_fmul_op1_constant_v4f32:98; AVX: # %bb.0:99; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero100; AVX-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0101; AVX-NEXT: retq102 %x = load float, ptr %p103 %v = insertelement <4 x float> undef, float %x, i32 0104 %b = fmul <4 x float> %v, <float 42.0, float undef, float undef, float undef>105 ret <4 x float> %b106}107 108define <4 x float> @fdiv_op1_constant_v4f32(float %x) nounwind {109; SSE-LABEL: fdiv_op1_constant_v4f32:110; SSE: # %bb.0:111; SSE-NEXT: divss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0112; SSE-NEXT: retq113;114; AVX-LABEL: fdiv_op1_constant_v4f32:115; AVX: # %bb.0:116; AVX-NEXT: vdivss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0117; AVX-NEXT: retq118 %v = insertelement <4 x float> undef, float %x, i32 0119 %b = fdiv <4 x float> %v, <float 42.0, float undef, float undef, float undef>120 ret <4 x float> %b121}122 123define <4 x float> @load_fdiv_op1_constant_v4f32(ptr %p) nounwind {124; SSE-LABEL: load_fdiv_op1_constant_v4f32:125; SSE: # %bb.0:126; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero127; SSE-NEXT: divss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0128; SSE-NEXT: retq129;130; AVX-LABEL: load_fdiv_op1_constant_v4f32:131; AVX: # %bb.0:132; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero133; AVX-NEXT: vdivss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0134; AVX-NEXT: retq135 %x = load float, ptr %p136 %v = insertelement <4 x float> undef, float %x, i32 0137 %b = fdiv <4 x float> %v, <float 42.0, float undef, float undef, float undef>138 ret <4 x float> %b139}140 141define <4 x float> @fdiv_op0_constant_v4f32(float %x) nounwind {142; SSE-LABEL: fdiv_op0_constant_v4f32:143; SSE: # %bb.0:144; SSE-NEXT: movss {{.*#+}} xmm1 = [4.2E+1,0.0E+0,0.0E+0,0.0E+0]145; SSE-NEXT: divss %xmm0, %xmm1146; SSE-NEXT: movaps %xmm1, %xmm0147; SSE-NEXT: retq148;149; AVX-LABEL: fdiv_op0_constant_v4f32:150; AVX: # %bb.0:151; AVX-NEXT: vmovss {{.*#+}} xmm1 = [4.2E+1,0.0E+0,0.0E+0,0.0E+0]152; AVX-NEXT: vdivss %xmm0, %xmm1, %xmm0153; AVX-NEXT: retq154 %v = insertelement <4 x float> undef, float %x, i32 0155 %b = fdiv <4 x float> <float 42.0, float undef, float undef, float undef>, %v156 ret <4 x float> %b157}158 159define <4 x float> @load_fdiv_op0_constant_v4f32(ptr %p) nounwind {160; SSE-LABEL: load_fdiv_op0_constant_v4f32:161; SSE: # %bb.0:162; SSE-NEXT: movss {{.*#+}} xmm0 = [4.2E+1,0.0E+0,0.0E+0,0.0E+0]163; SSE-NEXT: divss (%rdi), %xmm0164; SSE-NEXT: retq165;166; AVX-LABEL: load_fdiv_op0_constant_v4f32:167; AVX: # %bb.0:168; AVX-NEXT: vmovss {{.*#+}} xmm0 = [4.2E+1,0.0E+0,0.0E+0,0.0E+0]169; AVX-NEXT: vdivss (%rdi), %xmm0, %xmm0170; AVX-NEXT: retq171 %x = load float, ptr %p172 %v = insertelement <4 x float> undef, float %x, i32 0173 %b = fdiv <4 x float> <float 42.0, float undef, float undef, float undef>, %v174 ret <4 x float> %b175}176 177define <4 x double> @fadd_op1_constant_v4f64(double %x) nounwind {178; SSE-LABEL: fadd_op1_constant_v4f64:179; SSE: # %bb.0:180; SSE-NEXT: addsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0181; SSE-NEXT: retq182;183; AVX-LABEL: fadd_op1_constant_v4f64:184; AVX: # %bb.0:185; AVX-NEXT: vaddsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0186; AVX-NEXT: retq187 %v = insertelement <4 x double> undef, double %x, i32 0188 %b = fadd <4 x double> %v, <double 42.0, double undef, double undef, double undef>189 ret <4 x double> %b190}191 192define <4 x double> @load_fadd_op1_constant_v4f64(ptr %p) nounwind {193; SSE-LABEL: load_fadd_op1_constant_v4f64:194; SSE: # %bb.0:195; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero196; SSE-NEXT: addsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0197; SSE-NEXT: retq198;199; AVX-LABEL: load_fadd_op1_constant_v4f64:200; AVX: # %bb.0:201; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero202; AVX-NEXT: vaddsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0203; AVX-NEXT: retq204 %x = load double, ptr %p205 %v = insertelement <4 x double> undef, double %x, i32 0206 %b = fadd <4 x double> %v, <double 42.0, double undef, double undef, double undef>207 ret <4 x double> %b208}209 210define <4 x double> @fsub_op0_constant_v4f64(double %x) nounwind {211; SSE-LABEL: fsub_op0_constant_v4f64:212; SSE: # %bb.0:213; SSE-NEXT: movsd {{.*#+}} xmm1 = [4.2E+1,0.0E+0]214; SSE-NEXT: subsd %xmm0, %xmm1215; SSE-NEXT: movapd %xmm1, %xmm0216; SSE-NEXT: retq217;218; AVX-LABEL: fsub_op0_constant_v4f64:219; AVX: # %bb.0:220; AVX-NEXT: vmovsd {{.*#+}} xmm1 = [4.2E+1,0.0E+0]221; AVX-NEXT: vsubsd %xmm0, %xmm1, %xmm0222; AVX-NEXT: retq223 %v = insertelement <4 x double> undef, double %x, i32 0224 %b = fsub <4 x double> <double 42.0, double undef, double undef, double undef>, %v225 ret <4 x double> %b226}227 228define <4 x double> @load_fsub_op0_constant_v4f64(ptr %p) nounwind {229; SSE-LABEL: load_fsub_op0_constant_v4f64:230; SSE: # %bb.0:231; SSE-NEXT: movsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]232; SSE-NEXT: subsd (%rdi), %xmm0233; SSE-NEXT: retq234;235; AVX-LABEL: load_fsub_op0_constant_v4f64:236; AVX: # %bb.0:237; AVX-NEXT: vmovsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]238; AVX-NEXT: vsubsd (%rdi), %xmm0, %xmm0239; AVX-NEXT: retq240 %x = load double, ptr %p241 %v = insertelement <4 x double> undef, double %x, i32 0242 %b = fsub <4 x double> <double 42.0, double undef, double undef, double undef>, %v243 ret <4 x double> %b244}245 246define <4 x double> @fmul_op1_constant_v4f64(double %x) nounwind {247; SSE-LABEL: fmul_op1_constant_v4f64:248; SSE: # %bb.0:249; SSE-NEXT: mulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0250; SSE-NEXT: retq251;252; AVX-LABEL: fmul_op1_constant_v4f64:253; AVX: # %bb.0:254; AVX-NEXT: vmulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0255; AVX-NEXT: retq256 %v = insertelement <4 x double> undef, double %x, i32 0257 %b = fmul <4 x double> %v, <double 42.0, double undef, double undef, double undef>258 ret <4 x double> %b259}260 261define <4 x double> @load_fmul_op1_constant_v4f64(ptr %p) nounwind {262; SSE-LABEL: load_fmul_op1_constant_v4f64:263; SSE: # %bb.0:264; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero265; SSE-NEXT: mulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0266; SSE-NEXT: retq267;268; AVX-LABEL: load_fmul_op1_constant_v4f64:269; AVX: # %bb.0:270; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero271; AVX-NEXT: vmulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0272; AVX-NEXT: retq273 %x = load double, ptr %p274 %v = insertelement <4 x double> undef, double %x, i32 0275 %b = fmul <4 x double> %v, <double 42.0, double undef, double undef, double undef>276 ret <4 x double> %b277}278 279define <4 x double> @fdiv_op1_constant_v4f64(double %x) nounwind {280; SSE-LABEL: fdiv_op1_constant_v4f64:281; SSE: # %bb.0:282; SSE-NEXT: divsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0283; SSE-NEXT: retq284;285; AVX-LABEL: fdiv_op1_constant_v4f64:286; AVX: # %bb.0:287; AVX-NEXT: vdivsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0288; AVX-NEXT: retq289 %v = insertelement <4 x double> undef, double %x, i32 0290 %b = fdiv <4 x double> %v, <double 42.0, double undef, double undef, double undef>291 ret <4 x double> %b292}293 294define <4 x double> @load_fdiv_op1_constant_v4f64(ptr %p) nounwind {295; SSE-LABEL: load_fdiv_op1_constant_v4f64:296; SSE: # %bb.0:297; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero298; SSE-NEXT: divsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0299; SSE-NEXT: retq300;301; AVX-LABEL: load_fdiv_op1_constant_v4f64:302; AVX: # %bb.0:303; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero304; AVX-NEXT: vdivsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0305; AVX-NEXT: retq306 %x = load double, ptr %p307 %v = insertelement <4 x double> undef, double %x, i32 0308 %b = fdiv <4 x double> %v, <double 42.0, double undef, double undef, double undef>309 ret <4 x double> %b310}311 312define <4 x double> @fdiv_op0_constant_v4f64(double %x) nounwind {313; SSE-LABEL: fdiv_op0_constant_v4f64:314; SSE: # %bb.0:315; SSE-NEXT: movsd {{.*#+}} xmm1 = [4.2E+1,0.0E+0]316; SSE-NEXT: divsd %xmm0, %xmm1317; SSE-NEXT: movapd %xmm1, %xmm0318; SSE-NEXT: retq319;320; AVX-LABEL: fdiv_op0_constant_v4f64:321; AVX: # %bb.0:322; AVX-NEXT: vmovsd {{.*#+}} xmm1 = [4.2E+1,0.0E+0]323; AVX-NEXT: vdivsd %xmm0, %xmm1, %xmm0324; AVX-NEXT: retq325 %v = insertelement <4 x double> undef, double %x, i32 0326 %b = fdiv <4 x double> <double 42.0, double undef, double undef, double undef>, %v327 ret <4 x double> %b328}329 330define <4 x double> @load_fdiv_op0_constant_v4f64(ptr %p) nounwind {331; SSE-LABEL: load_fdiv_op0_constant_v4f64:332; SSE: # %bb.0:333; SSE-NEXT: movsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]334; SSE-NEXT: divsd (%rdi), %xmm0335; SSE-NEXT: retq336;337; AVX-LABEL: load_fdiv_op0_constant_v4f64:338; AVX: # %bb.0:339; AVX-NEXT: vmovsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]340; AVX-NEXT: vdivsd (%rdi), %xmm0, %xmm0341; AVX-NEXT: retq342 %x = load double, ptr %p343 %v = insertelement <4 x double> undef, double %x, i32 0344 %b = fdiv <4 x double> <double 42.0, double undef, double undef, double undef>, %v345 ret <4 x double> %b346}347 348define <2 x double> @fadd_splat_splat_v2f64(<2 x double> %vx, <2 x double> %vy) {349; SSE-LABEL: fadd_splat_splat_v2f64:350; SSE: # %bb.0:351; SSE-NEXT: addsd %xmm1, %xmm0352; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]353; SSE-NEXT: retq354;355; AVX-LABEL: fadd_splat_splat_v2f64:356; AVX: # %bb.0:357; AVX-NEXT: vaddsd %xmm1, %xmm0, %xmm0358; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]359; AVX-NEXT: retq360 %splatx = shufflevector <2 x double> %vx, <2 x double> undef, <2 x i32> zeroinitializer361 %splaty = shufflevector <2 x double> %vy, <2 x double> undef, <2 x i32> zeroinitializer362 %r = fadd <2 x double> %splatx, %splaty363 ret <2 x double> %r364}365 366define <4 x double> @fsub_splat_splat_v4f64(double %x, double %y) {367; SSE-LABEL: fsub_splat_splat_v4f64:368; SSE: # %bb.0:369; SSE-NEXT: subsd %xmm1, %xmm0370; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]371; SSE-NEXT: movapd %xmm0, %xmm1372; SSE-NEXT: retq373;374; AVX1-LABEL: fsub_splat_splat_v4f64:375; AVX1: # %bb.0:376; AVX1-NEXT: vsubsd %xmm1, %xmm0, %xmm0377; AVX1-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]378; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0379; AVX1-NEXT: retq380;381; AVX512-LABEL: fsub_splat_splat_v4f64:382; AVX512: # %bb.0:383; AVX512-NEXT: vsubsd %xmm1, %xmm0, %xmm0384; AVX512-NEXT: vbroadcastsd %xmm0, %ymm0385; AVX512-NEXT: retq386 %vx = insertelement <4 x double> undef, double %x, i32 0387 %vy = insertelement <4 x double> undef, double %y, i32 0388 %splatx = shufflevector <4 x double> %vx, <4 x double> undef, <4 x i32> zeroinitializer389 %splaty = shufflevector <4 x double> %vy, <4 x double> undef, <4 x i32> zeroinitializer390 %r = fsub <4 x double> %splatx, %splaty391 ret <4 x double> %r392}393 394define <4 x float> @fmul_splat_splat_v4f32(<4 x float> %vx, <4 x float> %vy) {395; SSE-LABEL: fmul_splat_splat_v4f32:396; SSE: # %bb.0:397; SSE-NEXT: mulss %xmm1, %xmm0398; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,0,0]399; SSE-NEXT: retq400;401; AVX1-LABEL: fmul_splat_splat_v4f32:402; AVX1: # %bb.0:403; AVX1-NEXT: vmulss %xmm1, %xmm0, %xmm0404; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0,0,0]405; AVX1-NEXT: retq406;407; AVX512-LABEL: fmul_splat_splat_v4f32:408; AVX512: # %bb.0:409; AVX512-NEXT: vmulss %xmm1, %xmm0, %xmm0410; AVX512-NEXT: vbroadcastss %xmm0, %xmm0411; AVX512-NEXT: retq412 %splatx = shufflevector <4 x float> %vx, <4 x float> undef, <4 x i32> zeroinitializer413 %splaty = shufflevector <4 x float> %vy, <4 x float> undef, <4 x i32> zeroinitializer414 %r = fmul fast <4 x float> %splatx, %splaty415 ret <4 x float> %r416}417 418define <8 x float> @fdiv_splat_splat_v8f32(<8 x float> %vx, <8 x float> %vy) {419; SSE-LABEL: fdiv_splat_splat_v8f32:420; SSE: # %bb.0:421; SSE-NEXT: divss %xmm2, %xmm0422; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,0,0]423; SSE-NEXT: movaps %xmm0, %xmm1424; SSE-NEXT: retq425;426; AVX1-LABEL: fdiv_splat_splat_v8f32:427; AVX1: # %bb.0:428; AVX1-NEXT: vdivss %xmm1, %xmm0, %xmm0429; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0,0,0]430; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0431; AVX1-NEXT: retq432;433; AVX512-LABEL: fdiv_splat_splat_v8f32:434; AVX512: # %bb.0:435; AVX512-NEXT: vdivss %xmm1, %xmm0, %xmm0436; AVX512-NEXT: vbroadcastss %xmm0, %ymm0437; AVX512-NEXT: retq438 %splatx = shufflevector <8 x float> %vx, <8 x float> undef, <8 x i32> zeroinitializer439 %splaty = shufflevector <8 x float> %vy, <8 x float> undef, <8 x i32> zeroinitializer440 %r = fdiv fast <8 x float> %splatx, %splaty441 ret <8 x float> %r442}443 444; Negative test - splat of non-zero indexes (still sink the splat).445 446define <2 x double> @fadd_splat_splat_nonzero_v2f64(<2 x double> %vx, <2 x double> %vy) {447; SSE-LABEL: fadd_splat_splat_nonzero_v2f64:448; SSE: # %bb.0:449; SSE-NEXT: addpd %xmm1, %xmm0450; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]451; SSE-NEXT: retq452;453; AVX-LABEL: fadd_splat_splat_nonzero_v2f64:454; AVX: # %bb.0:455; AVX-NEXT: vaddpd %xmm1, %xmm0, %xmm0456; AVX-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,1]457; AVX-NEXT: retq458 %splatx = shufflevector <2 x double> %vx, <2 x double> undef, <2 x i32> <i32 1, i32 1>459 %splaty = shufflevector <2 x double> %vy, <2 x double> undef, <2 x i32> <i32 1, i32 1>460 %r = fadd <2 x double> %splatx, %splaty461 ret <2 x double> %r462}463 464; Negative test - splat of non-zero index and mismatched indexes.465 466define <2 x double> @fadd_splat_splat_mismatch_v2f64(<2 x double> %vx, <2 x double> %vy) {467; SSE-LABEL: fadd_splat_splat_mismatch_v2f64:468; SSE: # %bb.0:469; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]470; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1]471; SSE-NEXT: addpd %xmm1, %xmm0472; SSE-NEXT: retq473;474; AVX-LABEL: fadd_splat_splat_mismatch_v2f64:475; AVX: # %bb.0:476; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]477; AVX-NEXT: vshufpd {{.*#+}} xmm1 = xmm1[1,1]478; AVX-NEXT: vaddpd %xmm1, %xmm0, %xmm0479; AVX-NEXT: retq480 %splatx = shufflevector <2 x double> %vx, <2 x double> undef, <2 x i32> <i32 0, i32 0>481 %splaty = shufflevector <2 x double> %vy, <2 x double> undef, <2 x i32> <i32 1, i32 1>482 %r = fadd <2 x double> %splatx, %splaty483 ret <2 x double> %r484}485 486; Negative test - non-splat.487 488define <2 x double> @fadd_splat_nonsplat_v2f64(<2 x double> %vx, <2 x double> %vy) {489; SSE-LABEL: fadd_splat_nonsplat_v2f64:490; SSE: # %bb.0:491; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]492; SSE-NEXT: addpd %xmm1, %xmm0493; SSE-NEXT: retq494;495; AVX-LABEL: fadd_splat_nonsplat_v2f64:496; AVX: # %bb.0:497; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]498; AVX-NEXT: vaddpd %xmm1, %xmm0, %xmm0499; AVX-NEXT: retq500 %splatx = shufflevector <2 x double> %vx, <2 x double> undef, <2 x i32> <i32 0, i32 0>501 %splaty = shufflevector <2 x double> %vy, <2 x double> undef, <2 x i32> <i32 0, i32 1>502 %r = fadd <2 x double> %splatx, %splaty503 ret <2 x double> %r504}505 506; Negative test - non-FP.507 508define <2 x i64> @add_splat_splat_v2i64(<2 x i64> %vx, <2 x i64> %vy) {509; SSE-LABEL: add_splat_splat_v2i64:510; SSE: # %bb.0:511; SSE-NEXT: paddq %xmm1, %xmm0512; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]513; SSE-NEXT: retq514;515; AVX1-LABEL: add_splat_splat_v2i64:516; AVX1: # %bb.0:517; AVX1-NEXT: vpaddq %xmm1, %xmm0, %xmm0518; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]519; AVX1-NEXT: retq520;521; AVX512-LABEL: add_splat_splat_v2i64:522; AVX512: # %bb.0:523; AVX512-NEXT: vpaddq %xmm1, %xmm0, %xmm0524; AVX512-NEXT: vpbroadcastq %xmm0, %xmm0525; AVX512-NEXT: retq526 %splatx = shufflevector <2 x i64> %vx, <2 x i64> undef, <2 x i32> <i32 0, i32 0>527 %splaty = shufflevector <2 x i64> %vy, <2 x i64> undef, <2 x i32> <i32 0, i32 0>528 %r = add <2 x i64> %splatx, %splaty529 ret <2 x i64> %r530}531 532define <2 x double> @fadd_splat_const_op1_v2f64(<2 x double> %vx) {533; SSE-LABEL: fadd_splat_const_op1_v2f64:534; SSE: # %bb.0:535; SSE-NEXT: addsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0536; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]537; SSE-NEXT: retq538;539; AVX-LABEL: fadd_splat_const_op1_v2f64:540; AVX: # %bb.0:541; AVX-NEXT: vaddsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0542; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]543; AVX-NEXT: retq544 %splatx = shufflevector <2 x double> %vx, <2 x double> undef, <2 x i32> zeroinitializer545 %r = fadd <2 x double> %splatx, <double 42.0, double 42.0>546 ret <2 x double> %r547}548 549define <4 x double> @fsub_const_op0_splat_v4f64(double %x) {550; SSE-LABEL: fsub_const_op0_splat_v4f64:551; SSE: # %bb.0:552; SSE-NEXT: movsd {{.*#+}} xmm1 = [8.0E+0,0.0E+0]553; SSE-NEXT: subsd %xmm0, %xmm1554; SSE-NEXT: unpcklpd {{.*#+}} xmm1 = xmm1[0,0]555; SSE-NEXT: movapd %xmm1, %xmm0556; SSE-NEXT: retq557;558; AVX1-LABEL: fsub_const_op0_splat_v4f64:559; AVX1: # %bb.0:560; AVX1-NEXT: vmovsd {{.*#+}} xmm1 = [8.0E+0,0.0E+0]561; AVX1-NEXT: vsubsd %xmm0, %xmm1, %xmm0562; AVX1-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]563; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0564; AVX1-NEXT: retq565;566; AVX512-LABEL: fsub_const_op0_splat_v4f64:567; AVX512: # %bb.0:568; AVX512-NEXT: vmovsd {{.*#+}} xmm1 = [8.0E+0,0.0E+0]569; AVX512-NEXT: vsubsd %xmm0, %xmm1, %xmm0570; AVX512-NEXT: vbroadcastsd %xmm0, %ymm0571; AVX512-NEXT: retq572 %vx = insertelement <4 x double> undef, double 8.0, i32 0573 %vy = insertelement <4 x double> undef, double %x, i32 0574 %splatx = shufflevector <4 x double> %vx, <4 x double> undef, <4 x i32> zeroinitializer575 %splaty = shufflevector <4 x double> %vy, <4 x double> undef, <4 x i32> zeroinitializer576 %r = fsub <4 x double> %splatx, %splaty577 ret <4 x double> %r578}579 580define <4 x float> @fmul_splat_const_op1_v4f32(<4 x float> %vx, <4 x float> %vy) {581; SSE-LABEL: fmul_splat_const_op1_v4f32:582; SSE: # %bb.0:583; SSE-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0584; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,0,0]585; SSE-NEXT: retq586;587; AVX1-LABEL: fmul_splat_const_op1_v4f32:588; AVX1: # %bb.0:589; AVX1-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0590; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0,0,0]591; AVX1-NEXT: retq592;593; AVX512-LABEL: fmul_splat_const_op1_v4f32:594; AVX512: # %bb.0:595; AVX512-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0596; AVX512-NEXT: vbroadcastss %xmm0, %xmm0597; AVX512-NEXT: retq598 %splatx = shufflevector <4 x float> %vx, <4 x float> undef, <4 x i32> zeroinitializer599 %r = fmul fast <4 x float> %splatx, <float 17.0, float 17.0, float 17.0, float 17.0>600 ret <4 x float> %r601}602 603define <8 x float> @fdiv_splat_const_op0_v8f32(<8 x float> %vy) {604; SSE-LABEL: fdiv_splat_const_op0_v8f32:605; SSE: # %bb.0:606; SSE-NEXT: movss {{.*#+}} xmm1 = [4.5E+0,0.0E+0,0.0E+0,0.0E+0]607; SSE-NEXT: divss %xmm0, %xmm1608; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0,0,0]609; SSE-NEXT: movaps %xmm1, %xmm0610; SSE-NEXT: retq611;612; AVX1-LABEL: fdiv_splat_const_op0_v8f32:613; AVX1: # %bb.0:614; AVX1-NEXT: vmovss {{.*#+}} xmm1 = [4.5E+0,0.0E+0,0.0E+0,0.0E+0]615; AVX1-NEXT: vdivss %xmm0, %xmm1, %xmm0616; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0,0,0]617; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0618; AVX1-NEXT: retq619;620; AVX512-LABEL: fdiv_splat_const_op0_v8f32:621; AVX512: # %bb.0:622; AVX512-NEXT: vmovss {{.*#+}} xmm1 = [4.5E+0,0.0E+0,0.0E+0,0.0E+0]623; AVX512-NEXT: vdivss %xmm0, %xmm1, %xmm0624; AVX512-NEXT: vbroadcastss %xmm0, %ymm0625; AVX512-NEXT: retq626 %splatx = shufflevector <8 x float> <float 4.5, float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0>, <8 x float> undef, <8 x i32> zeroinitializer627 %splaty = shufflevector <8 x float> %vy, <8 x float> undef, <8 x i32> zeroinitializer628 %r = fdiv fast <8 x float> %splatx, %splaty629 ret <8 x float> %r630}631 632define <8 x float> @fdiv_const_op1_splat_v8f32(<8 x float> %vx) {633; SSE-LABEL: fdiv_const_op1_splat_v8f32:634; SSE: # %bb.0:635; SSE-NEXT: xorps %xmm1, %xmm1636; SSE-NEXT: divss %xmm1, %xmm0637; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,0,0]638; SSE-NEXT: movaps %xmm0, %xmm1639; SSE-NEXT: retq640;641; AVX1-LABEL: fdiv_const_op1_splat_v8f32:642; AVX1: # %bb.0:643; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1644; AVX1-NEXT: vdivss %xmm1, %xmm0, %xmm0645; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0,0,0]646; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0647; AVX1-NEXT: retq648;649; AVX512-LABEL: fdiv_const_op1_splat_v8f32:650; AVX512: # %bb.0:651; AVX512-NEXT: vxorps %xmm1, %xmm1, %xmm1652; AVX512-NEXT: vdivss %xmm1, %xmm0, %xmm0653; AVX512-NEXT: vbroadcastss %xmm0, %ymm0654; AVX512-NEXT: retq655 %splatx = shufflevector <8 x float> %vx, <8 x float> undef, <8 x i32> zeroinitializer656 %splaty = shufflevector <8 x float> <float 0.0, float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0>, <8 x float> undef, <8 x i32> zeroinitializer657 %r = fdiv fast <8 x float> %splatx, %splaty658 ret <8 x float> %r659}660 661define <2 x double> @splat0_fadd_v2f64(<2 x double> %vx, <2 x double> %vy) {662; SSE-LABEL: splat0_fadd_v2f64:663; SSE: # %bb.0:664; SSE-NEXT: addsd %xmm1, %xmm0665; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]666; SSE-NEXT: retq667;668; AVX-LABEL: splat0_fadd_v2f64:669; AVX: # %bb.0:670; AVX-NEXT: vaddsd %xmm1, %xmm0, %xmm0671; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]672; AVX-NEXT: retq673 %b = fadd <2 x double> %vx, %vy674 %r = shufflevector <2 x double> %b, <2 x double> undef, <2 x i32> zeroinitializer675 ret <2 x double> %r676}677 678define <4 x double> @splat0_fsub_v4f64(double %x, double %y) {679; SSE-LABEL: splat0_fsub_v4f64:680; SSE: # %bb.0:681; SSE-NEXT: subsd %xmm1, %xmm0682; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]683; SSE-NEXT: movapd %xmm0, %xmm1684; SSE-NEXT: retq685;686; AVX1-LABEL: splat0_fsub_v4f64:687; AVX1: # %bb.0:688; AVX1-NEXT: vsubsd %xmm1, %xmm0, %xmm0689; AVX1-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]690; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0691; AVX1-NEXT: retq692;693; AVX512-LABEL: splat0_fsub_v4f64:694; AVX512: # %bb.0:695; AVX512-NEXT: vsubsd %xmm1, %xmm0, %xmm0696; AVX512-NEXT: vbroadcastsd %xmm0, %ymm0697; AVX512-NEXT: retq698 %vx = insertelement <4 x double> undef, double %x, i32 0699 %vy = insertelement <4 x double> undef, double %y, i32 0700 %b = fsub <4 x double> %vx, %vy701 %r = shufflevector <4 x double> %b, <4 x double> undef, <4 x i32> zeroinitializer702 ret <4 x double> %r703}704 705define <4 x float> @splat0_fmul_v4f32(<4 x float> %vx, <4 x float> %vy) {706; SSE-LABEL: splat0_fmul_v4f32:707; SSE: # %bb.0:708; SSE-NEXT: mulss %xmm1, %xmm0709; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,0,0]710; SSE-NEXT: retq711;712; AVX1-LABEL: splat0_fmul_v4f32:713; AVX1: # %bb.0:714; AVX1-NEXT: vmulss %xmm1, %xmm0, %xmm0715; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0,0,0]716; AVX1-NEXT: retq717;718; AVX512-LABEL: splat0_fmul_v4f32:719; AVX512: # %bb.0:720; AVX512-NEXT: vmulss %xmm1, %xmm0, %xmm0721; AVX512-NEXT: vbroadcastss %xmm0, %xmm0722; AVX512-NEXT: retq723 %b = fmul fast <4 x float> %vx, %vy724 %r = shufflevector <4 x float> %b, <4 x float> undef, <4 x i32> zeroinitializer725 ret <4 x float> %r726}727 728define <8 x float> @splat0_fdiv_v8f32(<8 x float> %vx, <8 x float> %vy) {729; SSE-LABEL: splat0_fdiv_v8f32:730; SSE: # %bb.0:731; SSE-NEXT: divss %xmm2, %xmm0732; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,0,0]733; SSE-NEXT: movaps %xmm0, %xmm1734; SSE-NEXT: retq735;736; AVX1-LABEL: splat0_fdiv_v8f32:737; AVX1: # %bb.0:738; AVX1-NEXT: vdivss %xmm1, %xmm0, %xmm0739; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0,0,0]740; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0741; AVX1-NEXT: retq742;743; AVX512-LABEL: splat0_fdiv_v8f32:744; AVX512: # %bb.0:745; AVX512-NEXT: vdivss %xmm1, %xmm0, %xmm0746; AVX512-NEXT: vbroadcastss %xmm0, %ymm0747; AVX512-NEXT: retq748 %b = fdiv fast <8 x float> %vx, %vy749 %r = shufflevector <8 x float> %b, <8 x float> undef, <8 x i32> zeroinitializer750 ret <8 x float> %r751}752 753define <2 x double> @splat0_fadd_const_op1_v2f64(<2 x double> %vx) {754; SSE-LABEL: splat0_fadd_const_op1_v2f64:755; SSE: # %bb.0:756; SSE-NEXT: addsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0757; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]758; SSE-NEXT: retq759;760; AVX-LABEL: splat0_fadd_const_op1_v2f64:761; AVX: # %bb.0:762; AVX-NEXT: vaddsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0763; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]764; AVX-NEXT: retq765 %b = fadd <2 x double> %vx, <double 42.0, double 12.0>766 %r = shufflevector <2 x double> %b, <2 x double> undef, <2 x i32> zeroinitializer767 ret <2 x double> %r768}769 770define <4 x double> @splat0_fsub_const_op0_v4f64(double %x) {771; SSE-LABEL: splat0_fsub_const_op0_v4f64:772; SSE: # %bb.0:773; SSE-NEXT: movsd {{.*#+}} xmm1 = [-4.2E+1,0.0E+0]774; SSE-NEXT: subsd %xmm0, %xmm1775; SSE-NEXT: unpcklpd {{.*#+}} xmm1 = xmm1[0,0]776; SSE-NEXT: movapd %xmm1, %xmm0777; SSE-NEXT: retq778;779; AVX1-LABEL: splat0_fsub_const_op0_v4f64:780; AVX1: # %bb.0:781; AVX1-NEXT: vmovsd {{.*#+}} xmm1 = [-4.2E+1,0.0E+0]782; AVX1-NEXT: vsubsd %xmm0, %xmm1, %xmm0783; AVX1-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]784; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0785; AVX1-NEXT: retq786;787; AVX512-LABEL: splat0_fsub_const_op0_v4f64:788; AVX512: # %bb.0:789; AVX512-NEXT: vmovsd {{.*#+}} xmm1 = [-4.2E+1,0.0E+0]790; AVX512-NEXT: vsubsd %xmm0, %xmm1, %xmm0791; AVX512-NEXT: vbroadcastsd %xmm0, %ymm0792; AVX512-NEXT: retq793 %vx = insertelement <4 x double> undef, double %x, i32 0794 %b = fsub <4 x double> <double -42.0, double 42.0, double 0.0, double 1.0>, %vx795 %r = shufflevector <4 x double> %b, <4 x double> undef, <4 x i32> zeroinitializer796 ret <4 x double> %r797}798 799define <4 x float> @splat0_fmul_const_op1_v4f32(<4 x float> %vx) {800; SSE-LABEL: splat0_fmul_const_op1_v4f32:801; SSE: # %bb.0:802; SSE-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0803; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,0,0]804; SSE-NEXT: retq805;806; AVX1-LABEL: splat0_fmul_const_op1_v4f32:807; AVX1: # %bb.0:808; AVX1-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0809; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0,0,0]810; AVX1-NEXT: retq811;812; AVX512-LABEL: splat0_fmul_const_op1_v4f32:813; AVX512: # %bb.0:814; AVX512-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0815; AVX512-NEXT: vbroadcastss %xmm0, %xmm0816; AVX512-NEXT: retq817 %b = fmul fast <4 x float> %vx, <float 6.0, float -1.0, float 1.0, float 7.0>818 %r = shufflevector <4 x float> %b, <4 x float> undef, <4 x i32> zeroinitializer819 ret <4 x float> %r820}821 822define <8 x float> @splat0_fdiv_const_op1_v8f32(<8 x float> %vx) {823; SSE-LABEL: splat0_fdiv_const_op1_v8f32:824; SSE: # %bb.0:825; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,0,0]826; SSE-NEXT: movaps %xmm0, %xmm1827; SSE-NEXT: retq828;829; AVX1-LABEL: splat0_fdiv_const_op1_v8f32:830; AVX1: # %bb.0:831; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0,0,0]832; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0833; AVX1-NEXT: retq834;835; AVX512-LABEL: splat0_fdiv_const_op1_v8f32:836; AVX512: # %bb.0:837; AVX512-NEXT: vbroadcastss %xmm0, %ymm0838; AVX512-NEXT: retq839 %b = fdiv fast <8 x float> %vx, <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0>840 %r = shufflevector <8 x float> %b, <8 x float> undef, <8 x i32> zeroinitializer841 ret <8 x float> %r842}843 844define <8 x float> @splat0_fdiv_const_op0_v8f32(<8 x float> %vx) {845; SSE-LABEL: splat0_fdiv_const_op0_v8f32:846; SSE: # %bb.0:847; SSE-NEXT: movss {{.*#+}} xmm1 = [1.0E+0,0.0E+0,0.0E+0,0.0E+0]848; SSE-NEXT: divss %xmm0, %xmm1849; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0,0,0]850; SSE-NEXT: movaps %xmm1, %xmm0851; SSE-NEXT: retq852;853; AVX1-LABEL: splat0_fdiv_const_op0_v8f32:854; AVX1: # %bb.0:855; AVX1-NEXT: vmovss {{.*#+}} xmm1 = [1.0E+0,0.0E+0,0.0E+0,0.0E+0]856; AVX1-NEXT: vdivss %xmm0, %xmm1, %xmm0857; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0,0,0]858; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0859; AVX1-NEXT: retq860;861; AVX512-LABEL: splat0_fdiv_const_op0_v8f32:862; AVX512: # %bb.0:863; AVX512-NEXT: vmovss {{.*#+}} xmm1 = [1.0E+0,0.0E+0,0.0E+0,0.0E+0]864; AVX512-NEXT: vdivss %xmm0, %xmm1, %xmm0865; AVX512-NEXT: vbroadcastss %xmm0, %ymm0866; AVX512-NEXT: retq867 %b = fdiv fast <8 x float> <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0>, %vx868 %r = shufflevector <8 x float> %b, <8 x float> undef, <8 x i32> zeroinitializer869 ret <8 x float> %r870}871 872define <4 x float> @multi_use_binop(<4 x float> %x, <4 x float> %y) {873; SSE-LABEL: multi_use_binop:874; SSE: # %bb.0:875; SSE-NEXT: mulps %xmm1, %xmm0876; SSE-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]877; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,0,0]878; SSE-NEXT: addps %xmm1, %xmm0879; SSE-NEXT: retq880;881; AVX1-LABEL: multi_use_binop:882; AVX1: # %bb.0:883; AVX1-NEXT: vmulps %xmm1, %xmm0, %xmm0884; AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm0[0,0,0,0]885; AVX1-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]886; AVX1-NEXT: vaddps %xmm0, %xmm1, %xmm0887; AVX1-NEXT: retq888;889; AVX512-LABEL: multi_use_binop:890; AVX512: # %bb.0:891; AVX512-NEXT: vmulps %xmm1, %xmm0, %xmm0892; AVX512-NEXT: vbroadcastss %xmm0, %xmm1893; AVX512-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]894; AVX512-NEXT: vaddps %xmm0, %xmm1, %xmm0895; AVX512-NEXT: retq896 %mul = fmul <4 x float> %x, %y897 %mul0 = shufflevector <4 x float> %mul, <4 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 undef, i32 0>898 %mul1 = shufflevector <4 x float> %mul, <4 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 undef, i32 1>899 %r = fadd <4 x float> %mul0, %mul1900 ret <4 x float> %r901}902 903; PR140693904define <4 x float> @merge_fcmp_cmpeqss_v4f32(<4 x float> %x, <4 x float> %y) {905; SSE-LABEL: merge_fcmp_cmpeqss_v4f32:906; SSE: # %bb.0:907; SSE-NEXT: cmpeqss %xmm0, %xmm1908; SSE-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]909; SSE-NEXT: retq910;911; AVX1-LABEL: merge_fcmp_cmpeqss_v4f32:912; AVX1: # %bb.0:913; AVX1-NEXT: vcmpeqss %xmm0, %xmm1, %xmm1914; AVX1-NEXT: vmovss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]915; AVX1-NEXT: retq916;917; AVX512-LABEL: merge_fcmp_cmpeqss_v4f32:918; AVX512: # %bb.0:919; AVX512-NEXT: vcmpeqss %xmm0, %xmm1, %k0920; AVX512-NEXT: kmovw %k0, %eax921; AVX512-NEXT: negl %eax922; AVX512-NEXT: vmovd %eax, %xmm1923; AVX512-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]924; AVX512-NEXT: retq925 %cmp = fcmp oeq <4 x float> %y, %x926 %ext = extractelement <4 x i1> %cmp, i64 0927 %neg = sext i1 %ext to i32928 %vec = insertelement <4 x i32> poison, i32 %neg, i64 0929 %vecinit.i = bitcast <4 x i32> %vec to <4 x float>930 %vecinit3.i = shufflevector <4 x float> %vecinit.i, <4 x float> %x, <4 x i32> <i32 0, i32 5, i32 6, i32 7>931 ret <4 x float> %vecinit3.i932}933