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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=BASE3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=slow-3ops-lea | FileCheck %s --check-prefix=SLOWLEA34 5; TODO: Should the 'cmpl' be 'dec' instead?6; TODO: What if 'cmov' is 1 uop and full throughput (Ryzen)?7 8define i32 @PR28968(i32 %x) {9; BASE-LABEL: PR28968:10; BASE: # %bb.0:11; BASE-NEXT: xorl %eax, %eax12; BASE-NEXT: cmpl $1, %edi13; BASE-NEXT: sete %al14; BASE-NEXT: leal -1(%rax,%rax), %eax15; BASE-NEXT: retq16;17; SLOWLEA3-LABEL: PR28968:18; SLOWLEA3: # %bb.0:19; SLOWLEA3-NEXT: xorl %eax, %eax20; SLOWLEA3-NEXT: cmpl $1, %edi21; SLOWLEA3-NEXT: sete %al22; SLOWLEA3-NEXT: leal -1(,%rax,2), %eax23; SLOWLEA3-NEXT: retq24 %cmp = icmp eq i32 %x, 125 %sel = select i1 %cmp, i32 1, i32 -126 ret i32 %sel27}28 29