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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s3 4; (zext(select c, load1, load2)) -> (select c, zextload1, zextload2)5define i64 @zext_scalar(ptr %p, i1 zeroext %c) {6; CHECK-LABEL: zext_scalar:7; CHECK: # %bb.0:8; CHECK-NEXT: movzbl (%rdi), %ecx9; CHECK-NEXT: movzbl 1(%rdi), %eax10; CHECK-NEXT: testl %esi, %esi11; CHECK-NEXT: cmoveq %rcx, %rax12; CHECK-NEXT: retq13 %ld1 = load volatile i8, ptr %p14 %arrayidx1 = getelementptr inbounds i8, ptr %p, i64 115 %ld2 = load volatile i8, ptr %arrayidx116 %cond.v = select i1 %c, i8 %ld2, i8 %ld117 %cond = zext i8 %cond.v to i6418 ret i64 %cond19}20 21define i64 @zext_scalar2(ptr %p, ptr %q, i1 zeroext %c) {22; CHECK-LABEL: zext_scalar2:23; CHECK: # %bb.0:24; CHECK-NEXT: movzbl (%rdi), %ecx25; CHECK-NEXT: movzwl (%rsi), %eax26; CHECK-NEXT: testl %edx, %edx27; CHECK-NEXT: cmoveq %rcx, %rax28; CHECK-NEXT: retq29 %ld1 = load volatile i8, ptr %p30 %ext_ld1 = zext i8 %ld1 to i1631 %ld2 = load volatile i16, ptr %q32 %cond.v = select i1 %c, i16 %ld2, i16 %ext_ld133 %cond = zext i16 %cond.v to i6434 ret i64 %cond35}36 37; Don't fold the ext if there is a load with conflicting ext type.38define i64 @zext_scalar_neg(ptr %p, ptr %q, i1 zeroext %c) {39; CHECK-LABEL: zext_scalar_neg:40; CHECK: # %bb.0:41; CHECK-NEXT: movsbl (%rdi), %eax42; CHECK-NEXT: testl %edx, %edx43; CHECK-NEXT: je .LBB2_244; CHECK-NEXT: # %bb.1:45; CHECK-NEXT: movzwl (%rsi), %eax46; CHECK-NEXT: .LBB2_2:47; CHECK-NEXT: movzwl %ax, %eax48; CHECK-NEXT: retq49 %ld1 = load volatile i8, ptr %p50 %ext_ld1 = sext i8 %ld1 to i1651 %ld2 = load volatile i16, ptr %q52 %cond.v = select i1 %c, i16 %ld2, i16 %ext_ld153 %cond = zext i16 %cond.v to i6454 ret i64 %cond55}56 57; (sext(select c, load1, load2)) -> (select c, sextload1, sextload2)58define i64 @sext_scalar(ptr %p, i1 zeroext %c) {59; CHECK-LABEL: sext_scalar:60; CHECK: # %bb.0:61; CHECK-NEXT: movsbq (%rdi), %rcx62; CHECK-NEXT: movsbq 1(%rdi), %rax63; CHECK-NEXT: testl %esi, %esi64; CHECK-NEXT: cmoveq %rcx, %rax65; CHECK-NEXT: retq66 %ld1 = load volatile i8, ptr %p67 %arrayidx1 = getelementptr inbounds i8, ptr %p, i64 168 %ld2 = load volatile i8, ptr %arrayidx169 %cond.v = select i1 %c, i8 %ld2, i8 %ld170 %cond = sext i8 %cond.v to i6471 ret i64 %cond72}73 74; Same as zext_scalar, but operate on vectors.75define <2 x i64> @zext_vector_i1(ptr %p, i1 zeroext %c) {76; CHECK-LABEL: zext_vector_i1:77; CHECK: # %bb.0:78; CHECK-NEXT: pmovzxdq {{.*#+}} xmm1 = mem[0],zero,mem[1],zero79; CHECK-NEXT: pmovzxdq {{.*#+}} xmm0 = mem[0],zero,mem[1],zero80; CHECK-NEXT: testl %esi, %esi81; CHECK-NEXT: jne .LBB4_282; CHECK-NEXT: # %bb.1:83; CHECK-NEXT: movdqa %xmm1, %xmm084; CHECK-NEXT: .LBB4_2:85; CHECK-NEXT: retq86 %ld1 = load volatile <2 x i32>, ptr %p87 %arrayidx1 = getelementptr inbounds <2 x i32>, ptr %p, i64 188 %ld2 = load volatile <2 x i32>, ptr %arrayidx189 %cond.v = select i1 %c, <2 x i32> %ld2, <2 x i32> %ld190 %cond = zext <2 x i32> %cond.v to <2 x i64>91 ret <2 x i64> %cond92}93 94define <2 x i64> @zext_vector_v2i1(ptr %p, <2 x i1> %c) {95; CHECK-LABEL: zext_vector_v2i1:96; CHECK: # %bb.0:97; CHECK-NEXT: psllq $63, %xmm098; CHECK-NEXT: pmovzxdq {{.*#+}} xmm1 = mem[0],zero,mem[1],zero99; CHECK-NEXT: pmovzxdq {{.*#+}} xmm2 = mem[0],zero,mem[1],zero100; CHECK-NEXT: blendvpd %xmm0, %xmm2, %xmm1101; CHECK-NEXT: movapd %xmm1, %xmm0102; CHECK-NEXT: retq103 %ld1 = load volatile <2 x i32>, ptr %p104 %arrayidx1 = getelementptr inbounds <2 x i32>, ptr %p, i64 1105 %ld2 = load volatile <2 x i32>, ptr %arrayidx1106 %cond.v = select <2 x i1> %c, <2 x i32> %ld2, <2 x i32> %ld1107 %cond = zext <2 x i32> %cond.v to <2 x i64>108 ret <2 x i64> %cond109}110 111; Same as sext_scalar, but operate on vectors.112define <2 x i64> @sext_vector_i1(ptr %p, i1 zeroext %c) {113; CHECK-LABEL: sext_vector_i1:114; CHECK: # %bb.0:115; CHECK-NEXT: pmovsxdq (%rdi), %xmm1116; CHECK-NEXT: pmovsxdq 8(%rdi), %xmm0117; CHECK-NEXT: testl %esi, %esi118; CHECK-NEXT: jne .LBB6_2119; CHECK-NEXT: # %bb.1:120; CHECK-NEXT: movdqa %xmm1, %xmm0121; CHECK-NEXT: .LBB6_2:122; CHECK-NEXT: retq123 %ld1 = load volatile <2 x i32>, ptr %p124 %arrayidx1 = getelementptr inbounds <2 x i32>, ptr %p, i64 1125 %ld2 = load volatile <2 x i32>, ptr %arrayidx1126 %cond.v = select i1 %c, <2 x i32> %ld2, <2 x i32> %ld1127 %cond = sext <2 x i32> %cond.v to <2 x i64>128 ret <2 x i64> %cond129}130 131define <2 x i64> @sext_vector_v2i1(ptr %p, <2 x i1> %c) {132; CHECK-LABEL: sext_vector_v2i1:133; CHECK: # %bb.0:134; CHECK-NEXT: psllq $63, %xmm0135; CHECK-NEXT: pmovsxdq (%rdi), %xmm1136; CHECK-NEXT: pmovsxdq 8(%rdi), %xmm2137; CHECK-NEXT: blendvpd %xmm0, %xmm2, %xmm1138; CHECK-NEXT: movapd %xmm1, %xmm0139; CHECK-NEXT: retq140 %ld1 = load volatile <2 x i32>, ptr %p141 %arrayidx1 = getelementptr inbounds <2 x i32>, ptr %p, i64 1142 %ld2 = load volatile <2 x i32>, ptr %arrayidx1143 %cond.v = select <2 x i1> %c, <2 x i32> %ld2, <2 x i32> %ld1144 %cond = sext <2 x i32> %cond.v to <2 x i64>145 ret <2 x i64> %cond146}147