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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s3 4define <4 x i32> @test1(<4 x float> %a, <4 x float> %b, <4 x i32> %c) {5; CHECK-LABEL: test1:6; CHECK: # %bb.0:7; CHECK-NEXT: vcmpnleps %xmm0, %xmm1, %xmm08; CHECK-NEXT: vandps %xmm2, %xmm0, %xmm09; CHECK-NEXT: retq10 %f = fcmp ult <4 x float> %a, %b11 %r = select <4 x i1> %f, <4 x i32> %c, <4 x i32> zeroinitializer12 ret <4 x i32> %r13}14 15define <4 x i32> @test2(<4 x float> %a, <4 x float> %b, <4 x i32> %c) {16; CHECK-LABEL: test2:17; CHECK: # %bb.0:18; CHECK-NEXT: vcmpnleps %xmm0, %xmm1, %xmm019; CHECK-NEXT: vorps %xmm2, %xmm0, %xmm020; CHECK-NEXT: retq21 %f = fcmp ult <4 x float> %a, %b22 %r = select <4 x i1> %f, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %c23 ret <4 x i32> %r24}25 26define <4 x i32> @test3(<4 x float> %a, <4 x float> %b, <4 x i32> %c) {27; CHECK-LABEL: test3:28; CHECK: # %bb.0:29; CHECK-NEXT: vcmpleps %xmm0, %xmm1, %xmm030; CHECK-NEXT: vandps %xmm2, %xmm0, %xmm031; CHECK-NEXT: retq32 %f = fcmp ult <4 x float> %a, %b33 %r = select <4 x i1> %f, <4 x i32> zeroinitializer, <4 x i32> %c34 ret <4 x i32> %r35}36 37define <4 x i32> @test4(<4 x float> %a, <4 x float> %b, <4 x i32> %c) {38; CHECK-LABEL: test4:39; CHECK: # %bb.0:40; CHECK-NEXT: vcmpleps %xmm0, %xmm1, %xmm041; CHECK-NEXT: vorps %xmm2, %xmm0, %xmm042; CHECK-NEXT: retq43 %f = fcmp ult <4 x float> %a, %b44 %r = select <4 x i1> %f, <4 x i32> %c, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>45 ret <4 x i32> %r46}47 48define <4 x i32> @test5(<4 x float> %a, <4 x float> %b, <4 x i32> %c) {49; CHECK-LABEL: test5:50; CHECK: # %bb.0:51; CHECK-NEXT: vcmpnleps %xmm0, %xmm1, %xmm052; CHECK-NEXT: retq53 %f = fcmp ult <4 x float> %a, %b54 %r = sext <4 x i1> %f to <4 x i32>55 ret <4 x i32> %r56}57 58define <4 x i32> @test6(<4 x float> %a, <4 x float> %b, <4 x i32> %c) {59; CHECK-LABEL: test6:60; CHECK: # %bb.0:61; CHECK-NEXT: vcmpleps %xmm0, %xmm1, %xmm062; CHECK-NEXT: retq63 %not.f = fcmp oge <4 x float> %a, %b64 %r = sext <4 x i1> %not.f to <4 x i32>65 ret <4 x i32> %r66}67 68define <4 x i32> @test7(<4 x float> %a, <4 x float> %b, ptr %p) {69; CHECK-LABEL: test7:70; CHECK: # %bb.0:71; CHECK-NEXT: vcmpnleps %xmm0, %xmm1, %xmm072; CHECK-NEXT: vandps (%rdi), %xmm0, %xmm073; CHECK-NEXT: retq74 %f = fcmp ult <4 x float> %a, %b75 %l = load <4 x i32>, ptr %p, align 1676 %r = select <4 x i1> %f, <4 x i32> %l, <4 x i32> zeroinitializer77 ret <4 x i32> %r78}79 80; Repeat all with FP types for the select operands. Also, use different comparison predicates for better test coverage.81 82define <2 x double> @test1f(<2 x double> %a, <2 x double> %b, <2 x double> %c) {83; CHECK-LABEL: test1f:84; CHECK: # %bb.0:85; CHECK-NEXT: vcmpltpd %xmm0, %xmm1, %xmm086; CHECK-NEXT: vandpd %xmm2, %xmm0, %xmm087; CHECK-NEXT: retq88 %f = fcmp ogt <2 x double> %a, %b89 %r = select <2 x i1> %f, <2 x double> %c, <2 x double> zeroinitializer90 ret <2 x double> %r91}92 93define <2 x double> @test2f(<2 x double> %a, <2 x double> %b, <2 x double> %c) {94; CHECK-LABEL: test2f:95; CHECK: # %bb.0:96; CHECK-NEXT: vcmplepd %xmm0, %xmm1, %xmm097; CHECK-NEXT: vorpd %xmm2, %xmm0, %xmm098; CHECK-NEXT: retq99 %f = fcmp oge <2 x double> %a, %b100 %r = select <2 x i1> %f, <2 x double> <double 0xffffffffffffffff, double 0xffffffffffffffff>, <2 x double> %c101 ret <2 x double> %r102}103 104define <2 x double> @test3f(<2 x double> %a, <2 x double> %b, <2 x double> %c) {105; CHECK-LABEL: test3f:106; CHECK: # %bb.0:107; CHECK-NEXT: vcmpnltpd %xmm1, %xmm0, %xmm0108; CHECK-NEXT: vandpd %xmm2, %xmm0, %xmm0109; CHECK-NEXT: retq110 %f = fcmp olt <2 x double> %a, %b111 %r = select <2 x i1> %f, <2 x double> zeroinitializer, <2 x double> %c112 ret <2 x double> %r113}114 115define <2 x double> @test4f(<2 x double> %a, <2 x double> %b, <2 x double> %c) {116; CHECK-LABEL: test4f:117; CHECK: # %bb.0:118; CHECK-NEXT: vcmpnlepd %xmm1, %xmm0, %xmm0119; CHECK-NEXT: vorpd %xmm2, %xmm0, %xmm0120; CHECK-NEXT: retq121 %f = fcmp ole <2 x double> %a, %b122 %r = select <2 x i1> %f, <2 x double> %c, <2 x double> <double 0xffffffffffffffff, double 0xffffffffffffffff>123 ret <2 x double> %r124}125 126define <2 x double> @test5f(<2 x double> %a, <2 x double> %b, <2 x double> %c) {127; CHECK-LABEL: test5f:128; CHECK: # %bb.0:129; CHECK-NEXT: vcmpnlepd %xmm1, %xmm0, %xmm0130; CHECK-NEXT: retq131 %f = fcmp ugt <2 x double> %a, %b132 %r = select <2 x i1> %f, <2 x double> <double 0xffffffffffffffff, double 0xffffffffffffffff>, <2 x double> zeroinitializer133 ret <2 x double> %r134}135 136define <2 x double> @test6f(<2 x double> %a, <2 x double> %b, <2 x double> %c) {137; CHECK-LABEL: test6f:138; CHECK: # %bb.0:139; CHECK-NEXT: vcmpltpd %xmm0, %xmm1, %xmm0140; CHECK-NEXT: retq141 %f = fcmp ule <2 x double> %a, %b142 %r = select <2 x i1> %f, <2 x double> zeroinitializer, <2 x double> <double 0xffffffffffffffff, double 0xffffffffffffffff>143 ret <2 x double> %r144}145 146define <2 x double> @test7f(<2 x double> %a, <2 x double> %b, ptr %p) {147; CHECK-LABEL: test7f:148; CHECK: # %bb.0:149; CHECK-NEXT: vcmpeqpd %xmm1, %xmm0, %xmm0150; CHECK-NEXT: vandpd (%rdi), %xmm0, %xmm0151; CHECK-NEXT: retq152 %f = fcmp oeq <2 x double> %a, %b153 %l = load <2 x double>, ptr %p, align 16154 %r = select <2 x i1> %f, <2 x double> %l, <2 x double> zeroinitializer155 ret <2 x double> %r156}157 158define i1 @and(i32 %x, i32 %y, i32 %z, i32 %w) {159; CHECK-LABEL: and:160; CHECK: # %bb.0:161; CHECK-NEXT: cmpl %esi, %edi162; CHECK-NEXT: sete %sil163; CHECK-NEXT: cmpl %ecx, %edx164; CHECK-NEXT: setg %al165; CHECK-NEXT: andb %sil, %al166; CHECK-NEXT: retq167 %a = icmp eq i32 %x, %y168 %b = icmp sgt i32 %z, %w169 %s = select i1 %a, i1 %b, i1 false170 ret i1 %s171}172 173define i1 @or(i32 %x, i32 %y, i32 %z, i32 %w) {174; CHECK-LABEL: or:175; CHECK: # %bb.0:176; CHECK-NEXT: cmpl %esi, %edi177; CHECK-NEXT: sete %sil178; CHECK-NEXT: cmpl %ecx, %edx179; CHECK-NEXT: setg %al180; CHECK-NEXT: orb %sil, %al181; CHECK-NEXT: retq182 %a = icmp eq i32 %x, %y183 %b = icmp sgt i32 %z, %w184 %s = select i1 %a, i1 true, i1 %b185 ret i1 %s186}187 188define i1 @and_not(i32 %x, i32 %y, i32 %z, i32 %w) {189; CHECK-LABEL: and_not:190; CHECK: # %bb.0:191; CHECK-NEXT: cmpl %esi, %edi192; CHECK-NEXT: setne %sil193; CHECK-NEXT: cmpl %ecx, %edx194; CHECK-NEXT: setg %al195; CHECK-NEXT: andb %sil, %al196; CHECK-NEXT: retq197 %a = icmp eq i32 %x, %y198 %b = icmp sgt i32 %z, %w199 %s = select i1 %a, i1 false, i1 %b200 ret i1 %s201}202 203define i1 @or_not(i32 %x, i32 %y, i32 %z, i32 %w) {204; CHECK-LABEL: or_not:205; CHECK: # %bb.0:206; CHECK-NEXT: cmpl %esi, %edi207; CHECK-NEXT: setne %sil208; CHECK-NEXT: cmpl %ecx, %edx209; CHECK-NEXT: setg %al210; CHECK-NEXT: orb %sil, %al211; CHECK-NEXT: retq212 %a = icmp eq i32 %x, %y213 %b = icmp sgt i32 %z, %w214 %s = select i1 %a, i1 %b, i1 true215 ret i1 %s216}217 218define <4 x i1> @and_vec(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z, <4 x i32> %w) {219; CHECK-LABEL: and_vec:220; CHECK: # %bb.0:221; CHECK-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0222; CHECK-NEXT: vpcmpgtd %xmm3, %xmm2, %xmm1223; CHECK-NEXT: vpand %xmm1, %xmm0, %xmm0224; CHECK-NEXT: retq225 %a = icmp eq <4 x i32> %x, %y226 %b = icmp sgt <4 x i32> %z, %w227 %s = select <4 x i1> %a, <4 x i1> %b, <4 x i1> zeroinitializer228 ret <4 x i1> %s229}230 231define <4 x i1> @or_vec(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z, <4 x i32> %w) {232; CHECK-LABEL: or_vec:233; CHECK: # %bb.0:234; CHECK-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0235; CHECK-NEXT: vpcmpgtd %xmm3, %xmm2, %xmm1236; CHECK-NEXT: vpor %xmm1, %xmm0, %xmm0237; CHECK-NEXT: retq238 %a = icmp eq <4 x i32> %x, %y239 %b = icmp sgt <4 x i32> %z, %w240 %s = select <4 x i1> %a, <4 x i1> <i1 1, i1 1, i1 1, i1 1>, <4 x i1> %b241 ret <4 x i1> %s242}243 244define <4 x i1> @and_not_vec(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z, <4 x i32> %w) {245; CHECK-LABEL: and_not_vec:246; CHECK: # %bb.0:247; CHECK-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0248; CHECK-NEXT: vpcmpgtd %xmm3, %xmm2, %xmm1249; CHECK-NEXT: vpandn %xmm1, %xmm0, %xmm0250; CHECK-NEXT: retq251 %a = icmp eq <4 x i32> %x, %y252 %b = icmp sgt <4 x i32> %z, %w253 %s = select <4 x i1> %a, <4 x i1> zeroinitializer, <4 x i1> %b254 ret <4 x i1> %s255}256 257define <4 x i1> @or_not_vec(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z, <4 x i32> %w) {258; CHECK-LABEL: or_not_vec:259; CHECK: # %bb.0:260; CHECK-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0261; CHECK-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1262; CHECK-NEXT: vpxor %xmm1, %xmm0, %xmm0263; CHECK-NEXT: vpcmpgtd %xmm3, %xmm2, %xmm1264; CHECK-NEXT: vpor %xmm1, %xmm0, %xmm0265; CHECK-NEXT: retq266 %a = icmp eq <4 x i32> %x, %y267 %b = icmp sgt <4 x i32> %z, %w268 %s = select <4 x i1> %a, <4 x i1> %b, <4 x i1> <i1 1, i1 1, i1 1, i1 1>269 ret <4 x i1> %s270}271