269 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mattr=+sha -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=CHECK --check-prefix=SSE3; RUN: llc < %s -mattr=+sha,+avx2 -mtriple=x86_64-unknown-unknown --show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=AVX4 5declare <4 x i32> @llvm.x86.sha1rnds4(<4 x i32>, <4 x i32>, i8) nounwind readnone6 7define <4 x i32> @test_sha1rnds4rr(<4 x i32> %a, <4 x i32> %b) nounwind uwtable {8; SSE-LABEL: test_sha1rnds4rr:9; SSE: # %bb.0: # %entry10; SSE-NEXT: sha1rnds4 $3, %xmm1, %xmm011; SSE-NEXT: retq12;13; AVX-LABEL: test_sha1rnds4rr:14; AVX: # %bb.0: # %entry15; AVX-NEXT: sha1rnds4 $3, %xmm1, %xmm0 # encoding: [0x0f,0x3a,0xcc,0xc1,0x03]16; AVX-NEXT: retq # encoding: [0xc3]17entry:18 %0 = tail call <4 x i32> @llvm.x86.sha1rnds4(<4 x i32> %a, <4 x i32> %b, i8 3)19 ret <4 x i32> %020}21 22define <4 x i32> @test_sha1rnds4rm(<4 x i32> %a, ptr %b) nounwind uwtable {23; SSE-LABEL: test_sha1rnds4rm:24; SSE: # %bb.0: # %entry25; SSE-NEXT: sha1rnds4 $3, (%rdi), %xmm026; SSE-NEXT: retq27;28; AVX-LABEL: test_sha1rnds4rm:29; AVX: # %bb.0: # %entry30; AVX-NEXT: sha1rnds4 $3, (%rdi), %xmm0 # encoding: [0x0f,0x3a,0xcc,0x07,0x03]31; AVX-NEXT: retq # encoding: [0xc3]32entry:33 %0 = load <4 x i32>, ptr %b34 %1 = tail call <4 x i32> @llvm.x86.sha1rnds4(<4 x i32> %a, <4 x i32> %0, i8 3)35 ret <4 x i32> %136}37 38declare <4 x i32> @llvm.x86.sha1nexte(<4 x i32>, <4 x i32>) nounwind readnone39 40define <4 x i32> @test_sha1nexterr(<4 x i32> %a, <4 x i32> %b) nounwind uwtable {41; SSE-LABEL: test_sha1nexterr:42; SSE: # %bb.0: # %entry43; SSE-NEXT: sha1nexte %xmm1, %xmm044; SSE-NEXT: retq45;46; AVX-LABEL: test_sha1nexterr:47; AVX: # %bb.0: # %entry48; AVX-NEXT: sha1nexte %xmm1, %xmm0 # encoding: [0x0f,0x38,0xc8,0xc1]49; AVX-NEXT: retq # encoding: [0xc3]50entry:51 %0 = tail call <4 x i32> @llvm.x86.sha1nexte(<4 x i32> %a, <4 x i32> %b)52 ret <4 x i32> %053}54 55define <4 x i32> @test_sha1nexterm(<4 x i32> %a, ptr %b) nounwind uwtable {56; SSE-LABEL: test_sha1nexterm:57; SSE: # %bb.0: # %entry58; SSE-NEXT: sha1nexte (%rdi), %xmm059; SSE-NEXT: retq60;61; AVX-LABEL: test_sha1nexterm:62; AVX: # %bb.0: # %entry63; AVX-NEXT: sha1nexte (%rdi), %xmm0 # encoding: [0x0f,0x38,0xc8,0x07]64; AVX-NEXT: retq # encoding: [0xc3]65entry:66 %0 = load <4 x i32>, ptr %b67 %1 = tail call <4 x i32> @llvm.x86.sha1nexte(<4 x i32> %a, <4 x i32> %0)68 ret <4 x i32> %169}70 71declare <4 x i32> @llvm.x86.sha1msg1(<4 x i32>, <4 x i32>) nounwind readnone72 73define <4 x i32> @test_sha1msg1rr(<4 x i32> %a, <4 x i32> %b) nounwind uwtable {74; SSE-LABEL: test_sha1msg1rr:75; SSE: # %bb.0: # %entry76; SSE-NEXT: sha1msg1 %xmm1, %xmm077; SSE-NEXT: retq78;79; AVX-LABEL: test_sha1msg1rr:80; AVX: # %bb.0: # %entry81; AVX-NEXT: sha1msg1 %xmm1, %xmm0 # encoding: [0x0f,0x38,0xc9,0xc1]82; AVX-NEXT: retq # encoding: [0xc3]83entry:84 %0 = tail call <4 x i32> @llvm.x86.sha1msg1(<4 x i32> %a, <4 x i32> %b)85 ret <4 x i32> %086}87 88define <4 x i32> @test_sha1msg1rm(<4 x i32> %a, ptr %b) nounwind uwtable {89; SSE-LABEL: test_sha1msg1rm:90; SSE: # %bb.0: # %entry91; SSE-NEXT: sha1msg1 (%rdi), %xmm092; SSE-NEXT: retq93;94; AVX-LABEL: test_sha1msg1rm:95; AVX: # %bb.0: # %entry96; AVX-NEXT: sha1msg1 (%rdi), %xmm0 # encoding: [0x0f,0x38,0xc9,0x07]97; AVX-NEXT: retq # encoding: [0xc3]98entry:99 %0 = load <4 x i32>, ptr %b100 %1 = tail call <4 x i32> @llvm.x86.sha1msg1(<4 x i32> %a, <4 x i32> %0)101 ret <4 x i32> %1102}103 104declare <4 x i32> @llvm.x86.sha1msg2(<4 x i32>, <4 x i32>) nounwind readnone105 106define <4 x i32> @test_sha1msg2rr(<4 x i32> %a, <4 x i32> %b) nounwind uwtable {107; SSE-LABEL: test_sha1msg2rr:108; SSE: # %bb.0: # %entry109; SSE-NEXT: sha1msg2 %xmm1, %xmm0110; SSE-NEXT: retq111;112; AVX-LABEL: test_sha1msg2rr:113; AVX: # %bb.0: # %entry114; AVX-NEXT: sha1msg2 %xmm1, %xmm0 # encoding: [0x0f,0x38,0xca,0xc1]115; AVX-NEXT: retq # encoding: [0xc3]116entry:117 %0 = tail call <4 x i32> @llvm.x86.sha1msg2(<4 x i32> %a, <4 x i32> %b)118 ret <4 x i32> %0119}120 121define <4 x i32> @test_sha1msg2rm(<4 x i32> %a, ptr %b) nounwind uwtable {122; SSE-LABEL: test_sha1msg2rm:123; SSE: # %bb.0: # %entry124; SSE-NEXT: sha1msg2 (%rdi), %xmm0125; SSE-NEXT: retq126;127; AVX-LABEL: test_sha1msg2rm:128; AVX: # %bb.0: # %entry129; AVX-NEXT: sha1msg2 (%rdi), %xmm0 # encoding: [0x0f,0x38,0xca,0x07]130; AVX-NEXT: retq # encoding: [0xc3]131entry:132 %0 = load <4 x i32>, ptr %b133 %1 = tail call <4 x i32> @llvm.x86.sha1msg2(<4 x i32> %a, <4 x i32> %0)134 ret <4 x i32> %1135}136 137declare <4 x i32> @llvm.x86.sha256rnds2(<4 x i32>, <4 x i32>, <4 x i32>) nounwind readnone138 139define <4 x i32> @test_sha256rnds2rr(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) nounwind uwtable {140; SSE-LABEL: test_sha256rnds2rr:141; SSE: # %bb.0: # %entry142; SSE-NEXT: movaps %xmm0, %xmm3143; SSE-NEXT: movaps %xmm2, %xmm0144; SSE-NEXT: sha256rnds2 %xmm0, %xmm1, %xmm3145; SSE-NEXT: movaps %xmm3, %xmm0146; SSE-NEXT: retq147;148; AVX-LABEL: test_sha256rnds2rr:149; AVX: # %bb.0: # %entry150; AVX-NEXT: vmovaps %xmm0, %xmm3 # encoding: [0xc5,0xf8,0x28,0xd8]151; AVX-NEXT: vmovaps %xmm2, %xmm0 # encoding: [0xc5,0xf8,0x28,0xc2]152; AVX-NEXT: sha256rnds2 %xmm0, %xmm1, %xmm3 # encoding: [0x0f,0x38,0xcb,0xd9]153; AVX-NEXT: vmovaps %xmm3, %xmm0 # encoding: [0xc5,0xf8,0x28,0xc3]154; AVX-NEXT: retq # encoding: [0xc3]155entry:156 %0 = tail call <4 x i32> @llvm.x86.sha256rnds2(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c)157 ret <4 x i32> %0158}159 160define <4 x i32> @test_sha256rnds2rm(<4 x i32> %a, ptr %b, <4 x i32> %c) nounwind uwtable {161; SSE-LABEL: test_sha256rnds2rm:162; SSE: # %bb.0: # %entry163; SSE-NEXT: movaps %xmm0, %xmm2164; SSE-NEXT: movaps %xmm1, %xmm0165; SSE-NEXT: sha256rnds2 %xmm0, (%rdi), %xmm2166; SSE-NEXT: movaps %xmm2, %xmm0167; SSE-NEXT: retq168;169; AVX-LABEL: test_sha256rnds2rm:170; AVX: # %bb.0: # %entry171; AVX-NEXT: vmovaps %xmm0, %xmm2 # encoding: [0xc5,0xf8,0x28,0xd0]172; AVX-NEXT: vmovaps %xmm1, %xmm0 # encoding: [0xc5,0xf8,0x28,0xc1]173; AVX-NEXT: sha256rnds2 %xmm0, (%rdi), %xmm2 # encoding: [0x0f,0x38,0xcb,0x17]174; AVX-NEXT: vmovaps %xmm2, %xmm0 # encoding: [0xc5,0xf8,0x28,0xc2]175; AVX-NEXT: retq # encoding: [0xc3]176entry:177 %0 = load <4 x i32>, ptr %b178 %1 = tail call <4 x i32> @llvm.x86.sha256rnds2(<4 x i32> %a, <4 x i32> %0, <4 x i32> %c)179 ret <4 x i32> %1180}181 182declare <4 x i32> @llvm.x86.sha256msg1(<4 x i32>, <4 x i32>) nounwind readnone183 184define <4 x i32> @test_sha256msg1rr(<4 x i32> %a, <4 x i32> %b) nounwind uwtable {185; SSE-LABEL: test_sha256msg1rr:186; SSE: # %bb.0: # %entry187; SSE-NEXT: sha256msg1 %xmm1, %xmm0188; SSE-NEXT: retq189;190; AVX-LABEL: test_sha256msg1rr:191; AVX: # %bb.0: # %entry192; AVX-NEXT: sha256msg1 %xmm1, %xmm0 # encoding: [0x0f,0x38,0xcc,0xc1]193; AVX-NEXT: retq # encoding: [0xc3]194entry:195 %0 = tail call <4 x i32> @llvm.x86.sha256msg1(<4 x i32> %a, <4 x i32> %b)196 ret <4 x i32> %0197}198 199define <4 x i32> @test_sha256msg1rm(<4 x i32> %a, ptr %b) nounwind uwtable {200; SSE-LABEL: test_sha256msg1rm:201; SSE: # %bb.0: # %entry202; SSE-NEXT: sha256msg1 (%rdi), %xmm0203; SSE-NEXT: retq204;205; AVX-LABEL: test_sha256msg1rm:206; AVX: # %bb.0: # %entry207; AVX-NEXT: sha256msg1 (%rdi), %xmm0 # encoding: [0x0f,0x38,0xcc,0x07]208; AVX-NEXT: retq # encoding: [0xc3]209entry:210 %0 = load <4 x i32>, ptr %b211 %1 = tail call <4 x i32> @llvm.x86.sha256msg1(<4 x i32> %a, <4 x i32> %0)212 ret <4 x i32> %1213}214 215declare <4 x i32> @llvm.x86.sha256msg2(<4 x i32>, <4 x i32>) nounwind readnone216 217define <4 x i32> @test_sha256msg2rr(<4 x i32> %a, <4 x i32> %b) nounwind uwtable {218; SSE-LABEL: test_sha256msg2rr:219; SSE: # %bb.0: # %entry220; SSE-NEXT: sha256msg2 %xmm1, %xmm0221; SSE-NEXT: retq222;223; AVX-LABEL: test_sha256msg2rr:224; AVX: # %bb.0: # %entry225; AVX-NEXT: sha256msg2 %xmm1, %xmm0 # encoding: [0x0f,0x38,0xcd,0xc1]226; AVX-NEXT: retq # encoding: [0xc3]227entry:228 %0 = tail call <4 x i32> @llvm.x86.sha256msg2(<4 x i32> %a, <4 x i32> %b)229 ret <4 x i32> %0230}231 232define <4 x i32> @test_sha256msg2rm(<4 x i32> %a, ptr %b) nounwind uwtable {233; SSE-LABEL: test_sha256msg2rm:234; SSE: # %bb.0: # %entry235; SSE-NEXT: sha256msg2 (%rdi), %xmm0236; SSE-NEXT: retq237;238; AVX-LABEL: test_sha256msg2rm:239; AVX: # %bb.0: # %entry240; AVX-NEXT: sha256msg2 (%rdi), %xmm0 # encoding: [0x0f,0x38,0xcd,0x07]241; AVX-NEXT: retq # encoding: [0xc3]242entry:243 %0 = load <4 x i32>, ptr %b244 %1 = tail call <4 x i32> @llvm.x86.sha256msg2(<4 x i32> %a, <4 x i32> %0)245 ret <4 x i32> %1246}247 248; Make sure we don't forget that sha instructions have no VEX equivalents and thus don't zero YMM/ZMM.249define <8 x i32> @test_sha1rnds4_zero_extend(<4 x i32> %a, ptr %b) nounwind uwtable {250; SSE-LABEL: test_sha1rnds4_zero_extend:251; SSE: # %bb.0: # %entry252; SSE-NEXT: sha1rnds4 $3, (%rdi), %xmm0253; SSE-NEXT: xorps %xmm1, %xmm1254; SSE-NEXT: retq255;256; AVX-LABEL: test_sha1rnds4_zero_extend:257; AVX: # %bb.0: # %entry258; AVX-NEXT: sha1rnds4 $3, (%rdi), %xmm0 # encoding: [0x0f,0x3a,0xcc,0x07,0x03]259; AVX-NEXT: vmovaps %xmm0, %xmm0 # encoding: [0xc5,0xf8,0x28,0xc0]260; AVX-NEXT: retq # encoding: [0xc3]261entry:262 %0 = load <4 x i32>, ptr %b263 %1 = tail call <4 x i32> @llvm.x86.sha1rnds4(<4 x i32> %a, <4 x i32> %0, i8 3)264 %2 = shufflevector <4 x i32> %1, <4 x i32> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>265 ret <8 x i32> %2266}267;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:268; CHECK: {{.*}}269