831 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=i686-unknown < %s | FileCheck %s --check-prefix=X863; RUN: llc -mtriple=x86_64-unknown < %s | FileCheck %s --check-prefix=X644 5@array = weak dso_local global [4 x i32] zeroinitializer6 7define dso_local i32 @test_lshr_and(i32 %x) {8; X86-LABEL: test_lshr_and:9; X86: # %bb.0:10; X86-NEXT: movl {{[0-9]+}}(%esp), %eax11; X86-NEXT: andl $12, %eax12; X86-NEXT: movl array(%eax), %eax13; X86-NEXT: retl14;15; X64-LABEL: test_lshr_and:16; X64: # %bb.0:17; X64-NEXT: # kill: def $edi killed $edi def $rdi18; X64-NEXT: andl $12, %edi19; X64-NEXT: movl array(%rdi), %eax20; X64-NEXT: retq21 %tmp2 = lshr i32 %x, 222 %tmp3 = and i32 %tmp2, 323 %tmp4 = getelementptr [4 x i32], ptr @array, i32 0, i32 %tmp324 %tmp5 = load i32, ptr %tmp4, align 425 ret i32 %tmp526}27 28define dso_local ptr @test_exact1(i32 %a, i32 %b, ptr %x) {29; X86-LABEL: test_exact1:30; X86: # %bb.0:31; X86-NEXT: movl {{[0-9]+}}(%esp), %eax32; X86-NEXT: subl {{[0-9]+}}(%esp), %eax33; X86-NEXT: sarl %eax34; X86-NEXT: addl {{[0-9]+}}(%esp), %eax35; X86-NEXT: retl36;37; X64-LABEL: test_exact1:38; X64: # %bb.0:39; X64-NEXT: subl %edi, %esi40; X64-NEXT: sarl $3, %esi41; X64-NEXT: movslq %esi, %rax42; X64-NEXT: leaq (%rdx,%rax,4), %rax43; X64-NEXT: retq44 %sub = sub i32 %b, %a45 %shr = ashr exact i32 %sub, 346 %gep = getelementptr inbounds i32, ptr %x, i32 %shr47 ret ptr %gep48}49 50define dso_local ptr @test_exact2(i32 %a, i32 %b, ptr %x) {51; X86-LABEL: test_exact2:52; X86: # %bb.0:53; X86-NEXT: movl {{[0-9]+}}(%esp), %eax54; X86-NEXT: subl {{[0-9]+}}(%esp), %eax55; X86-NEXT: sarl %eax56; X86-NEXT: addl {{[0-9]+}}(%esp), %eax57; X86-NEXT: retl58;59; X64-LABEL: test_exact2:60; X64: # %bb.0:61; X64-NEXT: subl %edi, %esi62; X64-NEXT: sarl $3, %esi63; X64-NEXT: movslq %esi, %rax64; X64-NEXT: leaq (%rdx,%rax,4), %rax65; X64-NEXT: retq66 %sub = sub i32 %b, %a67 %shr = ashr exact i32 %sub, 368 %gep = getelementptr inbounds i32, ptr %x, i32 %shr69 ret ptr %gep70}71 72define dso_local ptr @test_exact3(i32 %a, i32 %b, ptr %x) {73; X86-LABEL: test_exact3:74; X86: # %bb.0:75; X86-NEXT: movl {{[0-9]+}}(%esp), %eax76; X86-NEXT: subl {{[0-9]+}}(%esp), %eax77; X86-NEXT: addl {{[0-9]+}}(%esp), %eax78; X86-NEXT: retl79;80; X64-LABEL: test_exact3:81; X64: # %bb.0:82; X64-NEXT: subl %edi, %esi83; X64-NEXT: sarl $2, %esi84; X64-NEXT: movslq %esi, %rax85; X64-NEXT: leaq (%rdx,%rax,4), %rax86; X64-NEXT: retq87 %sub = sub i32 %b, %a88 %shr = ashr exact i32 %sub, 289 %gep = getelementptr inbounds i32, ptr %x, i32 %shr90 ret ptr %gep91}92 93define dso_local ptr @test_exact4(i32 %a, i32 %b, ptr %x) {94; X86-LABEL: test_exact4:95; X86: # %bb.0:96; X86-NEXT: movl {{[0-9]+}}(%esp), %eax97; X86-NEXT: subl {{[0-9]+}}(%esp), %eax98; X86-NEXT: shrl %eax99; X86-NEXT: addl {{[0-9]+}}(%esp), %eax100; X86-NEXT: retl101;102; X64-LABEL: test_exact4:103; X64: # %bb.0:104; X64-NEXT: # kill: def $esi killed $esi def $rsi105; X64-NEXT: subl %edi, %esi106; X64-NEXT: shrl %esi107; X64-NEXT: leaq (%rsi,%rdx), %rax108; X64-NEXT: retq109 %sub = sub i32 %b, %a110 %shr = lshr exact i32 %sub, 3111 %gep = getelementptr inbounds i32, ptr %x, i32 %shr112 ret ptr %gep113}114 115define dso_local ptr @test_exact5(i32 %a, i32 %b, ptr %x) {116; X86-LABEL: test_exact5:117; X86: # %bb.0:118; X86-NEXT: movl {{[0-9]+}}(%esp), %eax119; X86-NEXT: subl {{[0-9]+}}(%esp), %eax120; X86-NEXT: shrl %eax121; X86-NEXT: addl {{[0-9]+}}(%esp), %eax122; X86-NEXT: retl123;124; X64-LABEL: test_exact5:125; X64: # %bb.0:126; X64-NEXT: # kill: def $esi killed $esi def $rsi127; X64-NEXT: subl %edi, %esi128; X64-NEXT: shrl %esi129; X64-NEXT: leaq (%rsi,%rdx), %rax130; X64-NEXT: retq131 %sub = sub i32 %b, %a132 %shr = lshr exact i32 %sub, 3133 %gep = getelementptr inbounds i32, ptr %x, i32 %shr134 ret ptr %gep135}136 137define dso_local ptr @test_exact6(i32 %a, i32 %b, ptr %x) {138; X86-LABEL: test_exact6:139; X86: # %bb.0:140; X86-NEXT: movl {{[0-9]+}}(%esp), %eax141; X86-NEXT: subl {{[0-9]+}}(%esp), %eax142; X86-NEXT: addl {{[0-9]+}}(%esp), %eax143; X86-NEXT: retl144;145; X64-LABEL: test_exact6:146; X64: # %bb.0:147; X64-NEXT: # kill: def $esi killed $esi def $rsi148; X64-NEXT: subl %edi, %esi149; X64-NEXT: leaq (%rsi,%rdx), %rax150; X64-NEXT: retq151 %sub = sub i32 %b, %a152 %shr = lshr exact i32 %sub, 2153 %gep = getelementptr inbounds i32, ptr %x, i32 %shr154 ret ptr %gep155}156 157; PR42644 - https://bugs.llvm.org/show_bug.cgi?id=42644158 159define i64 @ashr_add_shl_i32(i64 %r) nounwind {160; X86-LABEL: ashr_add_shl_i32:161; X86: # %bb.0:162; X86-NEXT: movl {{[0-9]+}}(%esp), %eax163; X86-NEXT: incl %eax164; X86-NEXT: movl %eax, %edx165; X86-NEXT: sarl $31, %edx166; X86-NEXT: retl167;168; X64-LABEL: ashr_add_shl_i32:169; X64: # %bb.0:170; X64-NEXT: incl %edi171; X64-NEXT: movslq %edi, %rax172; X64-NEXT: retq173 %conv = shl i64 %r, 32174 %sext = add i64 %conv, 4294967296175 %conv1 = ashr i64 %sext, 32176 ret i64 %conv1177}178 179define i64 @ashr_add_shl_i8(i64 %r) nounwind {180; X86-LABEL: ashr_add_shl_i8:181; X86: # %bb.0:182; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax183; X86-NEXT: addb $2, %al184; X86-NEXT: movsbl %al, %eax185; X86-NEXT: movl %eax, %edx186; X86-NEXT: sarl $31, %edx187; X86-NEXT: retl188;189; X64-LABEL: ashr_add_shl_i8:190; X64: # %bb.0:191; X64-NEXT: addb $2, %dil192; X64-NEXT: movsbq %dil, %rax193; X64-NEXT: retq194 %conv = shl i64 %r, 56195 %sext = add i64 %conv, 144115188075855872196 %conv1 = ashr i64 %sext, 56197 ret i64 %conv1198}199 200define <4 x i32> @ashr_add_shl_v4i8(<4 x i32> %r) nounwind {201; X86-LABEL: ashr_add_shl_v4i8:202; X86: # %bb.0:203; X86-NEXT: pushl %edi204; X86-NEXT: pushl %esi205; X86-NEXT: movl {{[0-9]+}}(%esp), %eax206; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx207; X86-NEXT: movzbl {{[0-9]+}}(%esp), %edx208; X86-NEXT: movb {{[0-9]+}}(%esp), %ch209; X86-NEXT: movb {{[0-9]+}}(%esp), %dh210; X86-NEXT: incb %dh211; X86-NEXT: movsbl %dh, %esi212; X86-NEXT: incb %ch213; X86-NEXT: movsbl %ch, %edi214; X86-NEXT: incb %dl215; X86-NEXT: movsbl %dl, %edx216; X86-NEXT: incb %cl217; X86-NEXT: movsbl %cl, %ecx218; X86-NEXT: movl %ecx, 12(%eax)219; X86-NEXT: movl %edx, 8(%eax)220; X86-NEXT: movl %edi, 4(%eax)221; X86-NEXT: movl %esi, (%eax)222; X86-NEXT: popl %esi223; X86-NEXT: popl %edi224; X86-NEXT: retl $4225;226; X64-LABEL: ashr_add_shl_v4i8:227; X64: # %bb.0:228; X64-NEXT: pslld $24, %xmm0229; X64-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0230; X64-NEXT: psrad $24, %xmm0231; X64-NEXT: retq232 %conv = shl <4 x i32> %r, <i32 24, i32 24, i32 24, i32 24>233 %sext = add <4 x i32> %conv, <i32 16777216, i32 16777216, i32 16777216, i32 16777216>234 %conv1 = ashr <4 x i32> %sext, <i32 24, i32 24, i32 24, i32 24>235 ret <4 x i32> %conv1236}237 238define i64 @ashr_add_shl_i36(i64 %r) nounwind {239; X86-LABEL: ashr_add_shl_i36:240; X86: # %bb.0:241; X86-NEXT: movl {{[0-9]+}}(%esp), %edx242; X86-NEXT: shll $4, %edx243; X86-NEXT: movl %edx, %eax244; X86-NEXT: sarl $4, %eax245; X86-NEXT: sarl $31, %edx246; X86-NEXT: retl247;248; X64-LABEL: ashr_add_shl_i36:249; X64: # %bb.0:250; X64-NEXT: movq %rdi, %rax251; X64-NEXT: shlq $36, %rax252; X64-NEXT: sarq $36, %rax253; X64-NEXT: retq254 %conv = shl i64 %r, 36255 %sext = add i64 %conv, 4294967296256 %conv1 = ashr i64 %sext, 36257 ret i64 %conv1258}259 260define i64 @ashr_add_shl_mismatch_shifts1(i64 %r) nounwind {261; X86-LABEL: ashr_add_shl_mismatch_shifts1:262; X86: # %bb.0:263; X86-NEXT: movl {{[0-9]+}}(%esp), %eax264; X86-NEXT: incl %eax265; X86-NEXT: movl %eax, %edx266; X86-NEXT: sarl $31, %edx267; X86-NEXT: retl268;269; X64-LABEL: ashr_add_shl_mismatch_shifts1:270; X64: # %bb.0:271; X64-NEXT: shlq $8, %rdi272; X64-NEXT: movabsq $4294967296, %rax # imm = 0x100000000273; X64-NEXT: addq %rdi, %rax274; X64-NEXT: sarq $32, %rax275; X64-NEXT: retq276 %conv = shl i64 %r, 8277 %sext = add i64 %conv, 4294967296278 %conv1 = ashr i64 %sext, 32279 ret i64 %conv1280}281 282define i64 @ashr_add_shl_mismatch_shifts2(i64 %r) nounwind {283; X86-LABEL: ashr_add_shl_mismatch_shifts2:284; X86: # %bb.0:285; X86-NEXT: movl {{[0-9]+}}(%esp), %eax286; X86-NEXT: movl {{[0-9]+}}(%esp), %edx287; X86-NEXT: shrl $8, %edx288; X86-NEXT: incl %edx289; X86-NEXT: shrdl $8, %edx, %eax290; X86-NEXT: shrl $8, %edx291; X86-NEXT: retl292;293; X64-LABEL: ashr_add_shl_mismatch_shifts2:294; X64: # %bb.0:295; X64-NEXT: shrq $8, %rdi296; X64-NEXT: movabsq $4294967296, %rax # imm = 0x100000000297; X64-NEXT: addq %rdi, %rax298; X64-NEXT: shrq $8, %rax299; X64-NEXT: retq300 %conv = lshr i64 %r, 8301 %sext = add i64 %conv, 4294967296302 %conv1 = ashr i64 %sext, 8303 ret i64 %conv1304}305 306define dso_local i32 @ashr_add_shl_i32_i8_extra_use1(i32 %r, ptr %p) nounwind {307; X86-LABEL: ashr_add_shl_i32_i8_extra_use1:308; X86: # %bb.0:309; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx310; X86-NEXT: movl {{[0-9]+}}(%esp), %eax311; X86-NEXT: shll $24, %eax312; X86-NEXT: addl $33554432, %eax # imm = 0x2000000313; X86-NEXT: movl %eax, (%ecx)314; X86-NEXT: sarl $24, %eax315; X86-NEXT: retl316;317; X64-LABEL: ashr_add_shl_i32_i8_extra_use1:318; X64: # %bb.0:319; X64-NEXT: # kill: def $edi killed $edi def $rdi320; X64-NEXT: shll $24, %edi321; X64-NEXT: leal 33554432(%rdi), %eax322; X64-NEXT: movl %eax, (%rsi)323; X64-NEXT: sarl $24, %eax324; X64-NEXT: retq325 %conv = shl i32 %r, 24326 %sext = add i32 %conv, 33554432327 store i32 %sext, ptr %p328 %conv1 = ashr i32 %sext, 24329 ret i32 %conv1330}331 332define dso_local i32 @ashr_add_shl_i32_i8_extra_use2(i32 %r, ptr %p) nounwind {333; X86-LABEL: ashr_add_shl_i32_i8_extra_use2:334; X86: # %bb.0:335; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx336; X86-NEXT: movl {{[0-9]+}}(%esp), %eax337; X86-NEXT: shll $24, %eax338; X86-NEXT: movl %eax, (%ecx)339; X86-NEXT: addl $33554432, %eax # imm = 0x2000000340; X86-NEXT: sarl $24, %eax341; X86-NEXT: retl342;343; X64-LABEL: ashr_add_shl_i32_i8_extra_use2:344; X64: # %bb.0:345; X64-NEXT: # kill: def $edi killed $edi def $rdi346; X64-NEXT: shll $24, %edi347; X64-NEXT: movl %edi, (%rsi)348; X64-NEXT: leal 33554432(%rdi), %eax349; X64-NEXT: sarl $24, %eax350; X64-NEXT: retq351 %conv = shl i32 %r, 24352 store i32 %conv, ptr %p353 %sext = add i32 %conv, 33554432354 %conv1 = ashr i32 %sext, 24355 ret i32 %conv1356}357 358define dso_local i32 @ashr_add_shl_i32_i8_extra_use3(i32 %r, ptr %p1, ptr %p2) nounwind {359; X86-LABEL: ashr_add_shl_i32_i8_extra_use3:360; X86: # %bb.0:361; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx362; X86-NEXT: movl {{[0-9]+}}(%esp), %edx363; X86-NEXT: movl {{[0-9]+}}(%esp), %eax364; X86-NEXT: shll $24, %eax365; X86-NEXT: movl %eax, (%edx)366; X86-NEXT: addl $33554432, %eax # imm = 0x2000000367; X86-NEXT: movl %eax, (%ecx)368; X86-NEXT: sarl $24, %eax369; X86-NEXT: retl370;371; X64-LABEL: ashr_add_shl_i32_i8_extra_use3:372; X64: # %bb.0:373; X64-NEXT: # kill: def $edi killed $edi def $rdi374; X64-NEXT: shll $24, %edi375; X64-NEXT: movl %edi, (%rsi)376; X64-NEXT: leal 33554432(%rdi), %eax377; X64-NEXT: movl %eax, (%rdx)378; X64-NEXT: sarl $24, %eax379; X64-NEXT: retq380 %conv = shl i32 %r, 24381 store i32 %conv, ptr %p1382 %sext = add i32 %conv, 33554432383 store i32 %sext, ptr %p2384 %conv1 = ashr i32 %sext, 24385 ret i32 %conv1386}387 388%"class.QPainterPath" = type { double, double, i32 }389 390define dso_local void @PR42880(i32 %t0) {391; X86-LABEL: PR42880:392; X86: # %bb.0:393; X86-NEXT: testb %al, %al394; X86-NEXT: je .LBB16_1395; X86-NEXT: # %bb.2: # %if396; X86-NEXT: .LBB16_1: # %then397;398; X64-LABEL: PR42880:399; X64: # %bb.0:400; X64-NEXT: testb %al, %al401; X64-NEXT: je .LBB16_1402; X64-NEXT: # %bb.2: # %if403; X64-NEXT: .LBB16_1: # %then404 %sub = add nsw i32 %t0, -1405 %add.ptr.i94 = getelementptr inbounds %"class.QPainterPath", ptr null, i32 %sub406 %x = ptrtoint ptr %add.ptr.i94 to i32407 %sub2 = sub i32 %x, 0408 %div = sdiv exact i32 %sub2, 24409 br i1 poison, label %if, label %then410 411then:412 %t1 = xor i32 %div, -1413 unreachable414 415if:416 unreachable417}418 419; The mul here is the equivalent of (neg (shl X, 32)).420define i64 @ashr_add_neg_shl_i32(i64 %r) nounwind {421; X86-LABEL: ashr_add_neg_shl_i32:422; X86: # %bb.0:423; X86-NEXT: movl $1, %eax424; X86-NEXT: subl {{[0-9]+}}(%esp), %eax425; X86-NEXT: movl %eax, %edx426; X86-NEXT: sarl $31, %edx427; X86-NEXT: retl428;429; X64-LABEL: ashr_add_neg_shl_i32:430; X64: # %bb.0:431; X64-NEXT: movl $1, %eax432; X64-NEXT: subl %edi, %eax433; X64-NEXT: cltq434; X64-NEXT: retq435 %conv = mul i64 %r, -4294967296436 %sext = add i64 %conv, 4294967296437 %conv1 = ashr i64 %sext, 32438 ret i64 %conv1439}440 441; The mul here is the equivalent of (neg (shl X, 56)).442define i64 @ashr_add_neg_shl_i8(i64 %r) nounwind {443; X86-LABEL: ashr_add_neg_shl_i8:444; X86: # %bb.0:445; X86-NEXT: movb $2, %al446; X86-NEXT: subb {{[0-9]+}}(%esp), %al447; X86-NEXT: movsbl %al, %eax448; X86-NEXT: movl %eax, %edx449; X86-NEXT: sarl $31, %edx450; X86-NEXT: retl451;452; X64-LABEL: ashr_add_neg_shl_i8:453; X64: # %bb.0:454; X64-NEXT: movb $2, %al455; X64-NEXT: subb %dil, %al456; X64-NEXT: movsbq %al, %rax457; X64-NEXT: retq458 %conv = mul i64 %r, -72057594037927936459 %sext = add i64 %conv, 144115188075855872460 %conv1 = ashr i64 %sext, 56461 ret i64 %conv1462}463 464; The mul here is the equivalent of (neg (shl X, 24)).465define <4 x i32> @ashr_add_neg_shl_v4i8(<4 x i32> %r) nounwind {466; X86-LABEL: ashr_add_neg_shl_v4i8:467; X86: # %bb.0:468; X86-NEXT: pushl %edi469; X86-NEXT: pushl %esi470; X86-NEXT: movl {{[0-9]+}}(%esp), %eax471; X86-NEXT: movb $1, %cl472; X86-NEXT: movb $1, %dl473; X86-NEXT: subb {{[0-9]+}}(%esp), %dl474; X86-NEXT: movsbl %dl, %edx475; X86-NEXT: movb $1, %ch476; X86-NEXT: subb {{[0-9]+}}(%esp), %ch477; X86-NEXT: movsbl %ch, %esi478; X86-NEXT: movb $1, %ch479; X86-NEXT: subb {{[0-9]+}}(%esp), %ch480; X86-NEXT: movsbl %ch, %edi481; X86-NEXT: subb {{[0-9]+}}(%esp), %cl482; X86-NEXT: movsbl %cl, %ecx483; X86-NEXT: movl %ecx, 12(%eax)484; X86-NEXT: movl %edi, 8(%eax)485; X86-NEXT: movl %esi, 4(%eax)486; X86-NEXT: movl %edx, (%eax)487; X86-NEXT: popl %esi488; X86-NEXT: popl %edi489; X86-NEXT: retl $4490;491; X64-LABEL: ashr_add_neg_shl_v4i8:492; X64: # %bb.0:493; X64-NEXT: pslld $24, %xmm0494; X64-NEXT: movdqa {{.*#+}} xmm1 = [16777216,16777216,16777216,16777216]495; X64-NEXT: psubd %xmm0, %xmm1496; X64-NEXT: psrad $24, %xmm1497; X64-NEXT: movdqa %xmm1, %xmm0498; X64-NEXT: retq499 %conv = mul <4 x i32> %r, <i32 -16777216, i32 -16777216, i32 -16777216, i32 -16777216>500 %sext = add <4 x i32> %conv, <i32 16777216, i32 16777216, i32 16777216, i32 16777216>501 %conv1 = ashr <4 x i32> %sext, <i32 24, i32 24, i32 24, i32 24>502 ret <4 x i32> %conv1503}504 505define i32 @or_tree_with_shifts_i32(i32 %a, i32 %b, i32 %c, i32 %d) {506; X86-LABEL: or_tree_with_shifts_i32:507; X86: # %bb.0:508; X86-NEXT: movl {{[0-9]+}}(%esp), %eax509; X86-NEXT: orl {{[0-9]+}}(%esp), %eax510; X86-NEXT: shll $16, %eax511; X86-NEXT: orl {{[0-9]+}}(%esp), %eax512; X86-NEXT: orl {{[0-9]+}}(%esp), %eax513; X86-NEXT: retl514;515; X64-LABEL: or_tree_with_shifts_i32:516; X64: # %bb.0:517; X64-NEXT: movl %esi, %eax518; X64-NEXT: orl %edx, %edi519; X64-NEXT: shll $16, %edi520; X64-NEXT: orl %ecx, %eax521; X64-NEXT: orl %edi, %eax522; X64-NEXT: retq523 %a.shifted = shl i32 %a, 16524 %c.shifted = shl i32 %c, 16525 %or.ab = or i32 %a.shifted, %b526 %or.cd = or i32 %c.shifted, %d527 %r = or i32 %or.ab, %or.cd528 ret i32 %r529}530 531define i32 @xor_tree_with_shifts_i32(i32 %a, i32 %b, i32 %c, i32 %d) {532; X86-LABEL: xor_tree_with_shifts_i32:533; X86: # %bb.0:534; X86-NEXT: movl {{[0-9]+}}(%esp), %eax535; X86-NEXT: xorl {{[0-9]+}}(%esp), %eax536; X86-NEXT: shrl $16, %eax537; X86-NEXT: xorl {{[0-9]+}}(%esp), %eax538; X86-NEXT: xorl {{[0-9]+}}(%esp), %eax539; X86-NEXT: retl540;541; X64-LABEL: xor_tree_with_shifts_i32:542; X64: # %bb.0:543; X64-NEXT: movl %esi, %eax544; X64-NEXT: xorl %edx, %edi545; X64-NEXT: shrl $16, %edi546; X64-NEXT: xorl %ecx, %eax547; X64-NEXT: xorl %edi, %eax548; X64-NEXT: retq549 %a.shifted = lshr i32 %a, 16550 %c.shifted = lshr i32 %c, 16551 %xor.ab = xor i32 %a.shifted, %b552 %xor.cd = xor i32 %d, %c.shifted553 %r = xor i32 %xor.ab, %xor.cd554 ret i32 %r555}556 557define i32 @and_tree_with_shifts_i32(i32 %a, i32 %b, i32 %c, i32 %d) {558; X86-LABEL: and_tree_with_shifts_i32:559; X86: # %bb.0:560; X86-NEXT: movswl {{[0-9]+}}(%esp), %eax561; X86-NEXT: movswl {{[0-9]+}}(%esp), %ecx562; X86-NEXT: andl {{[0-9]+}}(%esp), %ecx563; X86-NEXT: andl {{[0-9]+}}(%esp), %eax564; X86-NEXT: andl %ecx, %eax565; X86-NEXT: retl566;567; X64-LABEL: and_tree_with_shifts_i32:568; X64: # %bb.0:569; X64-NEXT: movl %esi, %eax570; X64-NEXT: andl %edx, %edi571; X64-NEXT: sarl $16, %edi572; X64-NEXT: andl %ecx, %eax573; X64-NEXT: andl %edi, %eax574; X64-NEXT: retq575 %a.shifted = ashr i32 %a, 16576 %c.shifted = ashr i32 %c, 16577 %and.ab = and i32 %b, %a.shifted578 %and.cd = and i32 %c.shifted, %d579 %r = and i32 %and.ab, %and.cd580 ret i32 %r581}582 583define i32 @logic_tree_with_shifts_var_i32(i32 %a, i32 %b, i32 %c, i32 %d, i32 %s) {584; X86-LABEL: logic_tree_with_shifts_var_i32:585; X86: # %bb.0:586; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx587; X86-NEXT: movl {{[0-9]+}}(%esp), %eax588; X86-NEXT: orl {{[0-9]+}}(%esp), %eax589; X86-NEXT: shll %cl, %eax590; X86-NEXT: orl {{[0-9]+}}(%esp), %eax591; X86-NEXT: orl {{[0-9]+}}(%esp), %eax592; X86-NEXT: retl593;594; X64-LABEL: logic_tree_with_shifts_var_i32:595; X64: # %bb.0:596; X64-NEXT: movl %ecx, %eax597; X64-NEXT: orl %edx, %edi598; X64-NEXT: movl %r8d, %ecx599; X64-NEXT: shll %cl, %edi600; X64-NEXT: orl %esi, %eax601; X64-NEXT: orl %edi, %eax602; X64-NEXT: retq603 %a.shifted = shl i32 %a, %s604 %c.shifted = shl i32 %c, %s605 %or.ab = or i32 %b, %a.shifted606 %or.cd = or i32 %d, %c.shifted607 %r = or i32 %or.ab, %or.cd608 ret i32 %r609}610 611define i32 @logic_tree_with_mismatching_shifts_i32(i32 %a, i32 %b, i32 %c, i32 %d) {612; X86-LABEL: logic_tree_with_mismatching_shifts_i32:613; X86: # %bb.0:614; X86-NEXT: movl {{[0-9]+}}(%esp), %eax615; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx616; X86-NEXT: shll $15, %ecx617; X86-NEXT: shll $16, %eax618; X86-NEXT: orl {{[0-9]+}}(%esp), %ecx619; X86-NEXT: orl {{[0-9]+}}(%esp), %eax620; X86-NEXT: orl %ecx, %eax621; X86-NEXT: retl622;623; X64-LABEL: logic_tree_with_mismatching_shifts_i32:624; X64: # %bb.0:625; X64-NEXT: movl %edx, %eax626; X64-NEXT: shll $15, %edi627; X64-NEXT: shll $16, %eax628; X64-NEXT: orl %esi, %edi629; X64-NEXT: orl %ecx, %eax630; X64-NEXT: orl %edi, %eax631; X64-NEXT: retq632 %a.shifted = shl i32 %a, 15633 %c.shifted = shl i32 %c, 16634 %or.ab = or i32 %a.shifted, %b635 %or.cd = or i32 %c.shifted, %d636 %r = or i32 %or.ab, %or.cd637 ret i32 %r638}639 640define i32 @logic_tree_with_mismatching_shifts2_i32(i32 %a, i32 %b, i32 %c, i32 %d) {641; X86-LABEL: logic_tree_with_mismatching_shifts2_i32:642; X86: # %bb.0:643; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax644; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx645; X86-NEXT: shll $16, %ecx646; X86-NEXT: orl {{[0-9]+}}(%esp), %ecx647; X86-NEXT: orl {{[0-9]+}}(%esp), %eax648; X86-NEXT: orl %ecx, %eax649; X86-NEXT: retl650;651; X64-LABEL: logic_tree_with_mismatching_shifts2_i32:652; X64: # %bb.0:653; X64-NEXT: movl %edx, %eax654; X64-NEXT: shll $16, %edi655; X64-NEXT: shrl $16, %eax656; X64-NEXT: orl %esi, %edi657; X64-NEXT: orl %ecx, %eax658; X64-NEXT: orl %edi, %eax659; X64-NEXT: retq660 %a.shifted = shl i32 %a, 16661 %c.shifted = lshr i32 %c, 16662 %or.ab = or i32 %a.shifted, %b663 %or.cd = or i32 %c.shifted, %d664 %r = or i32 %or.ab, %or.cd665 ret i32 %r666}667 668define <4 x i32> @or_tree_with_shifts_vec_i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {669; X86-LABEL: or_tree_with_shifts_vec_i32:670; X86: # %bb.0:671; X86-NEXT: pushl %edi672; X86-NEXT: .cfi_def_cfa_offset 8673; X86-NEXT: pushl %esi674; X86-NEXT: .cfi_def_cfa_offset 12675; X86-NEXT: .cfi_offset %esi, -12676; X86-NEXT: .cfi_offset %edi, -8677; X86-NEXT: movl {{[0-9]+}}(%esp), %eax678; X86-NEXT: movl {{[0-9]+}}(%esp), %edi679; X86-NEXT: movl {{[0-9]+}}(%esp), %esi680; X86-NEXT: movl {{[0-9]+}}(%esp), %edx681; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx682; X86-NEXT: orl {{[0-9]+}}(%esp), %ecx683; X86-NEXT: shll $16, %ecx684; X86-NEXT: orl {{[0-9]+}}(%esp), %ecx685; X86-NEXT: orl {{[0-9]+}}(%esp), %ecx686; X86-NEXT: orl {{[0-9]+}}(%esp), %edx687; X86-NEXT: shll $16, %edx688; X86-NEXT: orl {{[0-9]+}}(%esp), %edx689; X86-NEXT: orl {{[0-9]+}}(%esp), %edx690; X86-NEXT: orl {{[0-9]+}}(%esp), %esi691; X86-NEXT: shll $16, %esi692; X86-NEXT: orl {{[0-9]+}}(%esp), %esi693; X86-NEXT: orl {{[0-9]+}}(%esp), %esi694; X86-NEXT: orl {{[0-9]+}}(%esp), %edi695; X86-NEXT: shll $16, %edi696; X86-NEXT: orl {{[0-9]+}}(%esp), %edi697; X86-NEXT: orl {{[0-9]+}}(%esp), %edi698; X86-NEXT: movl %edi, 12(%eax)699; X86-NEXT: movl %esi, 8(%eax)700; X86-NEXT: movl %edx, 4(%eax)701; X86-NEXT: movl %ecx, (%eax)702; X86-NEXT: popl %esi703; X86-NEXT: .cfi_def_cfa_offset 8704; X86-NEXT: popl %edi705; X86-NEXT: .cfi_def_cfa_offset 4706; X86-NEXT: retl $4707;708; X64-LABEL: or_tree_with_shifts_vec_i32:709; X64: # %bb.0:710; X64-NEXT: por %xmm2, %xmm0711; X64-NEXT: pslld $16, %xmm0712; X64-NEXT: por %xmm3, %xmm1713; X64-NEXT: por %xmm1, %xmm0714; X64-NEXT: retq715 %a.shifted = shl <4 x i32> %a, <i32 16, i32 16, i32 16, i32 16>716 %c.shifted = shl <4 x i32> %c, <i32 16, i32 16, i32 16, i32 16>717 %or.ab = or <4 x i32> %a.shifted, %b718 %or.cd = or <4 x i32> %c.shifted, %d719 %r = or <4 x i32> %or.ab, %or.cd720 ret <4 x i32> %r721}722 723define <4 x i32> @or_tree_with_mismatching_shifts_vec_i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {724; X86-LABEL: or_tree_with_mismatching_shifts_vec_i32:725; X86: # %bb.0:726; X86-NEXT: pushl %edi727; X86-NEXT: .cfi_def_cfa_offset 8728; X86-NEXT: pushl %esi729; X86-NEXT: .cfi_def_cfa_offset 12730; X86-NEXT: .cfi_offset %esi, -12731; X86-NEXT: .cfi_offset %edi, -8732; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx733; X86-NEXT: movl {{[0-9]+}}(%esp), %edx734; X86-NEXT: movl {{[0-9]+}}(%esp), %esi735; X86-NEXT: movl {{[0-9]+}}(%esp), %edi736; X86-NEXT: movl {{[0-9]+}}(%esp), %eax737; X86-NEXT: shll $16, %eax738; X86-NEXT: shll $17, %ecx739; X86-NEXT: orl {{[0-9]+}}(%esp), %eax740; X86-NEXT: orl {{[0-9]+}}(%esp), %ecx741; X86-NEXT: orl %eax, %ecx742; X86-NEXT: movl {{[0-9]+}}(%esp), %eax743; X86-NEXT: shll $16, %eax744; X86-NEXT: shll $17, %edx745; X86-NEXT: orl {{[0-9]+}}(%esp), %eax746; X86-NEXT: orl {{[0-9]+}}(%esp), %edx747; X86-NEXT: orl %eax, %edx748; X86-NEXT: movl {{[0-9]+}}(%esp), %eax749; X86-NEXT: shll $16, %eax750; X86-NEXT: shll $17, %esi751; X86-NEXT: orl {{[0-9]+}}(%esp), %eax752; X86-NEXT: orl {{[0-9]+}}(%esp), %esi753; X86-NEXT: orl %eax, %esi754; X86-NEXT: movl {{[0-9]+}}(%esp), %eax755; X86-NEXT: shll $16, %eax756; X86-NEXT: shll $17, %edi757; X86-NEXT: orl {{[0-9]+}}(%esp), %eax758; X86-NEXT: orl {{[0-9]+}}(%esp), %edi759; X86-NEXT: orl %eax, %edi760; X86-NEXT: movl {{[0-9]+}}(%esp), %eax761; X86-NEXT: movl %ecx, 12(%eax)762; X86-NEXT: movl %edx, 8(%eax)763; X86-NEXT: movl %esi, 4(%eax)764; X86-NEXT: movl %edi, (%eax)765; X86-NEXT: popl %esi766; X86-NEXT: .cfi_def_cfa_offset 8767; X86-NEXT: popl %edi768; X86-NEXT: .cfi_def_cfa_offset 4769; X86-NEXT: retl $4770;771; X64-LABEL: or_tree_with_mismatching_shifts_vec_i32:772; X64: # %bb.0:773; X64-NEXT: pslld $16, %xmm0774; X64-NEXT: pslld $17, %xmm2775; X64-NEXT: por %xmm1, %xmm0776; X64-NEXT: por %xmm3, %xmm2777; X64-NEXT: por %xmm2, %xmm0778; X64-NEXT: retq779 %a.shifted = shl <4 x i32> %a, <i32 16, i32 16, i32 16, i32 16>780 %c.shifted = shl <4 x i32> %c, <i32 17, i32 17, i32 17, i32 17>781 %or.ab = or <4 x i32> %a.shifted, %b782 %or.cd = or <4 x i32> %c.shifted, %d783 %r = or <4 x i32> %or.ab, %or.cd784 ret <4 x i32> %r785}786 787; Reproducer for a DAGCombiner::combineShiftOfShiftedLogic bug. DAGCombiner788; need to check that the sum of the shift amounts fits in i8, which is the789; legal type used to described X86 shift amounts. Verify that we do not try to790; create a shift with 130+160 as shift amount, and verify that the stored791; value do not depend on %a1.792define void @combineShiftOfShiftedLogic(i128 %a1, i32 %a2, ptr %p) {793; X86-LABEL: combineShiftOfShiftedLogic:794; X86: # %bb.0:795; X86-NEXT: pushl %ebp796; X86-NEXT: .cfi_def_cfa_offset 8797; X86-NEXT: .cfi_offset %ebp, -8798; X86-NEXT: movl %esp, %ebp799; X86-NEXT: .cfi_def_cfa_register %ebp800; X86-NEXT: andl $-16, %esp801; X86-NEXT: subl $16, %esp802; X86-NEXT: movl 24(%ebp), %eax803; X86-NEXT: movl 28(%ebp), %ecx804; X86-NEXT: movl %eax, 20(%ecx)805; X86-NEXT: movl $0, 16(%ecx)806; X86-NEXT: movl $0, 12(%ecx)807; X86-NEXT: movl $0, 8(%ecx)808; X86-NEXT: movl $0, 4(%ecx)809; X86-NEXT: movl $0, (%ecx)810; X86-NEXT: movl %ebp, %esp811; X86-NEXT: popl %ebp812; X86-NEXT: .cfi_def_cfa %esp, 4813; X86-NEXT: retl814;815; X64-LABEL: combineShiftOfShiftedLogic:816; X64: # %bb.0:817; X64-NEXT: # kill: def $edx killed $edx def $rdx818; X64-NEXT: shlq $32, %rdx819; X64-NEXT: movq %rdx, 16(%rcx)820; X64-NEXT: movq $0, 8(%rcx)821; X64-NEXT: movq $0, (%rcx)822; X64-NEXT: retq823 %zext1 = zext i128 %a1 to i192824 %zext2 = zext i32 %a2 to i192825 %shl = shl i192 %zext1, 130826 %or = or i192 %shl, %zext2827 %res = shl i192 %or, 160828 store i192 %res, ptr %p, align 8829 ret void830}831