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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=i686-unknown-unknown -verify-coalescing | FileCheck %s3 4define ptr @test1(ptr %P, i32 %X) {5; CHECK-LABEL: test1:6; CHECK: # %bb.0:7; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax8; CHECK-NEXT: andl $-4, %eax9; CHECK-NEXT: addl {{[0-9]+}}(%esp), %eax10; CHECK-NEXT: retl11 %Y = lshr i32 %X, 212 %gep.upgrd.1 = zext i32 %Y to i6413 %P2 = getelementptr i32, ptr %P, i64 %gep.upgrd.114 ret ptr %P215}16 17define ptr @test2(ptr %P, i32 %X) {18; CHECK-LABEL: test2:19; CHECK: # %bb.0:20; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax21; CHECK-NEXT: shll $4, %eax22; CHECK-NEXT: addl {{[0-9]+}}(%esp), %eax23; CHECK-NEXT: retl24 %Y = shl i32 %X, 225 %gep.upgrd.2 = zext i32 %Y to i6426 %P2 = getelementptr i32, ptr %P, i64 %gep.upgrd.227 ret ptr %P228}29 30define ptr @test3(ptr %P, i32 %X) {31; CHECK-LABEL: test3:32; CHECK: # %bb.0:33; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax34; CHECK-NEXT: andl $-4, %eax35; CHECK-NEXT: addl {{[0-9]+}}(%esp), %eax36; CHECK-NEXT: retl37 %Y = ashr i32 %X, 238 %P2 = getelementptr i32, ptr %P, i32 %Y39 ret ptr %P240}41 42define fastcc i32 @test4(ptr %d) {43; CHECK-LABEL: test4:44; CHECK: # %bb.0:45; CHECK-NEXT: movzbl 3(%ecx), %eax46; CHECK-NEXT: retl47 %tmp4 = load i32, ptr %d48 %tmp512 = lshr i32 %tmp4, 2449 ret i32 %tmp51250}51 52; Ensure that we don't fold away shifts which have multiple uses, as they are53; just re-introduced for the second use.54 55define i64 @test5(i16 %i, ptr %arr) {56; CHECK-LABEL: test5:57; CHECK: # %bb.0:58; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx59; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %eax60; CHECK-NEXT: shrl $11, %eax61; CHECK-NEXT: xorl %edx, %edx62; CHECK-NEXT: addl (%ecx,%eax,4), %eax63; CHECK-NEXT: setb %dl64; CHECK-NEXT: retl65 %i.zext = zext i16 %i to i3266 %index = lshr i32 %i.zext, 1167 %index.zext = zext i32 %index to i6468 %val.ptr = getelementptr inbounds i32, ptr %arr, i64 %index.zext69 %val = load i32, ptr %val.ptr70 %val.zext = zext i32 %val to i6471 %sum = add i64 %val.zext, %index.zext72 ret i64 %sum73}74 75; We should not crash because an undef shift was created.76 77define i32 @overshift(i32 %a) {78; CHECK-LABEL: overshift:79; CHECK: # %bb.0:80; CHECK-NEXT: retl81 %shr = lshr i32 %a, 3382 %xor = xor i32 1, %shr83 ret i32 %xor84}85 86; Should be possible to adjust the pointer and narrow the load to 16 bits.87define i16 @srl_load_narrowing1(ptr %arg) {88; CHECK-LABEL: srl_load_narrowing1:89; CHECK: # %bb.0:90; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax91; CHECK-NEXT: movzwl 1(%eax), %eax92; CHECK-NEXT: retl93 %tmp1 = load i32, ptr %arg, align 194 %tmp2 = lshr i32 %tmp1, 895 %tmp3 = trunc i32 %tmp2 to i1696 ret i16 %tmp397}98 99define i16 @srl_load_narrowing2(ptr %arg) {100; CHECK-LABEL: srl_load_narrowing2:101; CHECK: # %bb.0:102; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax103; CHECK-NEXT: movzbl 3(%eax), %eax104; CHECK-NEXT: # kill: def $ax killed $ax killed $eax105; CHECK-NEXT: retl106 %tmp1 = load i32, ptr %arg, align 1107 %tmp2 = lshr i32 %tmp1, 24108 %tmp3 = trunc i32 %tmp2 to i16109 ret i16 %tmp3110}111