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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512vl,+avx512dq,+avx512bw | FileCheck %s -check-prefixes=AVX512VL3; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512vl,+avx512dq,+avx512bw,+avx512vbmi2 | FileCheck %s -check-prefixes=AVX512VBMI4; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver4 | FileCheck %s -check-prefixes=ZNVER45 6; i512 shifts hidden inside 512-bit vectors.7 8define <8 x i64> @shl_i512_1(<8 x i64> %a) {9; AVX512VL-LABEL: shl_i512_1:10; AVX512VL: # %bb.0:11; AVX512VL-NEXT: valignq {{.*#+}} zmm1 = zmm0[3,4,5,6,7,0,1,2]12; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm213; AVX512VL-NEXT: vpaddq %xmm0, %xmm0, %xmm314; AVX512VL-NEXT: vpshufd {{.*#+}} xmm4 = xmm0[2,3,2,3]15; AVX512VL-NEXT: vpsrlq $63, %xmm4, %xmm416; AVX512VL-NEXT: vpaddq %xmm2, %xmm2, %xmm217; AVX512VL-NEXT: vpor %xmm4, %xmm2, %xmm218; AVX512VL-NEXT: vinserti128 $1, %xmm2, %ymm3, %ymm219; AVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm320; AVX512VL-NEXT: vpaddq %ymm3, %ymm3, %ymm321; AVX512VL-NEXT: vpsrlq $63, %ymm1, %ymm122; AVX512VL-NEXT: vpor %ymm1, %ymm3, %ymm123; AVX512VL-NEXT: vinserti64x4 $1, %ymm1, %zmm2, %zmm124; AVX512VL-NEXT: vpsrlq $63, %zmm0, %zmm225; AVX512VL-NEXT: vpshufd {{.*#+}} zmm0 = zmm0[2,3,2,3,6,7,6,7,10,11,10,11,14,15,14,15]26; AVX512VL-NEXT: vpaddq %zmm0, %zmm0, %zmm027; AVX512VL-NEXT: vporq %zmm2, %zmm0, %zmm028; AVX512VL-NEXT: vpunpcklqdq {{.*#+}} zmm0 = zmm1[0],zmm0[0],zmm1[2],zmm0[2],zmm1[4],zmm0[4],zmm1[6],zmm0[6]29; AVX512VL-NEXT: retq30;31; AVX512VBMI-LABEL: shl_i512_1:32; AVX512VBMI: # %bb.0:33; AVX512VBMI-NEXT: vextracti32x4 $2, %zmm0, %xmm134; AVX512VBMI-NEXT: vextracti128 $1, %ymm0, %xmm235; AVX512VBMI-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[2,3,2,3]36; AVX512VBMI-NEXT: vpshldq $1, %xmm3, %xmm2, %xmm337; AVX512VBMI-NEXT: vpaddq %xmm0, %xmm0, %xmm438; AVX512VBMI-NEXT: vinserti128 $1, %xmm3, %ymm4, %ymm339; AVX512VBMI-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm140; AVX512VBMI-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[2,3,2,3,6,7,6,7]41; AVX512VBMI-NEXT: vextracti64x4 $1, %zmm0, %ymm242; AVX512VBMI-NEXT: vpshldq $1, %ymm1, %ymm2, %ymm143; AVX512VBMI-NEXT: vinserti64x4 $1, %ymm1, %zmm3, %zmm144; AVX512VBMI-NEXT: vpshufd {{.*#+}} zmm2 = zmm0[2,3,2,3,6,7,6,7,10,11,10,11,14,15,14,15]45; AVX512VBMI-NEXT: vpshldq $1, %zmm0, %zmm2, %zmm046; AVX512VBMI-NEXT: vpunpcklqdq {{.*#+}} zmm0 = zmm1[0],zmm0[0],zmm1[2],zmm0[2],zmm1[4],zmm0[4],zmm1[6],zmm0[6]47; AVX512VBMI-NEXT: retq48;49; ZNVER4-LABEL: shl_i512_1:50; ZNVER4: # %bb.0:51; ZNVER4-NEXT: vextracti32x4 $2, %zmm0, %xmm152; ZNVER4-NEXT: vextracti128 $1, %ymm0, %xmm253; ZNVER4-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[2,3,2,3]54; ZNVER4-NEXT: vpaddq %xmm0, %xmm0, %xmm455; ZNVER4-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm156; ZNVER4-NEXT: vpshldq $1, %xmm3, %xmm2, %xmm357; ZNVER4-NEXT: vextracti64x4 $1, %zmm0, %ymm258; ZNVER4-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[2,3,2,3,6,7,6,7]59; ZNVER4-NEXT: vpshldq $1, %ymm1, %ymm2, %ymm160; ZNVER4-NEXT: vinserti128 $1, %xmm3, %ymm4, %ymm361; ZNVER4-NEXT: vinserti64x4 $1, %ymm1, %zmm3, %zmm162; ZNVER4-NEXT: vpshufd {{.*#+}} zmm3 = zmm0[2,3,2,3,6,7,6,7,10,11,10,11,14,15,14,15]63; ZNVER4-NEXT: vpshldq $1, %zmm0, %zmm3, %zmm064; ZNVER4-NEXT: vpunpcklqdq {{.*#+}} zmm0 = zmm1[0],zmm0[0],zmm1[2],zmm0[2],zmm1[4],zmm0[4],zmm1[6],zmm0[6]65; ZNVER4-NEXT: retq66 %d = bitcast <8 x i64> %a to i51267 %s = shl i512 %d, 168 %r = bitcast i512 %s to <8 x i64>69 ret <8 x i64> %r70}71 72define <8 x i64> @lshr_i512_1(<8 x i64> %a) {73; AVX512VL-LABEL: lshr_i512_1:74; AVX512VL: # %bb.0:75; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm176; AVX512VL-NEXT: vextracti32x4 $2, %zmm0, %xmm277; AVX512VL-NEXT: vextracti32x4 $3, %zmm0, %xmm378; AVX512VL-NEXT: vpsllq $63, %xmm3, %xmm479; AVX512VL-NEXT: vpshufd {{.*#+}} xmm5 = xmm2[2,3,2,3]80; AVX512VL-NEXT: vpsrlq $1, %xmm5, %xmm581; AVX512VL-NEXT: vpor %xmm5, %xmm4, %xmm482; AVX512VL-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[2,3,2,3]83; AVX512VL-NEXT: vpsrlq $1, %xmm3, %xmm384; AVX512VL-NEXT: vinserti128 $1, %xmm3, %ymm4, %ymm385; AVX512VL-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm186; AVX512VL-NEXT: vpsllq $63, %ymm1, %ymm187; AVX512VL-NEXT: vpshufd {{.*#+}} ymm2 = ymm0[2,3,2,3,6,7,6,7]88; AVX512VL-NEXT: vpsrlq $1, %ymm2, %ymm289; AVX512VL-NEXT: vpor %ymm2, %ymm1, %ymm190; AVX512VL-NEXT: vinserti64x4 $1, %ymm3, %zmm1, %zmm191; AVX512VL-NEXT: vpsrlq $1, %zmm0, %zmm292; AVX512VL-NEXT: vpshufd {{.*#+}} zmm0 = zmm0[2,3,2,3,6,7,6,7,10,11,10,11,14,15,14,15]93; AVX512VL-NEXT: vpsllq $63, %zmm0, %zmm094; AVX512VL-NEXT: vporq %zmm2, %zmm0, %zmm095; AVX512VL-NEXT: vpunpcklqdq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[2],zmm1[2],zmm0[4],zmm1[4],zmm0[6],zmm1[6]96; AVX512VL-NEXT: retq97;98; AVX512VBMI-LABEL: lshr_i512_1:99; AVX512VBMI: # %bb.0:100; AVX512VBMI-NEXT: vextracti128 $1, %ymm0, %xmm1101; AVX512VBMI-NEXT: vextracti32x4 $3, %zmm0, %xmm2102; AVX512VBMI-NEXT: vextracti32x4 $2, %zmm0, %xmm3103; AVX512VBMI-NEXT: vpshufd {{.*#+}} xmm4 = xmm3[2,3,2,3]104; AVX512VBMI-NEXT: vpshldq $63, %xmm4, %xmm2, %xmm4105; AVX512VBMI-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[2,3,2,3]106; AVX512VBMI-NEXT: vpsrlq $1, %xmm2, %xmm2107; AVX512VBMI-NEXT: vinserti128 $1, %xmm2, %ymm4, %ymm2108; AVX512VBMI-NEXT: vinserti128 $1, %xmm3, %ymm1, %ymm1109; AVX512VBMI-NEXT: vpshufd {{.*#+}} ymm3 = ymm0[2,3,2,3,6,7,6,7]110; AVX512VBMI-NEXT: vpshldq $63, %ymm3, %ymm1, %ymm1111; AVX512VBMI-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm1112; AVX512VBMI-NEXT: vpshufd {{.*#+}} zmm2 = zmm0[2,3,2,3,6,7,6,7,10,11,10,11,14,15,14,15]113; AVX512VBMI-NEXT: vpshldq $63, %zmm0, %zmm2, %zmm0114; AVX512VBMI-NEXT: vpunpcklqdq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[2],zmm1[2],zmm0[4],zmm1[4],zmm0[6],zmm1[6]115; AVX512VBMI-NEXT: retq116;117; ZNVER4-LABEL: lshr_i512_1:118; ZNVER4: # %bb.0:119; ZNVER4-NEXT: vextracti32x4 $2, %zmm0, %xmm3120; ZNVER4-NEXT: vextracti128 $1, %ymm0, %xmm1121; ZNVER4-NEXT: vextracti32x4 $3, %zmm0, %xmm2122; ZNVER4-NEXT: vpshufd {{.*#+}} xmm4 = xmm3[2,3,2,3]123; ZNVER4-NEXT: vinserti128 $1, %xmm3, %ymm1, %ymm1124; ZNVER4-NEXT: vpshufd {{.*#+}} ymm3 = ymm0[2,3,2,3,6,7,6,7]125; ZNVER4-NEXT: vpshldq $63, %xmm4, %xmm2, %xmm4126; ZNVER4-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[2,3,2,3]127; ZNVER4-NEXT: vpshldq $63, %ymm3, %ymm1, %ymm1128; ZNVER4-NEXT: vpshufd {{.*#+}} zmm3 = zmm0[2,3,2,3,6,7,6,7,10,11,10,11,14,15,14,15]129; ZNVER4-NEXT: vpsrlq $1, %xmm2, %xmm2130; ZNVER4-NEXT: vpshldq $63, %zmm0, %zmm3, %zmm0131; ZNVER4-NEXT: vinserti128 $1, %xmm2, %ymm4, %ymm2132; ZNVER4-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm1133; ZNVER4-NEXT: vpunpcklqdq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[2],zmm1[2],zmm0[4],zmm1[4],zmm0[6],zmm1[6]134; ZNVER4-NEXT: retq135 %d = bitcast <8 x i64> %a to i512136 %s = lshr i512 %d, 1137 %r = bitcast i512 %s to <8 x i64>138 ret <8 x i64> %r139}140 141define <8 x i64> @ashr_i512_1(<8 x i64> %a) {142; AVX512VL-LABEL: ashr_i512_1:143; AVX512VL: # %bb.0:144; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm1145; AVX512VL-NEXT: vextracti32x4 $2, %zmm0, %xmm2146; AVX512VL-NEXT: vextracti32x4 $3, %zmm0, %xmm3147; AVX512VL-NEXT: vpsllq $63, %xmm3, %xmm4148; AVX512VL-NEXT: vpshufd {{.*#+}} xmm5 = xmm2[2,3,2,3]149; AVX512VL-NEXT: vpsrlq $1, %xmm5, %xmm5150; AVX512VL-NEXT: vpor %xmm5, %xmm4, %xmm4151; AVX512VL-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[2,3,2,3]152; AVX512VL-NEXT: vpsraq $1, %xmm3, %xmm3153; AVX512VL-NEXT: vinserti128 $1, %xmm3, %ymm4, %ymm3154; AVX512VL-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1155; AVX512VL-NEXT: vpsllq $63, %ymm1, %ymm1156; AVX512VL-NEXT: vpshufd {{.*#+}} ymm2 = ymm0[2,3,2,3,6,7,6,7]157; AVX512VL-NEXT: vpsrlq $1, %ymm2, %ymm2158; AVX512VL-NEXT: vpor %ymm2, %ymm1, %ymm1159; AVX512VL-NEXT: vinserti64x4 $1, %ymm3, %zmm1, %zmm1160; AVX512VL-NEXT: vpsrlq $1, %zmm0, %zmm2161; AVX512VL-NEXT: vpshufd {{.*#+}} zmm0 = zmm0[2,3,2,3,6,7,6,7,10,11,10,11,14,15,14,15]162; AVX512VL-NEXT: vpsllq $63, %zmm0, %zmm0163; AVX512VL-NEXT: vporq %zmm2, %zmm0, %zmm0164; AVX512VL-NEXT: vpunpcklqdq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[2],zmm1[2],zmm0[4],zmm1[4],zmm0[6],zmm1[6]165; AVX512VL-NEXT: retq166;167; AVX512VBMI-LABEL: ashr_i512_1:168; AVX512VBMI: # %bb.0:169; AVX512VBMI-NEXT: vextracti128 $1, %ymm0, %xmm1170; AVX512VBMI-NEXT: vextracti32x4 $3, %zmm0, %xmm2171; AVX512VBMI-NEXT: vextracti32x4 $2, %zmm0, %xmm3172; AVX512VBMI-NEXT: vpshufd {{.*#+}} xmm4 = xmm3[2,3,2,3]173; AVX512VBMI-NEXT: vpshldq $63, %xmm4, %xmm2, %xmm4174; AVX512VBMI-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[2,3,2,3]175; AVX512VBMI-NEXT: vpsraq $1, %xmm2, %xmm2176; AVX512VBMI-NEXT: vinserti128 $1, %xmm2, %ymm4, %ymm2177; AVX512VBMI-NEXT: vinserti128 $1, %xmm3, %ymm1, %ymm1178; AVX512VBMI-NEXT: vpshufd {{.*#+}} ymm3 = ymm0[2,3,2,3,6,7,6,7]179; AVX512VBMI-NEXT: vpshldq $63, %ymm3, %ymm1, %ymm1180; AVX512VBMI-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm1181; AVX512VBMI-NEXT: vpshufd {{.*#+}} zmm2 = zmm0[2,3,2,3,6,7,6,7,10,11,10,11,14,15,14,15]182; AVX512VBMI-NEXT: vpshldq $63, %zmm0, %zmm2, %zmm0183; AVX512VBMI-NEXT: vpunpcklqdq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[2],zmm1[2],zmm0[4],zmm1[4],zmm0[6],zmm1[6]184; AVX512VBMI-NEXT: retq185;186; ZNVER4-LABEL: ashr_i512_1:187; ZNVER4: # %bb.0:188; ZNVER4-NEXT: vextracti32x4 $2, %zmm0, %xmm3189; ZNVER4-NEXT: vextracti128 $1, %ymm0, %xmm1190; ZNVER4-NEXT: vextracti32x4 $3, %zmm0, %xmm2191; ZNVER4-NEXT: vpshufd {{.*#+}} xmm4 = xmm3[2,3,2,3]192; ZNVER4-NEXT: vinserti128 $1, %xmm3, %ymm1, %ymm1193; ZNVER4-NEXT: vpshufd {{.*#+}} ymm3 = ymm0[2,3,2,3,6,7,6,7]194; ZNVER4-NEXT: vpshldq $63, %xmm4, %xmm2, %xmm4195; ZNVER4-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[2,3,2,3]196; ZNVER4-NEXT: vpshldq $63, %ymm3, %ymm1, %ymm1197; ZNVER4-NEXT: vpshufd {{.*#+}} zmm3 = zmm0[2,3,2,3,6,7,6,7,10,11,10,11,14,15,14,15]198; ZNVER4-NEXT: vpsraq $1, %xmm2, %xmm2199; ZNVER4-NEXT: vpshldq $63, %zmm0, %zmm3, %zmm0200; ZNVER4-NEXT: vinserti128 $1, %xmm2, %ymm4, %ymm2201; ZNVER4-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm1202; ZNVER4-NEXT: vpunpcklqdq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[2],zmm1[2],zmm0[4],zmm1[4],zmm0[6],zmm1[6]203; ZNVER4-NEXT: retq204 %d = bitcast <8 x i64> %a to i512205 %s = ashr i512 %d, 1206 %r = bitcast i512 %s to <8 x i64>207 ret <8 x i64> %r208}209