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1; RUN: llc < %s -O1 -mtriple=i386-apple-darwin -x86-asm-syntax=intel | FileCheck %s2;3; Interesting test case where %tmp1220 = xor i32 %tmp862, %tmp592 and4; %tmp1676 = xor i32 %tmp1634, %tmp1530 have zero demanded bits after5; DAGCombiner optimization pass. These are changed to undef and in turn6; the successor shl(s) become shl undef, 1. This pattern then matches7; shl x, 1 -> add x, x. add undef, undef doesn't guarantee the low8; order bit is zero and is incorrect.9;10; See rdar://9453156 and rdar://9487392.11;12 13; Use intel syntax, or "shl" might hit "pushl".14 15; CHECK-NOT: shl16define i32 @foo(ptr %a0, ptr %a2) nounwind {17entry:18 %tmp0 = alloca i819 %tmp1 = alloca i3220 store i8 1, ptr %tmp021 %tmp921.i7845 = load i8, ptr %a0, align 122 %tmp309 = xor i8 %tmp921.i7845, 10423 %tmp592 = zext i8 %tmp309 to i3224 %tmp862 = xor i32 1293461297, %tmp59225 %tmp1220 = xor i32 %tmp862, %tmp59226 %tmp1506 = shl i32 %tmp1220, 127 %tmp1530 = sub i32 %tmp592, %tmp150628 %tmp1557 = sub i32 %tmp1530, 54276762929 %tmp1607 = and i32 %tmp1557, 130 store i32 %tmp1607, ptr %tmp131 %tmp1634 = and i32 %tmp1607, 208030924632 %tmp1676 = xor i32 %tmp1634, %tmp153033 %tmp1618 = shl i32 %tmp1676, 134 %tmp1645 = sub i32 %tmp862, %tmp161835 %tmp1697 = and i32 %tmp1645, 136 store i32 %tmp1697, ptr %a237 ret i32 %tmp160738}39 40; CHECK-NOT: shl41; shl undef, 0 -> undef42define i32 @foo2_undef() nounwind {43entry:44 %tmp2 = shl i32 undef, 0;45 ret i32 %tmp246}47 48; CHECK-NOT: shl49; shl undef, x -> 050define i32 @foo1_undef(ptr %a0) nounwind {51entry:52 %tmp1 = load i32, ptr %a0, align 153 %tmp2 = shl i32 undef, %tmp1;54 ret i32 %tmp255}56