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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2 | FileCheck %s --check-prefix=SSE3; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2 | FileCheck %s --check-prefix=AVX4 5; If targetShrinkDemandedConstant extends xor/or constants ensure it extends from the msb of the active bits6define <4 x i32> @sext_vector_constants(<4 x i32> %a0) {7; SSE-LABEL: sext_vector_constants:8; SSE: # %bb.0:9; SSE-NEXT: psrld $9, %xmm010; SSE-NEXT: pslld $26, %xmm011; SSE-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm012; SSE-NEXT: retq13;14; AVX-LABEL: sext_vector_constants:15; AVX: # %bb.0:16; AVX-NEXT: vpsrld $9, %xmm0, %xmm017; AVX-NEXT: vpslld $26, %xmm0, %xmm018; AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm019; AVX-NEXT: retq20 %1 = lshr <4 x i32> %a0, <i32 9, i32 9, i32 9, i32 9>21 %2 = xor <4 x i32> %1, <i32 314523200, i32 -2085372448, i32 144496960, i32 1532773600>22 %3 = shl <4 x i32> %2, <i32 26, i32 26, i32 26, i32 26>23 ret <4 x i32> %324}25