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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=skylake-avx512 | FileCheck %s --check-prefixes=CHECK,CHECK-SKX3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=icelake-server | FileCheck %s --check-prefixes=CHECK,CHECK-ICX4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=CHECK,CHECK-V45; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=znver4 | FileCheck %s --check-prefixes=CHECK,CHECK-ZNVER46; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=znver5 | FileCheck %s --check-prefixes=CHECK,CHECK-ZNVER47 8 9define <4 x i32> @shuf_rot_v4i32_1032(<4 x i32> %x) {10; CHECK-SKX-LABEL: shuf_rot_v4i32_1032:11; CHECK-SKX: # %bb.0:12; CHECK-SKX-NEXT: vpaddd %xmm0, %xmm0, %xmm013; CHECK-SKX-NEXT: vprolq $32, %xmm0, %xmm014; CHECK-SKX-NEXT: retq15;16; CHECK-ICX-LABEL: shuf_rot_v4i32_1032:17; CHECK-ICX: # %bb.0:18; CHECK-ICX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,0,3,2]19; CHECK-ICX-NEXT: vpaddd %xmm0, %xmm0, %xmm020; CHECK-ICX-NEXT: retq21;22; CHECK-V4-LABEL: shuf_rot_v4i32_1032:23; CHECK-V4: # %bb.0:24; CHECK-V4-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,0,3,2]25; CHECK-V4-NEXT: vpaddd %xmm0, %xmm0, %xmm026; CHECK-V4-NEXT: retq27;28; CHECK-ZNVER4-LABEL: shuf_rot_v4i32_1032:29; CHECK-ZNVER4: # %bb.0:30; CHECK-ZNVER4-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,0,3,2]31; CHECK-ZNVER4-NEXT: vpaddd %xmm0, %xmm0, %xmm032; CHECK-ZNVER4-NEXT: retq33 %x1 = add <4 x i32> %x, %x34 %r = shufflevector <4 x i32> %x1, <4 x i32> zeroinitializer, <4 x i32> <i32 1, i32 0, i32 3, i32 2>35 ret <4 x i32> %r36}37 38define <8 x i32> @shuf_rot_v8i32_10325476(<8 x i32> %x) {39; CHECK-SKX-LABEL: shuf_rot_v8i32_10325476:40; CHECK-SKX: # %bb.0:41; CHECK-SKX-NEXT: vpaddd %ymm0, %ymm0, %ymm042; CHECK-SKX-NEXT: vprolq $32, %ymm0, %ymm043; CHECK-SKX-NEXT: retq44;45; CHECK-ICX-LABEL: shuf_rot_v8i32_10325476:46; CHECK-ICX: # %bb.0:47; CHECK-ICX-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[1,0,3,2,5,4,7,6]48; CHECK-ICX-NEXT: vpaddd %ymm0, %ymm0, %ymm049; CHECK-ICX-NEXT: retq50;51; CHECK-V4-LABEL: shuf_rot_v8i32_10325476:52; CHECK-V4: # %bb.0:53; CHECK-V4-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[1,0,3,2,5,4,7,6]54; CHECK-V4-NEXT: vpaddd %ymm0, %ymm0, %ymm055; CHECK-V4-NEXT: retq56;57; CHECK-ZNVER4-LABEL: shuf_rot_v8i32_10325476:58; CHECK-ZNVER4: # %bb.0:59; CHECK-ZNVER4-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[1,0,3,2,5,4,7,6]60; CHECK-ZNVER4-NEXT: vpaddd %ymm0, %ymm0, %ymm061; CHECK-ZNVER4-NEXT: retq62 %x1 = add <8 x i32> %x, %x63 %r = shufflevector <8 x i32> %x1, <8 x i32> zeroinitializer, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>64 ret <8 x i32> %r65}66 67define <16 x i32> @shuf_rot_v16i32_1032547698111013121514(<16 x i32> %x) {68; CHECK-SKX-LABEL: shuf_rot_v16i32_1032547698111013121514:69; CHECK-SKX: # %bb.0:70; CHECK-SKX-NEXT: vpaddd %zmm0, %zmm0, %zmm071; CHECK-SKX-NEXT: vprolq $32, %zmm0, %zmm072; CHECK-SKX-NEXT: retq73;74; CHECK-ICX-LABEL: shuf_rot_v16i32_1032547698111013121514:75; CHECK-ICX: # %bb.0:76; CHECK-ICX-NEXT: vpshufd {{.*#+}} zmm0 = zmm0[1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14]77; CHECK-ICX-NEXT: vpaddd %zmm0, %zmm0, %zmm078; CHECK-ICX-NEXT: retq79;80; CHECK-V4-LABEL: shuf_rot_v16i32_1032547698111013121514:81; CHECK-V4: # %bb.0:82; CHECK-V4-NEXT: vpshufd {{.*#+}} zmm0 = zmm0[1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14]83; CHECK-V4-NEXT: vpaddd %zmm0, %zmm0, %zmm084; CHECK-V4-NEXT: retq85;86; CHECK-ZNVER4-LABEL: shuf_rot_v16i32_1032547698111013121514:87; CHECK-ZNVER4: # %bb.0:88; CHECK-ZNVER4-NEXT: vpshufd {{.*#+}} zmm0 = zmm0[1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14]89; CHECK-ZNVER4-NEXT: vpaddd %zmm0, %zmm0, %zmm090; CHECK-ZNVER4-NEXT: retq91 %x1 = add <16 x i32> %x, %x92 %r = shufflevector <16 x i32> %x1, <16 x i32> zeroinitializer, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>93 ret <16 x i32> %r94}95 96define <8 x i16> @shuf_rot_v8i16_10325476(<8 x i16> %x) {97; CHECK-LABEL: shuf_rot_v8i16_10325476:98; CHECK: # %bb.0:99; CHECK-NEXT: vpaddw %xmm0, %xmm0, %xmm0100; CHECK-NEXT: vprold $16, %xmm0, %xmm0101; CHECK-NEXT: retq102 %x1 = add <8 x i16> %x, %x103 %r = shufflevector <8 x i16> %x1, <8 x i16> zeroinitializer, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>104 ret <8 x i16> %r105}106 107define <16 x i16> @shuf_rot_v16i16_1032547698111013121514(<16 x i16> %x) {108; CHECK-LABEL: shuf_rot_v16i16_1032547698111013121514:109; CHECK: # %bb.0:110; CHECK-NEXT: vpaddw %ymm0, %ymm0, %ymm0111; CHECK-NEXT: vprold $16, %ymm0, %ymm0112; CHECK-NEXT: retq113 %x1 = add <16 x i16> %x, %x114 %r = shufflevector <16 x i16> %x1, <16 x i16> zeroinitializer, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>115 ret <16 x i16> %r116}117 118define <32 x i16> @shuf_rot_v32i16_1234056749101181314151217181916212223202527272429303128(<32 x i16> %x) {119; CHECK-LABEL: shuf_rot_v32i16_1234056749101181314151217181916212223202527272429303128:120; CHECK: # %bb.0:121; CHECK-NEXT: vpaddw %zmm0, %zmm0, %zmm0122; CHECK-NEXT: vprolq $48, %zmm0, %zmm0123; CHECK-NEXT: retq124 %x1 = add <32 x i16> %x, %x125 %r = shufflevector <32 x i16> %x1, <32 x i16> zeroinitializer, <32 x i32> <i32 1,i32 2,i32 3,i32 0,i32 5,i32 6,i32 7,i32 4,i32 9,i32 10,i32 11,i32 8,i32 13,i32 14,i32 15,i32 12,i32 17,i32 18,i32 19,i32 16,i32 21,i32 22,i32 23,i32 20,i32 25,i32 26,i32 27,i32 24,i32 29,i32 30,i32 31,i32 28>126 ret <32 x i16> %r127}128 129define <16 x i8> @shuf_rot_v16i8_2301674510118914151213(<16 x i8> %x) {130; CHECK-LABEL: shuf_rot_v16i8_2301674510118914151213:131; CHECK: # %bb.0:132; CHECK-NEXT: vpaddb %xmm0, %xmm0, %xmm0133; CHECK-NEXT: vprold $16, %xmm0, %xmm0134; CHECK-NEXT: retq135 %x1 = add <16 x i8> %x, %x136 %r = shufflevector <16 x i8> %x1, <16 x i8> zeroinitializer, <16 x i32> <i32 2, i32 3, i32 0, i32 1, i32 6, i32 7, i32 4, i32 5, i32 10, i32 11, i32 8, i32 9, i32 14, i32 15, i32 12, i32 13>137 ret <16 x i8> %r138}139 140define <32 x i8> @shuf_rot_v32i8_230167451011891415121318191617222320212627242530312829(<32 x i8> %x) {141; CHECK-LABEL: shuf_rot_v32i8_230167451011891415121318191617222320212627242530312829:142; CHECK: # %bb.0:143; CHECK-NEXT: vpaddb %ymm0, %ymm0, %ymm0144; CHECK-NEXT: vprold $16, %ymm0, %ymm0145; CHECK-NEXT: retq146 %x1 = add <32 x i8> %x, %x147 %r = shufflevector <32 x i8> %x1, <32 x i8> zeroinitializer, <32 x i32> <i32 2, i32 3, i32 0, i32 1, i32 6, i32 7, i32 4, i32 5, i32 10, i32 11, i32 8, i32 9, i32 14, i32 15, i32 12, i32 13, i32 18, i32 19, i32 16, i32 17, i32 22, i32 23, i32 20, i32 21, i32 26, i32 27, i32 24, i32 25, i32 30, i32 31, i32 28, i32 29>148 ret <32 x i8> %r149}150 151define <64 x i8> @shuf_rot_v64i8_3012745611891015121314191617182320212227242526312829303532333439363738434041424744454651484950555253545956575863606162(<64 x i8> %x) {152; CHECK-LABEL: shuf_rot_v64i8_3012745611891015121314191617182320212227242526312829303532333439363738434041424744454651484950555253545956575863606162:153; CHECK: # %bb.0:154; CHECK-NEXT: vpaddb %zmm0, %zmm0, %zmm0155; CHECK-NEXT: vprold $8, %zmm0, %zmm0156; CHECK-NEXT: retq157 %x1 = add <64 x i8> %x, %x158 %r = shufflevector <64 x i8> %x1, <64 x i8> zeroinitializer, <64 x i32> <i32 3,i32 0,i32 1,i32 2,i32 7,i32 4,i32 5,i32 6,i32 11,i32 8,i32 9,i32 10,i32 15,i32 12,i32 13,i32 14,i32 19,i32 16,i32 17,i32 18,i32 23,i32 20,i32 21,i32 22,i32 27,i32 24,i32 25,i32 26,i32 31,i32 28,i32 29,i32 30,i32 35,i32 32,i32 33,i32 34,i32 39,i32 36,i32 37,i32 38,i32 43,i32 40,i32 41,i32 42,i32 47,i32 44,i32 45,i32 46,i32 51,i32 48,i32 49,i32 50,i32 55,i32 52,i32 53,i32 54,i32 59,i32 56,i32 57,i32 58,i32 63,i32 60,i32 61,i32 62>159 ret <64 x i8> %r160}161 162define <4 x i32> @shuf_shr_v4i32_1U3U(<4 x i32> %x) {163; CHECK-SKX-LABEL: shuf_shr_v4i32_1U3U:164; CHECK-SKX: # %bb.0:165; CHECK-SKX-NEXT: vpaddd %xmm0, %xmm0, %xmm0166; CHECK-SKX-NEXT: vpsrlq $32, %xmm0, %xmm0167; CHECK-SKX-NEXT: retq168;169; CHECK-ICX-LABEL: shuf_shr_v4i32_1U3U:170; CHECK-ICX: # %bb.0:171; CHECK-ICX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]172; CHECK-ICX-NEXT: vpaddd %xmm0, %xmm0, %xmm0173; CHECK-ICX-NEXT: retq174;175; CHECK-V4-LABEL: shuf_shr_v4i32_1U3U:176; CHECK-V4: # %bb.0:177; CHECK-V4-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]178; CHECK-V4-NEXT: vpaddd %xmm0, %xmm0, %xmm0179; CHECK-V4-NEXT: retq180;181; CHECK-ZNVER4-LABEL: shuf_shr_v4i32_1U3U:182; CHECK-ZNVER4: # %bb.0:183; CHECK-ZNVER4-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]184; CHECK-ZNVER4-NEXT: vpaddd %xmm0, %xmm0, %xmm0185; CHECK-ZNVER4-NEXT: retq186 %x1 = add <4 x i32> %x, %x187 %r = shufflevector <4 x i32> %x1, <4 x i32> zeroinitializer, <4 x i32> <i32 1, i32 undef, i32 3, i32 undef>188 ret <4 x i32> %r189}190 191define <8 x i32> @shuf_shr_v8i32_1U3U5U7U(<8 x i32> %x) {192; CHECK-SKX-LABEL: shuf_shr_v8i32_1U3U5U7U:193; CHECK-SKX: # %bb.0:194; CHECK-SKX-NEXT: vpaddd %ymm0, %ymm0, %ymm0195; CHECK-SKX-NEXT: vpsrlq $32, %ymm0, %ymm0196; CHECK-SKX-NEXT: retq197;198; CHECK-ICX-LABEL: shuf_shr_v8i32_1U3U5U7U:199; CHECK-ICX: # %bb.0:200; CHECK-ICX-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[1,1,3,3,5,5,7,7]201; CHECK-ICX-NEXT: vpaddd %ymm0, %ymm0, %ymm0202; CHECK-ICX-NEXT: retq203;204; CHECK-V4-LABEL: shuf_shr_v8i32_1U3U5U7U:205; CHECK-V4: # %bb.0:206; CHECK-V4-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[1,1,3,3,5,5,7,7]207; CHECK-V4-NEXT: vpaddd %ymm0, %ymm0, %ymm0208; CHECK-V4-NEXT: retq209;210; CHECK-ZNVER4-LABEL: shuf_shr_v8i32_1U3U5U7U:211; CHECK-ZNVER4: # %bb.0:212; CHECK-ZNVER4-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[1,1,3,3,5,5,7,7]213; CHECK-ZNVER4-NEXT: vpaddd %ymm0, %ymm0, %ymm0214; CHECK-ZNVER4-NEXT: retq215 %x1 = add <8 x i32> %x, %x216 %r = shufflevector <8 x i32> %x1, <8 x i32> zeroinitializer, <8 x i32> <i32 1, i32 undef, i32 3, i32 undef, i32 5, i32 undef, i32 7, i32 undef>217 ret <8 x i32> %r218}219 220define <16 x i32> @shuf_shr_v16i32_U3U5U7U9U11U13U15(<16 x i32> %x) {221; CHECK-SKX-LABEL: shuf_shr_v16i32_U3U5U7U9U11U13U15:222; CHECK-SKX: # %bb.0:223; CHECK-SKX-NEXT: vpaddd %zmm0, %zmm0, %zmm0224; CHECK-SKX-NEXT: vpsrlq $32, %zmm0, %zmm0225; CHECK-SKX-NEXT: retq226;227; CHECK-ICX-LABEL: shuf_shr_v16i32_U3U5U7U9U11U13U15:228; CHECK-ICX: # %bb.0:229; CHECK-ICX-NEXT: vpshufd {{.*#+}} zmm0 = zmm0[1,1,3,3,5,5,7,7,9,9,11,11,13,13,15,15]230; CHECK-ICX-NEXT: vpaddd %zmm0, %zmm0, %zmm0231; CHECK-ICX-NEXT: retq232;233; CHECK-V4-LABEL: shuf_shr_v16i32_U3U5U7U9U11U13U15:234; CHECK-V4: # %bb.0:235; CHECK-V4-NEXT: vpshufd {{.*#+}} zmm0 = zmm0[1,1,3,3,5,5,7,7,9,9,11,11,13,13,15,15]236; CHECK-V4-NEXT: vpaddd %zmm0, %zmm0, %zmm0237; CHECK-V4-NEXT: retq238;239; CHECK-ZNVER4-LABEL: shuf_shr_v16i32_U3U5U7U9U11U13U15:240; CHECK-ZNVER4: # %bb.0:241; CHECK-ZNVER4-NEXT: vpshufd {{.*#+}} zmm0 = zmm0[1,1,3,3,5,5,7,7,9,9,11,11,13,13,15,15]242; CHECK-ZNVER4-NEXT: vpaddd %zmm0, %zmm0, %zmm0243; CHECK-ZNVER4-NEXT: retq244 %x1 = add <16 x i32> %x, %x245 %r = shufflevector <16 x i32> %x1, <16 x i32> zeroinitializer, <16 x i32> <i32 1, i32 undef, i32 3, i32 undef, i32 5, i32 undef, i32 7, i32 undef, i32 9, i32 undef, i32 11, i32 undef, i32 13, i32 undef, i32 15, i32 undef>246 ret <16 x i32> %r247}248 249define <8 x i16> @shuf_shr_v8i16_123U567U(<8 x i16> %x) {250; CHECK-LABEL: shuf_shr_v8i16_123U567U:251; CHECK: # %bb.0:252; CHECK-NEXT: vpaddw %xmm0, %xmm0, %xmm0253; CHECK-NEXT: vpsrlq $16, %xmm0, %xmm0254; CHECK-NEXT: retq255 %x1 = add <8 x i16> %x, %x256 %r = shufflevector <8 x i16> %x1, <8 x i16> zeroinitializer, <8 x i32> <i32 1, i32 2, i32 3, i32 undef, i32 5, i32 6, i32 7, i32 undef>257 ret <8 x i16> %r258}259 260define <32 x i16> @shuf_shr_v32i16_1U3U5U7U9U11U13U15U17U19U21U23U25U27U29U31U(<32 x i16> %x) {261; CHECK-LABEL: shuf_shr_v32i16_1U3U5U7U9U11U13U15U17U19U21U23U25U27U29U31U:262; CHECK: # %bb.0:263; CHECK-NEXT: vpaddw %zmm0, %zmm0, %zmm0264; CHECK-NEXT: vpsrld $16, %zmm0, %zmm0265; CHECK-NEXT: retq266 %x1 = add <32 x i16> %x, %x267 %r = shufflevector <32 x i16> %x1, <32 x i16> zeroinitializer, <32 x i32> <i32 1, i32 undef, i32 3, i32 undef, i32 5, i32 undef, i32 7, i32 undef, i32 9, i32 undef, i32 11, i32 undef, i32 13, i32 undef, i32 15, i32 undef, i32 17, i32 undef, i32 19, i32 undef, i32 21, i32 undef, i32 23, i32 undef, i32 25, i32 undef, i32 27, i32 undef, i32 29, i32 undef, i32 31, i32 undef>268 ret <32 x i16> %r269}270 271define <32 x i8> @shuf_shr_v32i8_1U3U5U7U9U11U13U15U17U19U21U23U25U27U29U31U(<32 x i8> %x) {272; CHECK-LABEL: shuf_shr_v32i8_1U3U5U7U9U11U13U15U17U19U21U23U25U27U29U31U:273; CHECK: # %bb.0:274; CHECK-NEXT: vpaddb %ymm0, %ymm0, %ymm0275; CHECK-NEXT: vpsrlw $8, %ymm0, %ymm0276; CHECK-NEXT: retq277 %x1 = add <32 x i8> %x, %x278 %r = shufflevector <32 x i8> %x1, <32 x i8> zeroinitializer, <32 x i32> <i32 1, i32 undef, i32 3, i32 undef, i32 5, i32 undef, i32 7, i32 undef, i32 9, i32 undef, i32 11, i32 undef, i32 13, i32 undef, i32 15, i32 undef, i32 17, i32 undef, i32 19, i32 undef, i32 21, i32 undef, i32 23, i32 undef, i32 25, i32 undef, i32 27, i32 undef, i32 29, i32 undef, i32 31, i32 undef>279 ret <32 x i8> %r280}281 282define <4 x i32> @shuf_shl_v4i32_U0U2(<4 x i32> %x) {283; CHECK-SKX-LABEL: shuf_shl_v4i32_U0U2:284; CHECK-SKX: # %bb.0:285; CHECK-SKX-NEXT: vpaddd %xmm0, %xmm0, %xmm0286; CHECK-SKX-NEXT: vpsllq $32, %xmm0, %xmm0287; CHECK-SKX-NEXT: retq288;289; CHECK-ICX-LABEL: shuf_shl_v4i32_U0U2:290; CHECK-ICX: # %bb.0:291; CHECK-ICX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,2,2]292; CHECK-ICX-NEXT: vpaddd %xmm0, %xmm0, %xmm0293; CHECK-ICX-NEXT: retq294;295; CHECK-V4-LABEL: shuf_shl_v4i32_U0U2:296; CHECK-V4: # %bb.0:297; CHECK-V4-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,2,2]298; CHECK-V4-NEXT: vpaddd %xmm0, %xmm0, %xmm0299; CHECK-V4-NEXT: retq300;301; CHECK-ZNVER4-LABEL: shuf_shl_v4i32_U0U2:302; CHECK-ZNVER4: # %bb.0:303; CHECK-ZNVER4-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,2,2]304; CHECK-ZNVER4-NEXT: vpaddd %xmm0, %xmm0, %xmm0305; CHECK-ZNVER4-NEXT: retq306 %x1 = add <4 x i32> %x, %x307 %r = shufflevector <4 x i32> %x1, <4 x i32> zeroinitializer, <4 x i32> <i32 undef, i32 0, i32 undef, i32 2>308 ret <4 x i32> %r309}310 311define <8 x i32> @shuf_shl_v8i32_U0U2U4U6(<8 x i32> %x) {312; CHECK-SKX-LABEL: shuf_shl_v8i32_U0U2U4U6:313; CHECK-SKX: # %bb.0:314; CHECK-SKX-NEXT: vpaddd %ymm0, %ymm0, %ymm0315; CHECK-SKX-NEXT: vpsllq $32, %ymm0, %ymm0316; CHECK-SKX-NEXT: retq317;318; CHECK-ICX-LABEL: shuf_shl_v8i32_U0U2U4U6:319; CHECK-ICX: # %bb.0:320; CHECK-ICX-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,0,2,2,4,4,6,6]321; CHECK-ICX-NEXT: vpaddd %ymm0, %ymm0, %ymm0322; CHECK-ICX-NEXT: retq323;324; CHECK-V4-LABEL: shuf_shl_v8i32_U0U2U4U6:325; CHECK-V4: # %bb.0:326; CHECK-V4-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,0,2,2,4,4,6,6]327; CHECK-V4-NEXT: vpaddd %ymm0, %ymm0, %ymm0328; CHECK-V4-NEXT: retq329;330; CHECK-ZNVER4-LABEL: shuf_shl_v8i32_U0U2U4U6:331; CHECK-ZNVER4: # %bb.0:332; CHECK-ZNVER4-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,0,2,2,4,4,6,6]333; CHECK-ZNVER4-NEXT: vpaddd %ymm0, %ymm0, %ymm0334; CHECK-ZNVER4-NEXT: retq335 %x1 = add <8 x i32> %x, %x336 %r = shufflevector <8 x i32> %x1, <8 x i32> zeroinitializer, <8 x i32> <i32 undef, i32 0, i32 undef, i32 2, i32 undef, i32 4, i32 undef, i32 6>337 ret <8 x i32> %r338}339 340define <16 x i32> @shuf_shl_v16i32_U0U2U4U6U8U10U12U14(<16 x i32> %x) {341; CHECK-SKX-LABEL: shuf_shl_v16i32_U0U2U4U6U8U10U12U14:342; CHECK-SKX: # %bb.0:343; CHECK-SKX-NEXT: vpaddd %zmm0, %zmm0, %zmm0344; CHECK-SKX-NEXT: vpsllq $32, %zmm0, %zmm0345; CHECK-SKX-NEXT: retq346;347; CHECK-ICX-LABEL: shuf_shl_v16i32_U0U2U4U6U8U10U12U14:348; CHECK-ICX: # %bb.0:349; CHECK-ICX-NEXT: vpshufd {{.*#+}} zmm0 = zmm0[0,0,2,2,4,4,6,6,8,8,10,10,12,12,14,14]350; CHECK-ICX-NEXT: vpaddd %zmm0, %zmm0, %zmm0351; CHECK-ICX-NEXT: retq352;353; CHECK-V4-LABEL: shuf_shl_v16i32_U0U2U4U6U8U10U12U14:354; CHECK-V4: # %bb.0:355; CHECK-V4-NEXT: vpshufd {{.*#+}} zmm0 = zmm0[0,0,2,2,4,4,6,6,8,8,10,10,12,12,14,14]356; CHECK-V4-NEXT: vpaddd %zmm0, %zmm0, %zmm0357; CHECK-V4-NEXT: retq358;359; CHECK-ZNVER4-LABEL: shuf_shl_v16i32_U0U2U4U6U8U10U12U14:360; CHECK-ZNVER4: # %bb.0:361; CHECK-ZNVER4-NEXT: vpshufd {{.*#+}} zmm0 = zmm0[0,0,2,2,4,4,6,6,8,8,10,10,12,12,14,14]362; CHECK-ZNVER4-NEXT: vpaddd %zmm0, %zmm0, %zmm0363; CHECK-ZNVER4-NEXT: retq364 %x1 = add <16 x i32> %x, %x365 %r = shufflevector <16 x i32> %x1, <16 x i32> zeroinitializer, <16 x i32> <i32 undef, i32 0, i32 undef, i32 2, i32 undef, i32 4, i32 undef, i32 6, i32 undef, i32 8, i32 undef, i32 10, i32 undef, i32 12, i32 undef, i32 14>366 ret <16 x i32> %r367}368 369define <16 x i16> @shuf_shl_v16i16_U0U2U4U6U8U10U12U14(<16 x i16> %x) {370; CHECK-LABEL: shuf_shl_v16i16_U0U2U4U6U8U10U12U14:371; CHECK: # %bb.0:372; CHECK-NEXT: vpaddw %ymm0, %ymm0, %ymm0373; CHECK-NEXT: vpslld $16, %ymm0, %ymm0374; CHECK-NEXT: retq375 %x1 = add <16 x i16> %x, %x376 %r = shufflevector <16 x i16> %x1, <16 x i16> zeroinitializer, <16 x i32> <i32 undef, i32 0, i32 undef, i32 2, i32 undef, i32 4, i32 undef, i32 6, i32 undef, i32 8, i32 undef, i32 10, i32 undef, i32 12, i32 undef, i32 14>377 ret <16 x i16> %r378}379 380define <16 x i8> @shuf_shl_v16i8_U0U2U4U6U8U10U12U14(<16 x i8> %x) {381; CHECK-LABEL: shuf_shl_v16i8_U0U2U4U6U8U10U12U14:382; CHECK: # %bb.0:383; CHECK-NEXT: vpaddb %xmm0, %xmm0, %xmm0384; CHECK-NEXT: vpsllw $8, %xmm0, %xmm0385; CHECK-NEXT: retq386 %x1 = add <16 x i8> %x, %x387 %r = shufflevector <16 x i8> %x1, <16 x i8> zeroinitializer, <16 x i32> <i32 undef, i32 0, i32 undef, i32 2, i32 undef, i32 4, i32 undef, i32 6, i32 undef, i32 8, i32 undef, i32 10, i32 undef, i32 12, i32 undef, i32 14>388 ret <16 x i8> %r389}390 391define <64 x i8> @shuf_shl_v64i8_U0U2U4U6U8U10U12U14U16U18U20U22U24U26U28U30U32U34U36U38U40U42U44U46U48U50U52U54U56U58U60U62(<64 x i8> %x) {392; CHECK-LABEL: shuf_shl_v64i8_U0U2U4U6U8U10U12U14U16U18U20U22U24U26U28U30U32U34U36U38U40U42U44U46U48U50U52U54U56U58U60U62:393; CHECK: # %bb.0:394; CHECK-NEXT: vpaddb %zmm0, %zmm0, %zmm0395; CHECK-NEXT: vpsllw $8, %zmm0, %zmm0396; CHECK-NEXT: retq397 %x1 = add <64 x i8> %x, %x398 %r = shufflevector <64 x i8> %x1, <64 x i8> zeroinitializer, <64 x i32> <i32 undef, i32 0, i32 undef, i32 2, i32 undef, i32 4, i32 undef, i32 6, i32 undef, i32 8, i32 undef, i32 10, i32 undef, i32 12, i32 undef, i32 14, i32 undef, i32 16, i32 undef, i32 18, i32 undef, i32 20, i32 undef, i32 22, i32 undef, i32 24, i32 undef, i32 26, i32 undef, i32 28, i32 undef, i32 30, i32 undef, i32 32, i32 undef, i32 34, i32 undef, i32 36, i32 undef, i32 38, i32 undef, i32 40, i32 undef, i32 42, i32 undef, i32 44, i32 undef, i32 46, i32 undef, i32 48, i32 undef, i32 50, i32 undef, i32 52, i32 undef, i32 54, i32 undef, i32 56, i32 undef, i32 58, i32 undef, i32 60, i32 undef, i32 62>399 ret <64 x i8> %r400}401