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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx | FileCheck %s3 4; Make sure that we do not infinitely-loop combining shuffle vectors.5 6@test24_id5239 = dso_local local_unnamed_addr global i64 0, align 87define void @infiloop() {8; CHECK-LABEL: infiloop:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: pushq %rbp11; CHECK-NEXT: .cfi_def_cfa_offset 1612; CHECK-NEXT: .cfi_offset %rbp, -1613; CHECK-NEXT: movq %rsp, %rbp14; CHECK-NEXT: .cfi_def_cfa_register %rbp15; CHECK-NEXT: andq $-32, %rsp16; CHECK-NEXT: subq $64, %rsp17; CHECK-NEXT: movabsq $506097522914230528, %rax # imm = 0x70605040302010018; CHECK-NEXT: movq %rax, test24_id5239(%rip)19; CHECK-NEXT: vmovaps {{.*#+}} ymm0 = [4,1,6,7,6,7,2,3,6,7,4,5,6,7,2,3,6,7,2,3,2,3,2,3,4,5,4,5,2,3,0,1]20; CHECK-NEXT: vmovaps %ymm0, (%rsp)21; CHECK-NEXT: movq %rbp, %rsp22; CHECK-NEXT: popq %rbp23; CHECK-NEXT: .cfi_def_cfa %rsp, 824; CHECK-NEXT: vzeroupper25; CHECK-NEXT: retq26entry:27 %id5230 = alloca <32 x i8>, align 3228 store i8 0, ptr @test24_id5239, align 829 store i8 1, ptr getelementptr inbounds (i8, ptr @test24_id5239, i64 1), align 130 store i8 2, ptr getelementptr inbounds (i8, ptr @test24_id5239, i64 2), align 231 store i8 3, ptr getelementptr inbounds (i8, ptr @test24_id5239, i64 3), align 132 store i8 4, ptr getelementptr inbounds (i8, ptr @test24_id5239, i64 4), align 433 store i8 5, ptr getelementptr inbounds (i8, ptr @test24_id5239, i64 5), align 134 store i8 6, ptr getelementptr inbounds (i8, ptr @test24_id5239, i64 6), align 235 store i8 7, ptr getelementptr inbounds (i8, ptr @test24_id5239, i64 7), align 136 %0 = load <4 x i16>, ptr @test24_id5239, align 837 %shuffle = shufflevector <4 x i16> %0, <4 x i16> poison, <16 x i32> <i32 0, i32 3, i32 3, i32 1, i32 3, i32 2, i32 3, i32 1, i32 3, i32 1, i32 1, i32 1, i32 2, i32 2, i32 1, i32 0>38 %1 = bitcast <16 x i16> %shuffle to <32 x i8>39 %2 = or <32 x i8> %1, <i8 4, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>40 store volatile <32 x i8> %2, ptr %id5230, align 3241 ret void42}43