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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s3 4; If positive...5 6define i32 @zext_ifpos(i32 %x) {7; CHECK-LABEL: zext_ifpos:8; CHECK: # %bb.0:9; CHECK-NEXT: movl %edi, %eax10; CHECK-NEXT: notl %eax11; CHECK-NEXT: shrl $31, %eax12; CHECK-NEXT: retq13 %c = icmp sgt i32 %x, -114 %e = zext i1 %c to i3215 ret i32 %e16}17 18define i32 @add_zext_ifpos(i32 %x) {19; CHECK-LABEL: add_zext_ifpos:20; CHECK: # %bb.0:21; CHECK-NEXT: # kill: def $edi killed $edi def $rdi22; CHECK-NEXT: sarl $31, %edi23; CHECK-NEXT: leal 42(%rdi), %eax24; CHECK-NEXT: retq25 %c = icmp sgt i32 %x, -126 %e = zext i1 %c to i3227 %r = add i32 %e, 4128 ret i32 %r29}30 31define <4 x i32> @add_zext_ifpos_vec_splat(<4 x i32> %x) {32; CHECK-LABEL: add_zext_ifpos_vec_splat:33; CHECK: # %bb.0:34; CHECK-NEXT: pcmpeqd %xmm1, %xmm135; CHECK-NEXT: pcmpgtd %xmm1, %xmm036; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [42,42,42,42]37; CHECK-NEXT: psubd %xmm0, %xmm138; CHECK-NEXT: movdqa %xmm1, %xmm039; CHECK-NEXT: retq40 %c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>41 %e = zext <4 x i1> %c to <4 x i32>42 %r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>43 ret <4 x i32> %r44}45 46define <4 x i32> @add_zext_ifpos_vec_nonsplat(<4 x i32> %x) {47; CHECK-LABEL: add_zext_ifpos_vec_nonsplat:48; CHECK: # %bb.0:49; CHECK-NEXT: pcmpeqd %xmm1, %xmm150; CHECK-NEXT: pcmpgtd %xmm1, %xmm051; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [42,43,44,45]52; CHECK-NEXT: psubd %xmm0, %xmm153; CHECK-NEXT: movdqa %xmm1, %xmm054; CHECK-NEXT: retq55 %c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>56 %e = zext <4 x i1> %c to <4 x i32>57 %r = add <4 x i32> %e, <i32 42, i32 43, i32 44, i32 45>58 ret <4 x i32> %r59}60 61define i32 @sel_ifpos_tval_bigger(i32 %x) {62; CHECK-LABEL: sel_ifpos_tval_bigger:63; CHECK: # %bb.0:64; CHECK-NEXT: # kill: def $edi killed $edi def $rdi65; CHECK-NEXT: sarl $31, %edi66; CHECK-NEXT: leal 42(%rdi), %eax67; CHECK-NEXT: retq68 %c = icmp sgt i32 %x, -169 %r = select i1 %c, i32 42, i32 4170 ret i32 %r71}72 73define i32 @sext_ifpos(i32 %x) {74; CHECK-LABEL: sext_ifpos:75; CHECK: # %bb.0:76; CHECK-NEXT: movl %edi, %eax77; CHECK-NEXT: notl %eax78; CHECK-NEXT: sarl $31, %eax79; CHECK-NEXT: retq80 %c = icmp sgt i32 %x, -181 %e = sext i1 %c to i3282 ret i32 %e83}84 85define i32 @add_sext_ifpos(i32 %x) {86; CHECK-LABEL: add_sext_ifpos:87; CHECK: # %bb.0:88; CHECK-NEXT: # kill: def $edi killed $edi def $rdi89; CHECK-NEXT: shrl $31, %edi90; CHECK-NEXT: leal 41(%rdi), %eax91; CHECK-NEXT: retq92 %c = icmp sgt i32 %x, -193 %e = sext i1 %c to i3294 %r = add i32 %e, 4295 ret i32 %r96}97 98define <4 x i32> @add_sext_ifpos_vec_splat(<4 x i32> %x) {99; CHECK-LABEL: add_sext_ifpos_vec_splat:100; CHECK: # %bb.0:101; CHECK-NEXT: pcmpeqd %xmm1, %xmm1102; CHECK-NEXT: pcmpgtd %xmm1, %xmm0103; CHECK-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0104; CHECK-NEXT: retq105 %c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>106 %e = sext <4 x i1> %c to <4 x i32>107 %r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>108 ret <4 x i32> %r109}110 111define <4 x i32> @add_sext_ifpos_vec_nonsplat(<4 x i32> %x) {112; CHECK-LABEL: add_sext_ifpos_vec_nonsplat:113; CHECK: # %bb.0:114; CHECK-NEXT: pcmpeqd %xmm1, %xmm1115; CHECK-NEXT: pcmpgtd %xmm1, %xmm0116; CHECK-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0117; CHECK-NEXT: retq118 %c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>119 %e = sext <4 x i1> %c to <4 x i32>120 %r = add <4 x i32> %e, <i32 42, i32 43, i32 44, i32 45>121 ret <4 x i32> %r122}123 124define i32 @sel_ifpos_fval_bigger(i32 %x) {125; CHECK-LABEL: sel_ifpos_fval_bigger:126; CHECK: # %bb.0:127; CHECK-NEXT: # kill: def $edi killed $edi def $rdi128; CHECK-NEXT: shrl $31, %edi129; CHECK-NEXT: leal 41(%rdi), %eax130; CHECK-NEXT: retq131 %c = icmp sgt i32 %x, -1132 %r = select i1 %c, i32 41, i32 42133 ret i32 %r134}135 136; If negative...137 138define i32 @zext_ifneg(i32 %x) {139; CHECK-LABEL: zext_ifneg:140; CHECK: # %bb.0:141; CHECK-NEXT: movl %edi, %eax142; CHECK-NEXT: shrl $31, %eax143; CHECK-NEXT: retq144 %c = icmp slt i32 %x, 0145 %r = zext i1 %c to i32146 ret i32 %r147}148 149define i32 @add_zext_ifneg(i32 %x) {150; CHECK-LABEL: add_zext_ifneg:151; CHECK: # %bb.0:152; CHECK-NEXT: # kill: def $edi killed $edi def $rdi153; CHECK-NEXT: shrl $31, %edi154; CHECK-NEXT: leal 41(%rdi), %eax155; CHECK-NEXT: retq156 %c = icmp slt i32 %x, 0157 %e = zext i1 %c to i32158 %r = add i32 %e, 41159 ret i32 %r160}161 162define i32 @sel_ifneg_tval_bigger(i32 %x) {163; CHECK-LABEL: sel_ifneg_tval_bigger:164; CHECK: # %bb.0:165; CHECK-NEXT: # kill: def $edi killed $edi def $rdi166; CHECK-NEXT: shrl $31, %edi167; CHECK-NEXT: leal 41(%rdi), %eax168; CHECK-NEXT: retq169 %c = icmp slt i32 %x, 0170 %r = select i1 %c, i32 42, i32 41171 ret i32 %r172}173 174define i32 @sext_ifneg(i32 %x) {175; CHECK-LABEL: sext_ifneg:176; CHECK: # %bb.0:177; CHECK-NEXT: movl %edi, %eax178; CHECK-NEXT: sarl $31, %eax179; CHECK-NEXT: retq180 %c = icmp slt i32 %x, 0181 %r = sext i1 %c to i32182 ret i32 %r183}184 185define i32 @add_sext_ifneg(i32 %x) {186; CHECK-LABEL: add_sext_ifneg:187; CHECK: # %bb.0:188; CHECK-NEXT: # kill: def $edi killed $edi def $rdi189; CHECK-NEXT: sarl $31, %edi190; CHECK-NEXT: leal 42(%rdi), %eax191; CHECK-NEXT: retq192 %c = icmp slt i32 %x, 0193 %e = sext i1 %c to i32194 %r = add i32 %e, 42195 ret i32 %r196}197 198define i32 @sel_ifneg_fval_bigger(i32 %x) {199; CHECK-LABEL: sel_ifneg_fval_bigger:200; CHECK: # %bb.0:201; CHECK-NEXT: # kill: def $edi killed $edi def $rdi202; CHECK-NEXT: sarl $31, %edi203; CHECK-NEXT: leal 42(%rdi), %eax204; CHECK-NEXT: retq205 %c = icmp slt i32 %x, 0206 %r = select i1 %c, i32 41, i32 42207 ret i32 %r208}209 210define i32 @add_lshr_not(i32 %x) {211; CHECK-LABEL: add_lshr_not:212; CHECK: # %bb.0:213; CHECK-NEXT: # kill: def $edi killed $edi def $rdi214; CHECK-NEXT: sarl $31, %edi215; CHECK-NEXT: leal 42(%rdi), %eax216; CHECK-NEXT: retq217 %not = xor i32 %x, -1218 %sh = lshr i32 %not, 31219 %r = add i32 %sh, 41220 ret i32 %r221}222 223define <4 x i32> @add_lshr_not_vec_splat(<4 x i32> %x) {224; CHECK-LABEL: add_lshr_not_vec_splat:225; CHECK: # %bb.0:226; CHECK-NEXT: psrad $31, %xmm0227; CHECK-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0228; CHECK-NEXT: retq229 %c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>230 %e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>231 %r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>232 ret <4 x i32> %r233}234 235define <4 x i32> @add_lshr_not_vec_nonsplat(<4 x i32> %x) {236; CHECK-LABEL: add_lshr_not_vec_nonsplat:237; CHECK: # %bb.0:238; CHECK-NEXT: psrad $31, %xmm0239; CHECK-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0240; CHECK-NEXT: retq241 %c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>242 %e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>243 %r = add <4 x i32> %e, <i32 42, i32 43, i32 44, i32 45>244 ret <4 x i32> %r245}246 247define i32 @sub_lshr_not(i32 %x) {248; CHECK-LABEL: sub_lshr_not:249; CHECK: # %bb.0:250; CHECK-NEXT: # kill: def $edi killed $edi def $rdi251; CHECK-NEXT: shrl $31, %edi252; CHECK-NEXT: leal 42(%rdi), %eax253; CHECK-NEXT: retq254 %not = xor i32 %x, -1255 %sh = lshr i32 %not, 31256 %r = sub i32 43, %sh257 ret i32 %r258}259 260define <4 x i32> @sub_lshr_not_vec_splat(<4 x i32> %x) {261; CHECK-LABEL: sub_lshr_not_vec_splat:262; CHECK: # %bb.0:263; CHECK-NEXT: psrld $31, %xmm0264; CHECK-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0265; CHECK-NEXT: retq266 %c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>267 %e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>268 %r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %e269 ret <4 x i32> %r270}271 272define <4 x i32> @sub_lshr_not_vec_nonsplat(<4 x i32> %x) {273; CHECK-LABEL: sub_lshr_not_vec_nonsplat:274; CHECK: # %bb.0:275; CHECK-NEXT: psrld $31, %xmm0276; CHECK-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0277; CHECK-NEXT: retq278 %c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>279 %e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>280 %r = sub <4 x i32> <i32 42, i32 43, i32 44, i32 45>, %e281 ret <4 x i32> %r282}283 284define i32 @sub_lshr(i32 %x, i32 %y) {285; CHECK-LABEL: sub_lshr:286; CHECK: # %bb.0:287; CHECK-NEXT: # kill: def $esi killed $esi def $rsi288; CHECK-NEXT: # kill: def $edi killed $edi def $rdi289; CHECK-NEXT: sarl $31, %edi290; CHECK-NEXT: leal (%rdi,%rsi), %eax291; CHECK-NEXT: retq292 %sh = lshr i32 %x, 31293 %r = sub i32 %y, %sh294 ret i32 %r295}296 297define <4 x i32> @sub_lshr_vec(<4 x i32> %x, <4 x i32> %y) {298; CHECK-LABEL: sub_lshr_vec:299; CHECK: # %bb.0:300; CHECK-NEXT: psrad $31, %xmm0301; CHECK-NEXT: paddd %xmm1, %xmm0302; CHECK-NEXT: retq303 %sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>304 %r = sub <4 x i32> %y, %sh305 ret <4 x i32> %r306}307 308define i32 @sub_const_op_lshr(i32 %x) {309; CHECK-LABEL: sub_const_op_lshr:310; CHECK: # %bb.0:311; CHECK-NEXT: # kill: def $edi killed $edi def $rdi312; CHECK-NEXT: sarl $31, %edi313; CHECK-NEXT: leal 43(%rdi), %eax314; CHECK-NEXT: retq315 %sh = lshr i32 %x, 31316 %r = sub i32 43, %sh317 ret i32 %r318}319 320define <4 x i32> @sub_const_op_lshr_vec_splat(<4 x i32> %x) {321; CHECK-LABEL: sub_const_op_lshr_vec_splat:322; CHECK: # %bb.0:323; CHECK-NEXT: psrad $31, %xmm0324; CHECK-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0325; CHECK-NEXT: retq326 %sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>327 %r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %sh328 ret <4 x i32> %r329}330 331define <4 x i32> @sub_const_op_lshr_vec_nonsplat(<4 x i32> %x) {332; CHECK-LABEL: sub_const_op_lshr_vec_nonsplat:333; CHECK: # %bb.0:334; CHECK-NEXT: psrad $31, %xmm0335; CHECK-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0336; CHECK-NEXT: retq337 %sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>338 %r = sub <4 x i32> <i32 42, i32 43, i32 44, i32 45>, %sh339 ret <4 x i32> %r340}341 342