173 lines · plain
1; RUN: llc < %s -verify-machineinstrs -asm-verbose=false -mtriple=x86_64-unknown-linux-gnu -mcpu=nehalem -post-RA-scheduler=true -schedmodel=false | FileCheck %s2 3; Currently, floating-point selects are lowered to CFG triangles.4; This means that one side of the select is always unconditionally5; evaluated, however with MachineSink we can sink the other side so6; that it's conditionally evaluated.7 8; CHECK-LABEL: foo:9; CHECK-NEXT: testb $1, %dil10; CHECK-NEXT: jne11; CHECK-NEXT: divsd12; CHECK-NEXT: movapd13; CHECK-NEXT: ret14; CHECK: divsd15 16define double @foo(double %x, double %y, i1 %c) nounwind {17 %a = fdiv double %x, 3.218 %b = fdiv double %y, 3.319 %z = select i1 %c, double %a, double %b20 ret double %z21}22 23; Make sure the critical edge is broken so the divsd is sunken below24; the conditional branch.25; rdar://845488626 27; CHECK-LABEL: split:28; CHECK-NEXT: testb $1, %dil29; CHECK-NEXT: je30; CHECK: divsd31; CHECK: movapd32; CHECK: ret33define double @split(double %x, double %y, i1 %c) nounwind {34 %a = fdiv double %x, 3.235 %z = select i1 %c, double %a, double %y36 ret double %z37}38 39 40; Hoist floating-point constant-pool loads out of loops.41 42; CHECK-LABEL: bar:43; CHECK: movsd44; CHECK: align45define void @bar(ptr nocapture %p, i64 %n) nounwind {46entry:47 %0 = icmp sgt i64 %n, 048 br i1 %0, label %bb, label %return49 50bb:51 %i.03 = phi i64 [ 0, %entry ], [ %3, %bb ]52 %scevgep = getelementptr double, ptr %p, i64 %i.0353 %1 = load double, ptr %scevgep, align 854 %2 = fdiv double 3.200000e+00, %155 store double %2, ptr %scevgep, align 856 %3 = add nsw i64 %i.03, 157 %exitcond = icmp eq i64 %3, %n58 br i1 %exitcond, label %return, label %bb59 60return:61 ret void62}63 64; Sink instructions with dead EFLAGS defs.65 66; FIXME: Unfail the zzz test if we can correctly mark pregs with the kill flag.67;68; See <rdar://problem/8030636>. This test isn't valid after we made machine69; sinking more conservative about sinking instructions that define a preg into a70; block when we don't know if the preg is killed within the current block.71 72 73; FIXMEHECK: zzz:74; FIXMEHECK: je75; FIXMEHECK-NEXT: orb76 77; define zeroext i8 @zzz(i8 zeroext %a, i8 zeroext %b) nounwind readnone {78; entry:79; %tmp = zext i8 %a to i32 ; <i32> [#uses=1]80; %tmp2 = icmp eq i8 %a, 0 ; <i1> [#uses=1]81; %tmp3 = or i8 %b, -128 ; <i8> [#uses=1]82; %tmp4 = and i8 %b, 127 ; <i8> [#uses=1]83; %b_addr.0 = select i1 %tmp2, i8 %tmp4, i8 %tmp3 ; <i8> [#uses=1]84; ret i8 %b_addr.085; }86 87; Codegen should hoist and CSE these constants.88 89; CHECK-LABEL: vv:90; CHECK: LCPI3_0(%rip), %xmm091; CHECK: LCPI3_1(%rip), %xmm192; CHECK: LCPI3_2(%rip), %xmm293; CHECK: align94; CHECK-NOT: LCPI95; CHECK: ret96 97@_minusZero.6007 = internal constant <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00> ; <ptr> [#uses=0]98@twoTo23.6008 = internal constant <4 x float> <float 8.388608e+06, float 8.388608e+06, float 8.388608e+06, float 8.388608e+06> ; <ptr> [#uses=0]99 100define void @vv(ptr %y, ptr %x, ptr %n) nounwind ssp {101entry:102 br label %bb60103 104bb: ; preds = %bb60105 %i.0 = phi i32 [ 0, %bb60 ] ; <i32> [#uses=2]106 %0 = load <4 x float>, ptr %x_addr.0, align 16 ; <<4 x float>> [#uses=4]107 %tmp20 = bitcast <4 x float> %0 to <4 x i32> ; <<4 x i32>> [#uses=1]108 %tmp22 = and <4 x i32> %tmp20, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647> ; <<4 x i32>> [#uses=1]109 %tmp23 = bitcast <4 x i32> %tmp22 to <4 x float> ; <<4 x float>> [#uses=1]110 %tmp25 = bitcast <4 x float> %0 to <4 x i32> ; <<4 x i32>> [#uses=1]111 %tmp27 = and <4 x i32> %tmp25, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648> ; <<4 x i32>> [#uses=2]112 %tmp30 = call <4 x float> @llvm.x86.sse.cmp.ps(<4 x float> %tmp23, <4 x float> <float 8.388608e+06, float 8.388608e+06, float 8.388608e+06, float 8.388608e+06>, i8 5) ; <<4 x float>> [#uses=1]113 %tmp34 = bitcast <4 x float> %tmp30 to <4 x i32> ; <<4 x i32>> [#uses=1]114 %tmp36 = xor <4 x i32> %tmp34, <i32 -1, i32 -1, i32 -1, i32 -1> ; <<4 x i32>> [#uses=1]115 %tmp37 = and <4 x i32> %tmp36, <i32 1258291200, i32 1258291200, i32 1258291200, i32 1258291200> ; <<4 x i32>> [#uses=1]116 %tmp42 = or <4 x i32> %tmp37, %tmp27 ; <<4 x i32>> [#uses=1]117 %tmp43 = bitcast <4 x i32> %tmp42 to <4 x float> ; <<4 x float>> [#uses=2]118 %tmp45 = fadd <4 x float> %0, %tmp43 ; <<4 x float>> [#uses=1]119 %tmp47 = fsub <4 x float> %tmp45, %tmp43 ; <<4 x float>> [#uses=2]120 %tmp49 = call <4 x float> @llvm.x86.sse.cmp.ps(<4 x float> %0, <4 x float> %tmp47, i8 1) ; <<4 x float>> [#uses=1]121 %1 = bitcast <4 x float> %tmp49 to <4 x i32> ; <<4 x i32>> [#uses=1]122 %2 = call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %1) nounwind readnone ; <<4 x float>> [#uses=1]123 %tmp53 = fadd <4 x float> %tmp47, %2 ; <<4 x float>> [#uses=1]124 %tmp55 = bitcast <4 x float> %tmp53 to <4 x i32> ; <<4 x i32>> [#uses=1]125 %tmp57 = or <4 x i32> %tmp55, %tmp27 ; <<4 x i32>> [#uses=1]126 %tmp58 = bitcast <4 x i32> %tmp57 to <4 x float> ; <<4 x float>> [#uses=1]127 store <4 x float> %tmp58, ptr %y_addr.0, align 16128 %3 = getelementptr float, ptr %x_addr.0, i64 4 ; <ptr> [#uses=1]129 %4 = getelementptr float, ptr %y_addr.0, i64 4 ; <ptr> [#uses=1]130 %5 = add i32 %i.0, 4 ; <i32> [#uses=1]131 %6 = load i32, ptr %n, align 4 ; <i32> [#uses=1]132 %7 = icmp sgt i32 %6, %5 ; <i1> [#uses=1]133 br i1 %7, label %bb60, label %return134 135bb60: ; preds = %bb, %entry136 %x_addr.0 = phi ptr [ %x, %entry ], [ %3, %bb ] ; <ptr> [#uses=2]137 %y_addr.0 = phi ptr [ %y, %entry ], [ %4, %bb ] ; <ptr> [#uses=2]138 br label %bb139 140return: ; preds = %bb60141 ret void142}143 144declare <4 x float> @llvm.x86.sse.cmp.ps(<4 x float>, <4 x float>, i8) nounwind readnone145 146declare <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32>) nounwind readnone147 148; CodeGen should use the correct register class when extracting149; a load from a zero-extending load for hoisting.150 151; CHECK-LABEL: default_get_pch_validity:152; CHECK: movl cl_options_count(%rip), %ecx153 154@cl_options_count = external dso_local constant i32 ; <ptr> [#uses=2]155 156define void @default_get_pch_validity() nounwind {157entry:158 %tmp4 = load i32, ptr @cl_options_count, align 4 ; <i32> [#uses=1]159 %tmp5 = icmp eq i32 %tmp4, 0 ; <i1> [#uses=1]160 br i1 %tmp5, label %bb6, label %bb2161 162bb2: ; preds = %bb2, %entry163 %i.019 = phi i64 [ 0, %entry ], [ %tmp25, %bb2 ] ; <i64> [#uses=1]164 %tmp25 = add i64 %i.019, 1 ; <i64> [#uses=2]165 %tmp11 = load i32, ptr @cl_options_count, align 4 ; <i32> [#uses=1]166 %tmp12 = zext i32 %tmp11 to i64 ; <i64> [#uses=1]167 %tmp13 = icmp ugt i64 %tmp12, %tmp25 ; <i1> [#uses=1]168 br i1 %tmp13, label %bb2, label %bb6169 170bb6: ; preds = %bb2, %entry171 ret void172}173