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1; Intel chips with slow unaligned memory accesses2 3; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=pentium3 2>&1 | FileCheck %s --check-prefixes=SLOW,SLOW-SCALAR4; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=pentium3m 2>&1 | FileCheck %s --check-prefixes=SLOW,SLOW-SCALAR5; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=pentium-m 2>&1 | FileCheck %s --check-prefixes=SLOW,SLOW-SSE6; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=pentium4 2>&1 | FileCheck %s --check-prefixes=SLOW,SLOW-SSE7; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=pentium4m 2>&1 | FileCheck %s --check-prefixes=SLOW,SLOW-SSE8; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=yonah 2>&1 | FileCheck %s --check-prefixes=SLOW,SLOW-SSE9; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=prescott 2>&1 | FileCheck %s --check-prefixes=SLOW,SLOW-SSE10; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=nocona 2>&1 | FileCheck %s --check-prefixes=SLOW,SLOW-SSE11; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=core2 2>&1 | FileCheck %s --check-prefixes=SLOW,SLOW-SSE12; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=penryn 2>&1 | FileCheck %s --check-prefixes=SLOW,SLOW-SSE13; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=bonnell 2>&1 | FileCheck %s --check-prefixes=SLOW,SLOW-SSE14 15; Intel chips with fast unaligned memory accesses16 17; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=silvermont 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-SSE18; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=nehalem 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-SSE19; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=westmere 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-SSE20; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=sandybridge 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX12821; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=ivybridge 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX12822; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=haswell 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX25623; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=broadwell 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX25624; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=knl 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX51225; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=skylake-avx512 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX25626 27; AMD chips with slow unaligned memory accesses28 29; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=athlon-4 2>&1 | FileCheck %s --check-prefixes=SLOW,SLOW-SCALAR30; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=athlon-xp 2>&1 | FileCheck %s --check-prefixes=SLOW,SLOW-SCALAR31; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=k8 2>&1 | FileCheck %s --check-prefixes=SLOW,SLOW-SSE32; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=opteron 2>&1 | FileCheck %s --check-prefixes=SLOW,SLOW-SSE33; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=athlon64 2>&1 | FileCheck %s --check-prefixes=SLOW,SLOW-SSE34; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=athlon-fx 2>&1 | FileCheck %s --check-prefixes=SLOW,SLOW-SSE35; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=k8-sse3 2>&1 | FileCheck %s --check-prefixes=SLOW,SLOW-SSE36; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=opteron-sse3 2>&1 | FileCheck %s --check-prefixes=SLOW,SLOW-SSE37; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=athlon64-sse3 2>&1 | FileCheck %s --check-prefixes=SLOW,SLOW-SSE38 39; AMD chips with fast unaligned memory accesses40 41; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=amdfam10 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-SSE42; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=barcelona 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-SSE43; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=btver1 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-SSE44; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=btver2 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX25645; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=bdver1 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX25646; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=bdver2 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX25647; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=bdver3 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX25648; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=bdver4 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX25649; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=znver1 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX25650; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=znver2 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX25651; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=znver3 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX25652; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=znver4 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX51253; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=znver5 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX51254 55; Other chips with slow unaligned memory accesses56 57; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=c3-2 2>&1 | FileCheck %s --check-prefixes=SLOW58 59; Verify that the slow/fast unaligned memory attribute is set correctly for each CPU model.60; Slow chips use 4-byte stores. Fast chips with SSE or later use something other than 4-byte stores.61; Chips that don't have SSE use 4-byte stores either way, so they're not tested.62 63; Also verify that SSE4.2 or SSE4a imply fast unaligned accesses.64 65; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=sse4.2 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-SSE66; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=sse4a 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-SSE67 68; SLOW-NOT: not a recognized processor69; FAST-NOT: not a recognized processor70define void @store_zeros(ptr %a) {71; SLOW-SCALAR-LABEL: store_zeros:72; SLOW-SCALAR: # %bb.0:73; SLOW-SCALAR-NEXT: movl {{[0-9]+}}(%esp), %eax74; SLOW-SCALAR-NEXT: movl $075; SLOW-SCALAR-NEXT: movl $076; SLOW-SCALAR-NEXT: movl $077; SLOW-SCALAR-NEXT: movl $078; SLOW-SCALAR-NEXT: movl $079; SLOW-SCALAR-NEXT: movl $080; SLOW-SCALAR-NEXT: movl $081; SLOW-SCALAR-NEXT: movl $082; SLOW-SCALAR-NEXT: movl $083; SLOW-SCALAR-NEXT: movl $084; SLOW-SCALAR-NEXT: movl $085; SLOW-SCALAR-NEXT: movl $086; SLOW-SCALAR-NEXT: movl $087; SLOW-SCALAR-NEXT: movl $088; SLOW-SCALAR-NEXT: movl $089; SLOW-SCALAR-NEXT: movl $090; SLOW-SCALAR-NOT: movl91;92; SLOW-SSE-LABEL: store_zeros:93; SLOW-SSE: # %bb.0:94; SLOW-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax95; SLOW-SSE-NEXT: xorps %xmm0, %xmm096; SLOW-SSE-NEXT: movsd %xmm097; SLOW-SSE-NEXT: movsd %xmm098; SLOW-SSE-NEXT: movsd %xmm099; SLOW-SSE-NEXT: movsd %xmm0100; SLOW-SSE-NEXT: movsd %xmm0101; SLOW-SSE-NEXT: movsd %xmm0102; SLOW-SSE-NEXT: movsd %xmm0103; SLOW-SSE-NEXT: movsd %xmm0104; SLOW-SSE-NOT: movsd105;106; FAST-SSE-LABEL: store_zeros:107; FAST-SSE: # %bb.0:108; FAST-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax109; FAST-SSE-NEXT: xorps %xmm0, %xmm0110; FAST-SSE-NEXT: movups %xmm0111; FAST-SSE-NEXT: movups %xmm0112; FAST-SSE-NEXT: movups %xmm0113; FAST-SSE-NEXT: movups %xmm0114; FAST-SSE-NOT: movups115;116; FAST-AVX128-LABEL: store_zeros:117; FAST-AVX128: # %bb.0:118; FAST-AVX128-NEXT: movl {{[0-9]+}}(%esp), %eax119; FAST-AVX128-NEXT: vxorps %xmm0, %xmm0, %xmm0120; FAST-AVX128-NEXT: vmovups %xmm0121; FAST-AVX128-NEXT: vmovups %xmm0122; FAST-AVX128-NEXT: vmovups %xmm0123; FAST-AVX128-NEXT: vmovups %xmm0124; FAST-AVX128-NOT: vmovups125;126; FAST-AVX256-LABEL: store_zeros:127; FAST-AVX256: # %bb.0:128; FAST-AVX256-NEXT: movl {{[0-9]+}}(%esp), %eax129; FAST-AVX256-NEXT: vxorps %xmm0, %xmm0, %xmm0130; FAST-AVX256-NEXT: vmovups %ymm0131; FAST-AVX256-NEXT: vmovups %ymm0132; FAST-AVX256-NOT: vmovups133;134; FAST-AVX512-LABEL: store_zeros:135; FAST-AVX512: # %bb.0:136; FAST-AVX512-NEXT: movl {{[0-9]+}}(%esp), %eax137; FAST-AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0138; FAST-AVX512-NEXT: vmovups %zmm0, (%eax)139; FAST-AVX512-NOT: vmovups140 call void @llvm.memset.p0.i64(ptr %a, i8 0, i64 64, i1 false)141 ret void142}143 144declare void @llvm.memset.p0.i64(ptr nocapture, i8, i64, i1)145 146