60 lines · plain
1; RUN: llc < %s -mtriple=i686-- -mattr=+mmx,+sse,+soft-float \2; RUN: | FileCheck %s --check-prefix=SOFT1 --check-prefix=CHECK3; RUN: llc < %s -mtriple=x86_64-- -mattr=+mmx,+sse2,+soft-float \4; RUN: | FileCheck %s --check-prefix=SOFT2 --check-prefix=CHECK5; RUN: llc < %s -mtriple=x86_64-- -mattr=+mmx,+sse \6; RUN: | FileCheck %s --check-prefix=SSE1 --check-prefix=CHECK7; RUN: llc < %s -mtriple=x86_64-- -mattr=+mmx,+sse2 \8; RUN: | FileCheck %s --check-prefix=SSE2 --check-prefix=CHECK9; RUN: llc < %s -mtriple=x86_64-gnux32 -mattr=+mmx,+sse2,+soft-float | FileCheck %s10 11; CHECK-NOT: xmm{{[0-9]+}}12 13%struct.__va_list_tag = type { i32, i32, ptr, ptr }14 15define i32 @t1(i32 %a, ...) nounwind {16entry:17 %va = alloca [1 x %struct.__va_list_tag], align 8 ; <ptr> [#uses=2]18 call void @llvm.va_start(ptr %va)19 %va3 = getelementptr [1 x %struct.__va_list_tag], ptr %va, i64 0, i64 0 ; <ptr> [#uses=1]20 call void @bar(ptr %va3) nounwind21 call void @llvm.va_end(ptr %va)22 ret i32 undef23; CHECK-LABEL: t1:24; CHECK: ret{{[lq]}}25}26 27declare void @llvm.va_start(ptr) nounwind28 29declare void @bar(ptr)30 31declare void @llvm.va_end(ptr) nounwind32 33define float @t2(float %a, float %b) nounwind readnone {34entry:35 %0 = fadd float %a, %b ; <float> [#uses=1]36 ret float %037; CHECK-LABEL: t2:38; SOFT1-NOT: xmm{{[0-9]+}}39; SOFT2-NOT: xmm{{[0-9]+}}40; SSE1: xmm{{[0-9]+}}41; SSE2: xmm{{[0-9]+}}42; CHECK: ret{{[lq]}}43}44 45; soft-float means no SSE instruction and passing fp128 as pair of i64.46define fp128 @t3(fp128 %a, fp128 %b) nounwind readnone {47entry:48 %0 = fadd fp128 %b, %a49 ret fp128 %050; CHECK-LABEL: t3:51; SOFT1-NOT: xmm{{[0-9]+}}52; SOFT2-NOT: xmm{{[0-9]+}}53; SSE1: xmm{{[0-9]+}}54; SSE2: xmm{{[0-9]+}}55; SOFT1: ret{{[lq]}}56; SOFT2: ret{{[lq]}}57; SSE1: jmp __addtf358; SSE2: jmp __addtf359}60