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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=SSE3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX4 5; PR31455 - https://bugs.llvm.org/show_bug.cgi?id=314556; We have to assume that errno can be set, so we have to make a libcall in that case.7; But it's better for perf to check that the argument is valid rather than the result of8; sqrtss/sqrtsd.9; Note: This is really a test of the -partially-inline-libcalls IR pass (and we have an IR test10; for that), but we're checking the final asm to make sure that comes out as expected too.11 12define float @f(float %val) nounwind {13; SSE-LABEL: f:14; SSE: # %bb.0:15; SSE-NEXT: xorps %xmm1, %xmm116; SSE-NEXT: ucomiss %xmm1, %xmm017; SSE-NEXT: jb sqrtf # TAILCALL18; SSE-NEXT: # %bb.1: # %.split19; SSE-NEXT: sqrtss %xmm0, %xmm020; SSE-NEXT: retq21;22; AVX-LABEL: f:23; AVX: # %bb.0:24; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm125; AVX-NEXT: vucomiss %xmm1, %xmm026; AVX-NEXT: jb sqrtf # TAILCALL27; AVX-NEXT: # %bb.1: # %.split28; AVX-NEXT: vsqrtss %xmm0, %xmm0, %xmm029; AVX-NEXT: retq30 %res = tail call float @sqrtf(float %val)31 ret float %res32}33 34define double @d(double %val) nounwind {35; SSE-LABEL: d:36; SSE: # %bb.0:37; SSE-NEXT: xorpd %xmm1, %xmm138; SSE-NEXT: ucomisd %xmm1, %xmm039; SSE-NEXT: jb sqrt # TAILCALL40; SSE-NEXT: # %bb.1: # %.split41; SSE-NEXT: sqrtsd %xmm0, %xmm042; SSE-NEXT: retq43;44; AVX-LABEL: d:45; AVX: # %bb.0:46; AVX-NEXT: vxorpd %xmm1, %xmm1, %xmm147; AVX-NEXT: vucomisd %xmm1, %xmm048; AVX-NEXT: jb sqrt # TAILCALL49; AVX-NEXT: # %bb.1: # %.split50; AVX-NEXT: vsqrtsd %xmm0, %xmm0, %xmm051; AVX-NEXT: retq52 %res = tail call double @sqrt(double %val)53 ret double %res54}55 56define double @minsize(double %x, double %y) minsize {57; SSE-LABEL: minsize:58; SSE: # %bb.0:59; SSE-NEXT: mulsd %xmm0, %xmm060; SSE-NEXT: mulsd %xmm1, %xmm161; SSE-NEXT: addsd %xmm0, %xmm162; SSE-NEXT: sqrtsd %xmm1, %xmm063; SSE-NEXT: retq64;65; AVX-LABEL: minsize:66; AVX: # %bb.0:67; AVX-NEXT: vmulsd %xmm0, %xmm0, %xmm068; AVX-NEXT: vmulsd %xmm1, %xmm1, %xmm169; AVX-NEXT: vaddsd %xmm1, %xmm0, %xmm070; AVX-NEXT: vsqrtsd %xmm0, %xmm0, %xmm071; AVX-NEXT: retq72 %t3 = fmul fast double %x, %x73 %t4 = fmul fast double %y, %y74 %t5 = fadd fast double %t3, %t475 %t6 = tail call fast double @llvm.sqrt.f64(double %t5)76 ret double %t677}78 79; Partial reg avoidance may involve register allocation80; rather than adding an instruction.81 82define double @partial_dep_minsize(double %x, double %y) minsize {83; SSE-LABEL: partial_dep_minsize:84; SSE: # %bb.0:85; SSE-NEXT: sqrtsd %xmm1, %xmm086; SSE-NEXT: addsd %xmm1, %xmm087; SSE-NEXT: retq88;89; AVX-LABEL: partial_dep_minsize:90; AVX: # %bb.0:91; AVX-NEXT: vsqrtsd %xmm1, %xmm1, %xmm092; AVX-NEXT: vaddsd %xmm1, %xmm0, %xmm093; AVX-NEXT: retq94 %t6 = tail call fast double @llvm.sqrt.f64(double %y)95 %t = fadd fast double %t6, %y96 ret double %t97}98 99declare dso_local float @sqrtf(float)100declare dso_local double @sqrt(double)101declare dso_local double @llvm.sqrt.f64(double)102