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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX13; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX24; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512f | FileCheck %s --check-prefix=AVX --check-prefix=AVX512F5 6; 'signum' test cases (PR13248)7 8;9; generic implementation for 128-bit vectors10;11 12define void @signum32a(ptr) {13; AVX-LABEL: signum32a:14; AVX: # %bb.0: # %entry15; AVX-NEXT: vmovaps (%rdi), %xmm016; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm117; AVX-NEXT: vcmpltps %xmm1, %xmm0, %xmm218; AVX-NEXT: vcvtdq2ps %xmm2, %xmm219; AVX-NEXT: vcmpltps %xmm0, %xmm1, %xmm020; AVX-NEXT: vcvtdq2ps %xmm0, %xmm021; AVX-NEXT: vsubps %xmm0, %xmm2, %xmm022; AVX-NEXT: vmovaps %xmm0, (%rdi)23; AVX-NEXT: retq24entry:25 %1 = load <4 x float>, ptr %026 %2 = fcmp olt <4 x float> %1, zeroinitializer27 %3 = sitofp <4 x i1> %2 to <4 x float>28 %4 = fcmp ogt <4 x float> %1, zeroinitializer29 %5 = sitofp <4 x i1> %4 to <4 x float>30 %6 = fsub <4 x float> %3, %531 store <4 x float> %6, ptr %032 ret void33}34 35define void @signum64a(ptr) {36; AVX-LABEL: signum64a:37; AVX: # %bb.0: # %entry38; AVX-NEXT: vmovapd (%rdi), %xmm039; AVX-NEXT: vxorpd %xmm1, %xmm1, %xmm140; AVX-NEXT: vcmpltpd %xmm1, %xmm0, %xmm241; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm2[0,2,2,3]42; AVX-NEXT: vcvtdq2pd %xmm2, %xmm243; AVX-NEXT: vcmpltpd %xmm0, %xmm1, %xmm044; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2,2,3]45; AVX-NEXT: vcvtdq2pd %xmm0, %xmm046; AVX-NEXT: vsubpd %xmm0, %xmm2, %xmm047; AVX-NEXT: vmovapd %xmm0, (%rdi)48; AVX-NEXT: retq49entry:50 %1 = load <2 x double>, ptr %051 %2 = fcmp olt <2 x double> %1, zeroinitializer52 %3 = sitofp <2 x i1> %2 to <2 x double>53 %4 = fcmp ogt <2 x double> %1, zeroinitializer54 %5 = sitofp <2 x i1> %4 to <2 x double>55 %6 = fsub <2 x double> %3, %556 store <2 x double> %6, ptr %057 ret void58}59 60;61; generic implementation for 256-bit vectors62;63 64define void @signum32b(ptr) {65; AVX-LABEL: signum32b:66; AVX: # %bb.0: # %entry67; AVX-NEXT: vmovaps (%rdi), %ymm068; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm169; AVX-NEXT: vcmpltps %ymm1, %ymm0, %ymm270; AVX-NEXT: vcvtdq2ps %ymm2, %ymm271; AVX-NEXT: vcmpltps %ymm0, %ymm1, %ymm072; AVX-NEXT: vcvtdq2ps %ymm0, %ymm073; AVX-NEXT: vsubps %ymm0, %ymm2, %ymm074; AVX-NEXT: vmovaps %ymm0, (%rdi)75; AVX-NEXT: vzeroupper76; AVX-NEXT: retq77entry:78 %1 = load <8 x float>, ptr %079 %2 = fcmp olt <8 x float> %1, zeroinitializer80 %3 = sitofp <8 x i1> %2 to <8 x float>81 %4 = fcmp ogt <8 x float> %1, zeroinitializer82 %5 = sitofp <8 x i1> %4 to <8 x float>83 %6 = fsub <8 x float> %3, %584 store <8 x float> %6, ptr %085 ret void86}87 88define void @signum64b(ptr) {89; AVX1-LABEL: signum64b:90; AVX1: # %bb.0: # %entry91; AVX1-NEXT: vmovapd (%rdi), %ymm092; AVX1-NEXT: vxorpd %xmm1, %xmm1, %xmm193; AVX1-NEXT: vcmpltpd %ymm1, %ymm0, %ymm294; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm395; AVX1-NEXT: vpackssdw %xmm3, %xmm2, %xmm296; AVX1-NEXT: vcvtdq2pd %xmm2, %ymm297; AVX1-NEXT: vcmpltpd %ymm0, %ymm1, %ymm098; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm199; AVX1-NEXT: vpackssdw %xmm1, %xmm0, %xmm0100; AVX1-NEXT: vcvtdq2pd %xmm0, %ymm0101; AVX1-NEXT: vsubpd %ymm0, %ymm2, %ymm0102; AVX1-NEXT: vmovapd %ymm0, (%rdi)103; AVX1-NEXT: vzeroupper104; AVX1-NEXT: retq105;106; AVX2-LABEL: signum64b:107; AVX2: # %bb.0: # %entry108; AVX2-NEXT: vmovapd (%rdi), %ymm0109; AVX2-NEXT: vxorpd %xmm1, %xmm1, %xmm1110; AVX2-NEXT: vcmpltpd %ymm1, %ymm0, %ymm2111; AVX2-NEXT: vextractf128 $1, %ymm2, %xmm3112; AVX2-NEXT: vpackssdw %xmm3, %xmm2, %xmm2113; AVX2-NEXT: vcvtdq2pd %xmm2, %ymm2114; AVX2-NEXT: vcmpltpd %ymm0, %ymm1, %ymm0115; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm1116; AVX2-NEXT: vpackssdw %xmm1, %xmm0, %xmm0117; AVX2-NEXT: vcvtdq2pd %xmm0, %ymm0118; AVX2-NEXT: vsubpd %ymm0, %ymm2, %ymm0119; AVX2-NEXT: vmovapd %ymm0, (%rdi)120; AVX2-NEXT: vzeroupper121; AVX2-NEXT: retq122;123; AVX512F-LABEL: signum64b:124; AVX512F: # %bb.0: # %entry125; AVX512F-NEXT: vmovapd (%rdi), %ymm0126; AVX512F-NEXT: vxorpd %xmm1, %xmm1, %xmm1127; AVX512F-NEXT: vcmpltpd %ymm1, %ymm0, %ymm2128; AVX512F-NEXT: vpmovqd %zmm2, %ymm2129; AVX512F-NEXT: vcvtdq2pd %xmm2, %ymm2130; AVX512F-NEXT: vcmpltpd %ymm0, %ymm1, %ymm0131; AVX512F-NEXT: vpmovqd %zmm0, %ymm0132; AVX512F-NEXT: vcvtdq2pd %xmm0, %ymm0133; AVX512F-NEXT: vsubpd %ymm0, %ymm2, %ymm0134; AVX512F-NEXT: vmovapd %ymm0, (%rdi)135; AVX512F-NEXT: vzeroupper136; AVX512F-NEXT: retq137entry:138 %1 = load <4 x double>, ptr %0139 %2 = fcmp olt <4 x double> %1, zeroinitializer140 %3 = sitofp <4 x i1> %2 to <4 x double>141 %4 = fcmp ogt <4 x double> %1, zeroinitializer142 %5 = sitofp <4 x i1> %4 to <4 x double>143 %6 = fsub <4 x double> %3, %5144 store <4 x double> %6, ptr %0145 ret void146}147 148;149; implementation using AVX intrinsics for 256-bit vectors150;151 152define void @signum32c(ptr) {153; AVX-LABEL: signum32c:154; AVX: # %bb.0: # %entry155; AVX-NEXT: vmovaps (%rdi), %ymm0156; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1157; AVX-NEXT: vcmpltps %ymm1, %ymm0, %ymm2158; AVX-NEXT: vcvtdq2ps %ymm2, %ymm2159; AVX-NEXT: vcmpltps %ymm0, %ymm1, %ymm0160; AVX-NEXT: vcvtdq2ps %ymm0, %ymm0161; AVX-NEXT: vsubps %ymm0, %ymm2, %ymm0162; AVX-NEXT: vmovaps %ymm0, (%rdi)163; AVX-NEXT: vzeroupper164; AVX-NEXT: retq165entry:166 %1 = load <8 x float>, ptr %0167 %2 = tail call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %1, <8 x float> zeroinitializer, i8 1)168 %3 = bitcast <8 x float> %2 to <8 x i32>169 %4 = sitofp <8 x i32> %3 to <8 x float>170 %5 = tail call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> zeroinitializer, <8 x float> %1, i8 1)171 %6 = bitcast <8 x float> %5 to <8 x i32>172 %7 = sitofp <8 x i32> %6 to <8 x float>173 %8 = fsub <8 x float> %4, %7174 store <8 x float> %8, ptr %0175 ret void176}177 178define void @signum64c(ptr) {179; AVX1-LABEL: signum64c:180; AVX1: # %bb.0: # %entry181; AVX1-NEXT: vmovapd (%rdi), %ymm0182; AVX1-NEXT: vxorpd %xmm1, %xmm1, %xmm1183; AVX1-NEXT: vcmpltpd %ymm1, %ymm0, %ymm2184; AVX1-NEXT: vcmpltpd %ymm0, %ymm1, %ymm0185; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1186; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm3187; AVX1-NEXT: vpsubd %xmm1, %xmm3, %xmm1188; AVX1-NEXT: vpsubd %xmm0, %xmm2, %xmm0189; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]190; AVX1-NEXT: vcvtdq2pd %xmm0, %ymm0191; AVX1-NEXT: vmovaps %ymm0, (%rdi)192; AVX1-NEXT: vzeroupper193; AVX1-NEXT: retq194;195; AVX2-LABEL: signum64c:196; AVX2: # %bb.0: # %entry197; AVX2-NEXT: vmovapd (%rdi), %ymm0198; AVX2-NEXT: vxorpd %xmm1, %xmm1, %xmm1199; AVX2-NEXT: vcmpltpd %ymm1, %ymm0, %ymm2200; AVX2-NEXT: vcmpltpd %ymm0, %ymm1, %ymm0201; AVX2-NEXT: vpsubd %ymm0, %ymm2, %ymm0202; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1203; AVX2-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]204; AVX2-NEXT: vcvtdq2pd %xmm0, %ymm0205; AVX2-NEXT: vmovaps %ymm0, (%rdi)206; AVX2-NEXT: vzeroupper207; AVX2-NEXT: retq208;209; AVX512F-LABEL: signum64c:210; AVX512F: # %bb.0: # %entry211; AVX512F-NEXT: vmovapd (%rdi), %ymm0212; AVX512F-NEXT: vxorpd %xmm1, %xmm1, %xmm1213; AVX512F-NEXT: vcmpltpd %ymm1, %ymm0, %ymm2214; AVX512F-NEXT: vcmpltpd %ymm0, %ymm1, %ymm0215; AVX512F-NEXT: vpsubd %ymm0, %ymm2, %ymm0216; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm1217; AVX512F-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]218; AVX512F-NEXT: vcvtdq2pd %xmm0, %ymm0219; AVX512F-NEXT: vmovaps %ymm0, (%rdi)220; AVX512F-NEXT: vzeroupper221; AVX512F-NEXT: retq222entry:223 %x = load <4 x double>, ptr %0224 %xgt = tail call <4 x double> @llvm.x86.avx.cmp.pd.256(<4 x double> %x, <4 x double> zeroinitializer, i8 1)225 %igt = bitcast <4 x double> %xgt to <8 x i32>226 %xlt = tail call <4 x double> @llvm.x86.avx.cmp.pd.256(<4 x double> zeroinitializer, <4 x double> %x, i8 1)227 %ilt = bitcast <4 x double> %xlt to <8 x i32>228 ; it is important to use %igt twice as source in order to make LLVM use a shuffle operation229 %isign = sub <8 x i32> %igt, %ilt230 %ssign = shufflevector <8 x i32> %isign, <8 x i32> %isign, <4 x i32> <i32 0, i32 2, i32 12, i32 14>231 %sign = tail call <4 x double> @llvm.x86.avx.cvtdq2.pd.256(<4 x i32> %ssign)232 store <4 x double> %sign, ptr %0233 ret void234}235 236declare <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float>, <8 x float>, i8) nounwind readnone237 238declare <4 x double> @llvm.x86.avx.cmp.pd.256(<4 x double>, <4 x double>, i8) nounwind readnone239 240declare <4 x double> @llvm.x86.avx.cvtdq2.pd.256(<4 x i32>) nounwind readnone241