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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,SSE23; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,SSE414; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX5; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX6 7; 0'th element insertion into an SSE register.8 9define <4 x float> @insert_f32_firstelt(<4 x float> %x, float %s) {10; SSE-LABEL: insert_f32_firstelt:11; SSE: # %bb.0:12; SSE-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]13; SSE-NEXT: retq14;15; AVX-LABEL: insert_f32_firstelt:16; AVX: # %bb.0:17; AVX-NEXT: vmovss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]18; AVX-NEXT: retq19 %i0 = insertelement <4 x float> %x, float %s, i32 020 ret <4 x float> %i021}22 23define <2 x double> @insert_f64_firstelt(<2 x double> %x, double %s) {24; SSE-LABEL: insert_f64_firstelt:25; SSE: # %bb.0:26; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]27; SSE-NEXT: retq28;29; AVX-LABEL: insert_f64_firstelt:30; AVX: # %bb.0:31; AVX-NEXT: vmovsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]32; AVX-NEXT: retq33 %i0 = insertelement <2 x double> %x, double %s, i32 034 ret <2 x double> %i035}36 37define <16 x i8> @insert_i8_firstelt(<16 x i8> %x, i8 %s) {38; SSE2-LABEL: insert_i8_firstelt:39; SSE2: # %bb.0:40; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]41; SSE2-NEXT: pand %xmm1, %xmm042; SSE2-NEXT: movd %edi, %xmm243; SSE2-NEXT: pandn %xmm2, %xmm144; SSE2-NEXT: por %xmm1, %xmm045; SSE2-NEXT: retq46;47; SSE41-LABEL: insert_i8_firstelt:48; SSE41: # %bb.0:49; SSE41-NEXT: pinsrb $0, %edi, %xmm050; SSE41-NEXT: retq51;52; AVX-LABEL: insert_i8_firstelt:53; AVX: # %bb.0:54; AVX-NEXT: vpinsrb $0, %edi, %xmm0, %xmm055; AVX-NEXT: retq56 %i0 = insertelement <16 x i8> %x, i8 %s, i32 057 ret <16 x i8> %i058}59 60define <8 x i16> @insert_i16_firstelt(<8 x i16> %x, i16 %s) {61; SSE-LABEL: insert_i16_firstelt:62; SSE: # %bb.0:63; SSE-NEXT: pinsrw $0, %edi, %xmm064; SSE-NEXT: retq65;66; AVX-LABEL: insert_i16_firstelt:67; AVX: # %bb.0:68; AVX-NEXT: vpinsrw $0, %edi, %xmm0, %xmm069; AVX-NEXT: retq70 %i0 = insertelement <8 x i16> %x, i16 %s, i32 071 ret <8 x i16> %i072}73 74define <4 x i32> @insert_i32_firstelt(<4 x i32> %x, i32 %s) {75; SSE2-LABEL: insert_i32_firstelt:76; SSE2: # %bb.0:77; SSE2-NEXT: movd %edi, %xmm178; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]79; SSE2-NEXT: retq80;81; SSE41-LABEL: insert_i32_firstelt:82; SSE41: # %bb.0:83; SSE41-NEXT: pinsrd $0, %edi, %xmm084; SSE41-NEXT: retq85;86; AVX-LABEL: insert_i32_firstelt:87; AVX: # %bb.0:88; AVX-NEXT: vpinsrd $0, %edi, %xmm0, %xmm089; AVX-NEXT: retq90 %i0 = insertelement <4 x i32> %x, i32 %s, i32 091 ret <4 x i32> %i092}93 94define <2 x i64> @insert_i64_firstelt(<2 x i64> %x, i64 %s) {95; SSE2-LABEL: insert_i64_firstelt:96; SSE2: # %bb.0:97; SSE2-NEXT: movq %rdi, %xmm198; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]99; SSE2-NEXT: retq100;101; SSE41-LABEL: insert_i64_firstelt:102; SSE41: # %bb.0:103; SSE41-NEXT: pinsrq $0, %rdi, %xmm0104; SSE41-NEXT: retq105;106; AVX-LABEL: insert_i64_firstelt:107; AVX: # %bb.0:108; AVX-NEXT: vpinsrq $0, %rdi, %xmm0, %xmm0109; AVX-NEXT: retq110 %i0 = insertelement <2 x i64> %x, i64 %s, i32 0111 ret <2 x i64> %i0112}113 114; 1'th element insertion.115 116define <4 x float> @insert_f32_secondelt(<4 x float> %x, float %s) {117; SSE2-LABEL: insert_f32_secondelt:118; SSE2: # %bb.0:119; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]120; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]121; SSE2-NEXT: movaps %xmm1, %xmm0122; SSE2-NEXT: retq123;124; SSE41-LABEL: insert_f32_secondelt:125; SSE41: # %bb.0:126; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]127; SSE41-NEXT: retq128;129; AVX-LABEL: insert_f32_secondelt:130; AVX: # %bb.0:131; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]132; AVX-NEXT: retq133 %i0 = insertelement <4 x float> %x, float %s, i32 1134 ret <4 x float> %i0135}136 137define <2 x double> @insert_f64_secondelt(<2 x double> %x, double %s) {138; SSE-LABEL: insert_f64_secondelt:139; SSE: # %bb.0:140; SSE-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]141; SSE-NEXT: retq142;143; AVX-LABEL: insert_f64_secondelt:144; AVX: # %bb.0:145; AVX-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]146; AVX-NEXT: retq147 %i0 = insertelement <2 x double> %x, double %s, i32 1148 ret <2 x double> %i0149}150 151define <16 x i8> @insert_i8_secondelt(<16 x i8> %x, i8 %s) {152; SSE2-LABEL: insert_i8_secondelt:153; SSE2: # %bb.0:154; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255]155; SSE2-NEXT: pand %xmm1, %xmm0156; SSE2-NEXT: movd %edi, %xmm2157; SSE2-NEXT: psllw $8, %xmm2158; SSE2-NEXT: pandn %xmm2, %xmm1159; SSE2-NEXT: por %xmm1, %xmm0160; SSE2-NEXT: retq161;162; SSE41-LABEL: insert_i8_secondelt:163; SSE41: # %bb.0:164; SSE41-NEXT: pinsrb $1, %edi, %xmm0165; SSE41-NEXT: retq166;167; AVX-LABEL: insert_i8_secondelt:168; AVX: # %bb.0:169; AVX-NEXT: vpinsrb $1, %edi, %xmm0, %xmm0170; AVX-NEXT: retq171 %i0 = insertelement <16 x i8> %x, i8 %s, i32 1172 ret <16 x i8> %i0173}174 175define <8 x i16> @insert_i16_secondelt(<8 x i16> %x, i16 %s) {176; SSE-LABEL: insert_i16_secondelt:177; SSE: # %bb.0:178; SSE-NEXT: pinsrw $1, %edi, %xmm0179; SSE-NEXT: retq180;181; AVX-LABEL: insert_i16_secondelt:182; AVX: # %bb.0:183; AVX-NEXT: vpinsrw $1, %edi, %xmm0, %xmm0184; AVX-NEXT: retq185 %i0 = insertelement <8 x i16> %x, i16 %s, i32 1186 ret <8 x i16> %i0187}188 189define <4 x i32> @insert_i32_secondelt(<4 x i32> %x, i32 %s) {190; SSE2-LABEL: insert_i32_secondelt:191; SSE2: # %bb.0:192; SSE2-NEXT: movd %edi, %xmm1193; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]194; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]195; SSE2-NEXT: movaps %xmm1, %xmm0196; SSE2-NEXT: retq197;198; SSE41-LABEL: insert_i32_secondelt:199; SSE41: # %bb.0:200; SSE41-NEXT: pinsrd $1, %edi, %xmm0201; SSE41-NEXT: retq202;203; AVX-LABEL: insert_i32_secondelt:204; AVX: # %bb.0:205; AVX-NEXT: vpinsrd $1, %edi, %xmm0, %xmm0206; AVX-NEXT: retq207 %i0 = insertelement <4 x i32> %x, i32 %s, i32 1208 ret <4 x i32> %i0209}210 211define <2 x i64> @insert_i64_secondelt(<2 x i64> %x, i64 %s) {212; SSE2-LABEL: insert_i64_secondelt:213; SSE2: # %bb.0:214; SSE2-NEXT: movq %rdi, %xmm1215; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]216; SSE2-NEXT: retq217;218; SSE41-LABEL: insert_i64_secondelt:219; SSE41: # %bb.0:220; SSE41-NEXT: pinsrq $1, %rdi, %xmm0221; SSE41-NEXT: retq222;223; AVX-LABEL: insert_i64_secondelt:224; AVX: # %bb.0:225; AVX-NEXT: vpinsrq $1, %rdi, %xmm0, %xmm0226; AVX-NEXT: retq227 %i0 = insertelement <2 x i64> %x, i64 %s, i32 1228 ret <2 x i64> %i0229}230 231; element insertion into two elements232 233define <4 x float> @insert_f32_two_elts(<4 x float> %x, float %s) {234; SSE-LABEL: insert_f32_two_elts:235; SSE: # %bb.0:236; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,3]237; SSE-NEXT: movaps %xmm1, %xmm0238; SSE-NEXT: retq239;240; AVX-LABEL: insert_f32_two_elts:241; AVX: # %bb.0:242; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,0],xmm0[2,3]243; AVX-NEXT: retq244 %i0 = insertelement <4 x float> %x, float %s, i32 0245 %i1 = insertelement <4 x float> %i0, float %s, i32 1246 ret <4 x float> %i1247}248 249define <2 x double> @insert_f64_two_elts(<2 x double> %x, double %s) {250; SSE2-LABEL: insert_f64_two_elts:251; SSE2: # %bb.0:252; SSE2-NEXT: movaps %xmm1, %xmm0253; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]254; SSE2-NEXT: retq255;256; SSE41-LABEL: insert_f64_two_elts:257; SSE41: # %bb.0:258; SSE41-NEXT: movddup {{.*#+}} xmm0 = xmm1[0,0]259; SSE41-NEXT: retq260;261; AVX-LABEL: insert_f64_two_elts:262; AVX: # %bb.0:263; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm1[0,0]264; AVX-NEXT: retq265 %i0 = insertelement <2 x double> %x, double %s, i32 0266 %i1 = insertelement <2 x double> %i0, double %s, i32 1267 ret <2 x double> %i1268}269 270define <16 x i8> @insert_i8_two_elts(<16 x i8> %x, i8 %s) {271; SSE2-LABEL: insert_i8_two_elts:272; SSE2: # %bb.0:273; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]274; SSE2-NEXT: pand %xmm1, %xmm0275; SSE2-NEXT: movd %edi, %xmm2276; SSE2-NEXT: pandn %xmm2, %xmm1277; SSE2-NEXT: por %xmm1, %xmm0278; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255]279; SSE2-NEXT: pand %xmm1, %xmm0280; SSE2-NEXT: psllw $8, %xmm2281; SSE2-NEXT: pandn %xmm2, %xmm1282; SSE2-NEXT: por %xmm1, %xmm0283; SSE2-NEXT: retq284;285; SSE41-LABEL: insert_i8_two_elts:286; SSE41: # %bb.0:287; SSE41-NEXT: pinsrb $0, %edi, %xmm0288; SSE41-NEXT: pinsrb $1, %edi, %xmm0289; SSE41-NEXT: retq290;291; AVX-LABEL: insert_i8_two_elts:292; AVX: # %bb.0:293; AVX-NEXT: vpinsrb $0, %edi, %xmm0, %xmm0294; AVX-NEXT: vpinsrb $1, %edi, %xmm0, %xmm0295; AVX-NEXT: retq296 %i0 = insertelement <16 x i8> %x, i8 %s, i32 0297 %i1 = insertelement <16 x i8> %i0, i8 %s, i32 1298 ret <16 x i8> %i1299}300 301define <8 x i16> @insert_i16_two_elts(<8 x i16> %x, i16 %s) {302; SSE-LABEL: insert_i16_two_elts:303; SSE: # %bb.0:304; SSE-NEXT: pinsrw $0, %edi, %xmm0305; SSE-NEXT: pinsrw $1, %edi, %xmm0306; SSE-NEXT: retq307;308; AVX-LABEL: insert_i16_two_elts:309; AVX: # %bb.0:310; AVX-NEXT: vpinsrw $0, %edi, %xmm0, %xmm0311; AVX-NEXT: vpinsrw $1, %edi, %xmm0, %xmm0312; AVX-NEXT: retq313 %i0 = insertelement <8 x i16> %x, i16 %s, i32 0314 %i1 = insertelement <8 x i16> %i0, i16 %s, i32 1315 ret <8 x i16> %i1316}317 318define <4 x i32> @insert_i32_two_elts(<4 x i32> %x, i32 %s) {319; SSE2-LABEL: insert_i32_two_elts:320; SSE2: # %bb.0:321; SSE2-NEXT: movd %edi, %xmm2322; SSE2-NEXT: movd %edi, %xmm1323; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]324; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]325; SSE2-NEXT: movaps %xmm1, %xmm0326; SSE2-NEXT: retq327;328; SSE41-LABEL: insert_i32_two_elts:329; SSE41: # %bb.0:330; SSE41-NEXT: pinsrd $0, %edi, %xmm0331; SSE41-NEXT: pinsrd $1, %edi, %xmm0332; SSE41-NEXT: retq333;334; AVX-LABEL: insert_i32_two_elts:335; AVX: # %bb.0:336; AVX-NEXT: vpinsrd $0, %edi, %xmm0, %xmm0337; AVX-NEXT: vpinsrd $1, %edi, %xmm0, %xmm0338; AVX-NEXT: retq339 %i0 = insertelement <4 x i32> %x, i32 %s, i32 0340 %i1 = insertelement <4 x i32> %i0, i32 %s, i32 1341 ret <4 x i32> %i1342}343 344define <2 x i64> @insert_i64_two_elts(<2 x i64> %x, i64 %s) {345; SSE-LABEL: insert_i64_two_elts:346; SSE: # %bb.0:347; SSE-NEXT: movq %rdi, %xmm0348; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]349; SSE-NEXT: retq350 %i0 = insertelement <2 x i64> %x, i64 %s, i32 0351 %i1 = insertelement <2 x i64> %i0, i64 %s, i32 1352 ret <2 x i64> %i1353}354