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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,X86-SSE3; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,X86-SSE4; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX,X86-AVX,X86-AVX15; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=AVX,X86-AVX,X86-AVX5126; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,X64-SSE7; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,X64-SSE8; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX,X64-AVX,X64-AVX19; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=AVX,X64-AVX,X64-AVX51210 11; Ensure that the backend no longer emits unnecessary vector insert12; instructions immediately after SSE scalar fp instructions13; like addss or mulss.14 15define <4 x float> @test_add_ss(<4 x float> %a, <4 x float> %b) {16; SSE-LABEL: test_add_ss:17; SSE: # %bb.0:18; SSE-NEXT: addss %xmm1, %xmm019; SSE-NEXT: ret{{[l|q]}}20;21; AVX-LABEL: test_add_ss:22; AVX: # %bb.0:23; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm024; AVX-NEXT: ret{{[l|q]}}25 %1 = extractelement <4 x float> %b, i32 026 %2 = extractelement <4 x float> %a, i32 027 %add = fadd float %2, %128 %3 = insertelement <4 x float> %a, float %add, i32 029 ret <4 x float> %330}31 32define <4 x float> @test_sub_ss(<4 x float> %a, <4 x float> %b) {33; SSE-LABEL: test_sub_ss:34; SSE: # %bb.0:35; SSE-NEXT: subss %xmm1, %xmm036; SSE-NEXT: ret{{[l|q]}}37;38; AVX-LABEL: test_sub_ss:39; AVX: # %bb.0:40; AVX-NEXT: vsubss %xmm1, %xmm0, %xmm041; AVX-NEXT: ret{{[l|q]}}42 %1 = extractelement <4 x float> %b, i32 043 %2 = extractelement <4 x float> %a, i32 044 %sub = fsub float %2, %145 %3 = insertelement <4 x float> %a, float %sub, i32 046 ret <4 x float> %347}48 49define <4 x float> @test_mul_ss(<4 x float> %a, <4 x float> %b) {50; SSE-LABEL: test_mul_ss:51; SSE: # %bb.0:52; SSE-NEXT: mulss %xmm1, %xmm053; SSE-NEXT: ret{{[l|q]}}54;55; AVX-LABEL: test_mul_ss:56; AVX: # %bb.0:57; AVX-NEXT: vmulss %xmm1, %xmm0, %xmm058; AVX-NEXT: ret{{[l|q]}}59 %1 = extractelement <4 x float> %b, i32 060 %2 = extractelement <4 x float> %a, i32 061 %mul = fmul float %2, %162 %3 = insertelement <4 x float> %a, float %mul, i32 063 ret <4 x float> %364}65 66define <4 x float> @test_div_ss(<4 x float> %a, <4 x float> %b) {67; SSE-LABEL: test_div_ss:68; SSE: # %bb.0:69; SSE-NEXT: divss %xmm1, %xmm070; SSE-NEXT: ret{{[l|q]}}71;72; AVX-LABEL: test_div_ss:73; AVX: # %bb.0:74; AVX-NEXT: vdivss %xmm1, %xmm0, %xmm075; AVX-NEXT: ret{{[l|q]}}76 %1 = extractelement <4 x float> %b, i32 077 %2 = extractelement <4 x float> %a, i32 078 %div = fdiv float %2, %179 %3 = insertelement <4 x float> %a, float %div, i32 080 ret <4 x float> %381}82 83define <4 x float> @test_sqrt_ss(<4 x float> %a) {84; SSE-LABEL: test_sqrt_ss:85; SSE: # %bb.0:86; SSE-NEXT: sqrtss %xmm0, %xmm087; SSE-NEXT: ret{{[l|q]}}88;89; AVX-LABEL: test_sqrt_ss:90; AVX: # %bb.0:91; AVX-NEXT: vsqrtss %xmm0, %xmm0, %xmm092; AVX-NEXT: ret{{[l|q]}}93 %1 = extractelement <4 x float> %a, i32 094 %2 = call float @llvm.sqrt.f32(float %1)95 %3 = insertelement <4 x float> %a, float %2, i32 096 ret <4 x float> %397}98declare float @llvm.sqrt.f32(float)99 100define <2 x double> @test_add_sd(<2 x double> %a, <2 x double> %b) {101; SSE-LABEL: test_add_sd:102; SSE: # %bb.0:103; SSE-NEXT: addsd %xmm1, %xmm0104; SSE-NEXT: ret{{[l|q]}}105;106; AVX-LABEL: test_add_sd:107; AVX: # %bb.0:108; AVX-NEXT: vaddsd %xmm1, %xmm0, %xmm0109; AVX-NEXT: ret{{[l|q]}}110 %1 = extractelement <2 x double> %b, i32 0111 %2 = extractelement <2 x double> %a, i32 0112 %add = fadd double %2, %1113 %3 = insertelement <2 x double> %a, double %add, i32 0114 ret <2 x double> %3115}116 117define <2 x double> @test_sub_sd(<2 x double> %a, <2 x double> %b) {118; SSE-LABEL: test_sub_sd:119; SSE: # %bb.0:120; SSE-NEXT: subsd %xmm1, %xmm0121; SSE-NEXT: ret{{[l|q]}}122;123; AVX-LABEL: test_sub_sd:124; AVX: # %bb.0:125; AVX-NEXT: vsubsd %xmm1, %xmm0, %xmm0126; AVX-NEXT: ret{{[l|q]}}127 %1 = extractelement <2 x double> %b, i32 0128 %2 = extractelement <2 x double> %a, i32 0129 %sub = fsub double %2, %1130 %3 = insertelement <2 x double> %a, double %sub, i32 0131 ret <2 x double> %3132}133 134define <2 x double> @test_mul_sd(<2 x double> %a, <2 x double> %b) {135; SSE-LABEL: test_mul_sd:136; SSE: # %bb.0:137; SSE-NEXT: mulsd %xmm1, %xmm0138; SSE-NEXT: ret{{[l|q]}}139;140; AVX-LABEL: test_mul_sd:141; AVX: # %bb.0:142; AVX-NEXT: vmulsd %xmm1, %xmm0, %xmm0143; AVX-NEXT: ret{{[l|q]}}144 %1 = extractelement <2 x double> %b, i32 0145 %2 = extractelement <2 x double> %a, i32 0146 %mul = fmul double %2, %1147 %3 = insertelement <2 x double> %a, double %mul, i32 0148 ret <2 x double> %3149}150 151define <2 x double> @test_div_sd(<2 x double> %a, <2 x double> %b) {152; SSE-LABEL: test_div_sd:153; SSE: # %bb.0:154; SSE-NEXT: divsd %xmm1, %xmm0155; SSE-NEXT: ret{{[l|q]}}156;157; AVX-LABEL: test_div_sd:158; AVX: # %bb.0:159; AVX-NEXT: vdivsd %xmm1, %xmm0, %xmm0160; AVX-NEXT: ret{{[l|q]}}161 %1 = extractelement <2 x double> %b, i32 0162 %2 = extractelement <2 x double> %a, i32 0163 %div = fdiv double %2, %1164 %3 = insertelement <2 x double> %a, double %div, i32 0165 ret <2 x double> %3166}167 168define <2 x double> @test_sqrt_sd(<2 x double> %a) {169; SSE-LABEL: test_sqrt_sd:170; SSE: # %bb.0:171; SSE-NEXT: sqrtsd %xmm0, %xmm0172; SSE-NEXT: ret{{[l|q]}}173;174; AVX-LABEL: test_sqrt_sd:175; AVX: # %bb.0:176; AVX-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0177; AVX-NEXT: ret{{[l|q]}}178 %1 = extractelement <2 x double> %a, i32 0179 %2 = call double @llvm.sqrt.f64(double %1)180 %3 = insertelement <2 x double> %a, double %2, i32 0181 ret <2 x double> %3182}183declare double @llvm.sqrt.f64(double)184 185define <4 x float> @test2_add_ss(<4 x float> %a, <4 x float> %b) {186; SSE-LABEL: test2_add_ss:187; SSE: # %bb.0:188; SSE-NEXT: addss %xmm0, %xmm1189; SSE-NEXT: movaps %xmm1, %xmm0190; SSE-NEXT: ret{{[l|q]}}191;192; AVX-LABEL: test2_add_ss:193; AVX: # %bb.0:194; AVX-NEXT: vaddss %xmm0, %xmm1, %xmm0195; AVX-NEXT: ret{{[l|q]}}196 %1 = extractelement <4 x float> %a, i32 0197 %2 = extractelement <4 x float> %b, i32 0198 %add = fadd float %1, %2199 %3 = insertelement <4 x float> %b, float %add, i32 0200 ret <4 x float> %3201}202 203define <4 x float> @test2_sub_ss(<4 x float> %a, <4 x float> %b) {204; SSE-LABEL: test2_sub_ss:205; SSE: # %bb.0:206; SSE-NEXT: subss %xmm0, %xmm1207; SSE-NEXT: movaps %xmm1, %xmm0208; SSE-NEXT: ret{{[l|q]}}209;210; AVX-LABEL: test2_sub_ss:211; AVX: # %bb.0:212; AVX-NEXT: vsubss %xmm0, %xmm1, %xmm0213; AVX-NEXT: ret{{[l|q]}}214 %1 = extractelement <4 x float> %a, i32 0215 %2 = extractelement <4 x float> %b, i32 0216 %sub = fsub float %2, %1217 %3 = insertelement <4 x float> %b, float %sub, i32 0218 ret <4 x float> %3219}220 221define <4 x float> @test2_mul_ss(<4 x float> %a, <4 x float> %b) {222; SSE-LABEL: test2_mul_ss:223; SSE: # %bb.0:224; SSE-NEXT: mulss %xmm0, %xmm1225; SSE-NEXT: movaps %xmm1, %xmm0226; SSE-NEXT: ret{{[l|q]}}227;228; AVX-LABEL: test2_mul_ss:229; AVX: # %bb.0:230; AVX-NEXT: vmulss %xmm0, %xmm1, %xmm0231; AVX-NEXT: ret{{[l|q]}}232 %1 = extractelement <4 x float> %a, i32 0233 %2 = extractelement <4 x float> %b, i32 0234 %mul = fmul float %1, %2235 %3 = insertelement <4 x float> %b, float %mul, i32 0236 ret <4 x float> %3237}238 239define <4 x float> @test2_div_ss(<4 x float> %a, <4 x float> %b) {240; SSE-LABEL: test2_div_ss:241; SSE: # %bb.0:242; SSE-NEXT: divss %xmm0, %xmm1243; SSE-NEXT: movaps %xmm1, %xmm0244; SSE-NEXT: ret{{[l|q]}}245;246; AVX-LABEL: test2_div_ss:247; AVX: # %bb.0:248; AVX-NEXT: vdivss %xmm0, %xmm1, %xmm0249; AVX-NEXT: ret{{[l|q]}}250 %1 = extractelement <4 x float> %a, i32 0251 %2 = extractelement <4 x float> %b, i32 0252 %div = fdiv float %2, %1253 %3 = insertelement <4 x float> %b, float %div, i32 0254 ret <4 x float> %3255}256 257define <2 x double> @test2_add_sd(<2 x double> %a, <2 x double> %b) {258; SSE-LABEL: test2_add_sd:259; SSE: # %bb.0:260; SSE-NEXT: addsd %xmm0, %xmm1261; SSE-NEXT: movapd %xmm1, %xmm0262; SSE-NEXT: ret{{[l|q]}}263;264; AVX-LABEL: test2_add_sd:265; AVX: # %bb.0:266; AVX-NEXT: vaddsd %xmm0, %xmm1, %xmm0267; AVX-NEXT: ret{{[l|q]}}268 %1 = extractelement <2 x double> %a, i32 0269 %2 = extractelement <2 x double> %b, i32 0270 %add = fadd double %1, %2271 %3 = insertelement <2 x double> %b, double %add, i32 0272 ret <2 x double> %3273}274 275define <2 x double> @test2_sub_sd(<2 x double> %a, <2 x double> %b) {276; SSE-LABEL: test2_sub_sd:277; SSE: # %bb.0:278; SSE-NEXT: subsd %xmm0, %xmm1279; SSE-NEXT: movapd %xmm1, %xmm0280; SSE-NEXT: ret{{[l|q]}}281;282; AVX-LABEL: test2_sub_sd:283; AVX: # %bb.0:284; AVX-NEXT: vsubsd %xmm0, %xmm1, %xmm0285; AVX-NEXT: ret{{[l|q]}}286 %1 = extractelement <2 x double> %a, i32 0287 %2 = extractelement <2 x double> %b, i32 0288 %sub = fsub double %2, %1289 %3 = insertelement <2 x double> %b, double %sub, i32 0290 ret <2 x double> %3291}292 293define <2 x double> @test2_mul_sd(<2 x double> %a, <2 x double> %b) {294; SSE-LABEL: test2_mul_sd:295; SSE: # %bb.0:296; SSE-NEXT: mulsd %xmm0, %xmm1297; SSE-NEXT: movapd %xmm1, %xmm0298; SSE-NEXT: ret{{[l|q]}}299;300; AVX-LABEL: test2_mul_sd:301; AVX: # %bb.0:302; AVX-NEXT: vmulsd %xmm0, %xmm1, %xmm0303; AVX-NEXT: ret{{[l|q]}}304 %1 = extractelement <2 x double> %a, i32 0305 %2 = extractelement <2 x double> %b, i32 0306 %mul = fmul double %1, %2307 %3 = insertelement <2 x double> %b, double %mul, i32 0308 ret <2 x double> %3309}310 311define <2 x double> @test2_div_sd(<2 x double> %a, <2 x double> %b) {312; SSE-LABEL: test2_div_sd:313; SSE: # %bb.0:314; SSE-NEXT: divsd %xmm0, %xmm1315; SSE-NEXT: movapd %xmm1, %xmm0316; SSE-NEXT: ret{{[l|q]}}317;318; AVX-LABEL: test2_div_sd:319; AVX: # %bb.0:320; AVX-NEXT: vdivsd %xmm0, %xmm1, %xmm0321; AVX-NEXT: ret{{[l|q]}}322 %1 = extractelement <2 x double> %a, i32 0323 %2 = extractelement <2 x double> %b, i32 0324 %div = fdiv double %2, %1325 %3 = insertelement <2 x double> %b, double %div, i32 0326 ret <2 x double> %3327}328 329define <4 x float> @test_multiple_add_ss(<4 x float> %a, <4 x float> %b) {330; SSE-LABEL: test_multiple_add_ss:331; SSE: # %bb.0:332; SSE-NEXT: addss %xmm0, %xmm1333; SSE-NEXT: addss %xmm1, %xmm0334; SSE-NEXT: ret{{[l|q]}}335;336; AVX-LABEL: test_multiple_add_ss:337; AVX: # %bb.0:338; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm1339; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm0340; AVX-NEXT: ret{{[l|q]}}341 %1 = extractelement <4 x float> %b, i32 0342 %2 = extractelement <4 x float> %a, i32 0343 %add = fadd float %2, %1344 %add2 = fadd float %2, %add345 %3 = insertelement <4 x float> %a, float %add2, i32 0346 ret <4 x float> %3347}348 349define <4 x float> @test_multiple_sub_ss(<4 x float> %a, <4 x float> %b) {350; SSE-LABEL: test_multiple_sub_ss:351; SSE: # %bb.0:352; SSE-NEXT: movaps %xmm0, %xmm2353; SSE-NEXT: subss %xmm1, %xmm2354; SSE-NEXT: subss %xmm2, %xmm0355; SSE-NEXT: ret{{[l|q]}}356;357; AVX-LABEL: test_multiple_sub_ss:358; AVX: # %bb.0:359; AVX-NEXT: vsubss %xmm1, %xmm0, %xmm1360; AVX-NEXT: vsubss %xmm1, %xmm0, %xmm0361; AVX-NEXT: ret{{[l|q]}}362 %1 = extractelement <4 x float> %b, i32 0363 %2 = extractelement <4 x float> %a, i32 0364 %sub = fsub float %2, %1365 %sub2 = fsub float %2, %sub366 %3 = insertelement <4 x float> %a, float %sub2, i32 0367 ret <4 x float> %3368}369 370define <4 x float> @test_multiple_mul_ss(<4 x float> %a, <4 x float> %b) {371; SSE-LABEL: test_multiple_mul_ss:372; SSE: # %bb.0:373; SSE-NEXT: mulss %xmm0, %xmm1374; SSE-NEXT: mulss %xmm1, %xmm0375; SSE-NEXT: ret{{[l|q]}}376;377; AVX-LABEL: test_multiple_mul_ss:378; AVX: # %bb.0:379; AVX-NEXT: vmulss %xmm1, %xmm0, %xmm1380; AVX-NEXT: vmulss %xmm1, %xmm0, %xmm0381; AVX-NEXT: ret{{[l|q]}}382 %1 = extractelement <4 x float> %b, i32 0383 %2 = extractelement <4 x float> %a, i32 0384 %mul = fmul float %2, %1385 %mul2 = fmul float %2, %mul386 %3 = insertelement <4 x float> %a, float %mul2, i32 0387 ret <4 x float> %3388}389 390define <4 x float> @test_multiple_div_ss(<4 x float> %a, <4 x float> %b) {391; SSE-LABEL: test_multiple_div_ss:392; SSE: # %bb.0:393; SSE-NEXT: movaps %xmm0, %xmm2394; SSE-NEXT: divss %xmm1, %xmm2395; SSE-NEXT: divss %xmm2, %xmm0396; SSE-NEXT: ret{{[l|q]}}397;398; AVX-LABEL: test_multiple_div_ss:399; AVX: # %bb.0:400; AVX-NEXT: vdivss %xmm1, %xmm0, %xmm1401; AVX-NEXT: vdivss %xmm1, %xmm0, %xmm0402; AVX-NEXT: ret{{[l|q]}}403 %1 = extractelement <4 x float> %b, i32 0404 %2 = extractelement <4 x float> %a, i32 0405 %div = fdiv float %2, %1406 %div2 = fdiv float %2, %div407 %3 = insertelement <4 x float> %a, float %div2, i32 0408 ret <4 x float> %3409}410 411; With SSE4.1 or greater, the shuffles in the following tests may412; be lowered to X86Blendi nodes.413 414define <4 x float> @blend_add_ss(<4 x float> %a, float %b) {415; X86-SSE-LABEL: blend_add_ss:416; X86-SSE: # %bb.0:417; X86-SSE-NEXT: addss {{[0-9]+}}(%esp), %xmm0418; X86-SSE-NEXT: retl419;420; X86-AVX-LABEL: blend_add_ss:421; X86-AVX: # %bb.0:422; X86-AVX-NEXT: vaddss {{[0-9]+}}(%esp), %xmm0, %xmm0423; X86-AVX-NEXT: retl424;425; X64-SSE-LABEL: blend_add_ss:426; X64-SSE: # %bb.0:427; X64-SSE-NEXT: addss %xmm1, %xmm0428; X64-SSE-NEXT: retq429;430; X64-AVX-LABEL: blend_add_ss:431; X64-AVX: # %bb.0:432; X64-AVX-NEXT: vaddss %xmm1, %xmm0, %xmm0433; X64-AVX-NEXT: retq434 435 %ext = extractelement <4 x float> %a, i32 0436 %op = fadd float %b, %ext437 %ins = insertelement <4 x float> undef, float %op, i32 0438 %shuf = shufflevector <4 x float> %ins, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7>439 ret <4 x float> %shuf440}441 442define <4 x float> @blend_sub_ss(<4 x float> %a, float %b) {443; X86-SSE-LABEL: blend_sub_ss:444; X86-SSE: # %bb.0:445; X86-SSE-NEXT: subss {{[0-9]+}}(%esp), %xmm0446; X86-SSE-NEXT: retl447;448; X86-AVX-LABEL: blend_sub_ss:449; X86-AVX: # %bb.0:450; X86-AVX-NEXT: vsubss {{[0-9]+}}(%esp), %xmm0, %xmm0451; X86-AVX-NEXT: retl452;453; X64-SSE-LABEL: blend_sub_ss:454; X64-SSE: # %bb.0:455; X64-SSE-NEXT: subss %xmm1, %xmm0456; X64-SSE-NEXT: retq457;458; X64-AVX-LABEL: blend_sub_ss:459; X64-AVX: # %bb.0:460; X64-AVX-NEXT: vsubss %xmm1, %xmm0, %xmm0461; X64-AVX-NEXT: retq462 463 %ext = extractelement <4 x float> %a, i32 0464 %op = fsub float %ext, %b465 %ins = insertelement <4 x float> undef, float %op, i32 0466 %shuf = shufflevector <4 x float> %ins, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7>467 ret <4 x float> %shuf468}469 470define <4 x float> @blend_mul_ss(<4 x float> %a, float %b) {471; X86-SSE-LABEL: blend_mul_ss:472; X86-SSE: # %bb.0:473; X86-SSE-NEXT: mulss {{[0-9]+}}(%esp), %xmm0474; X86-SSE-NEXT: retl475;476; X86-AVX-LABEL: blend_mul_ss:477; X86-AVX: # %bb.0:478; X86-AVX-NEXT: vmulss {{[0-9]+}}(%esp), %xmm0, %xmm0479; X86-AVX-NEXT: retl480;481; X64-SSE-LABEL: blend_mul_ss:482; X64-SSE: # %bb.0:483; X64-SSE-NEXT: mulss %xmm1, %xmm0484; X64-SSE-NEXT: retq485;486; X64-AVX-LABEL: blend_mul_ss:487; X64-AVX: # %bb.0:488; X64-AVX-NEXT: vmulss %xmm1, %xmm0, %xmm0489; X64-AVX-NEXT: retq490 491 %ext = extractelement <4 x float> %a, i32 0492 %op = fmul float %b, %ext493 %ins = insertelement <4 x float> undef, float %op, i32 0494 %shuf = shufflevector <4 x float> %ins, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7>495 ret <4 x float> %shuf496}497 498define <4 x float> @blend_div_ss(<4 x float> %a, float %b) {499; X86-SSE-LABEL: blend_div_ss:500; X86-SSE: # %bb.0:501; X86-SSE-NEXT: divss {{[0-9]+}}(%esp), %xmm0502; X86-SSE-NEXT: retl503;504; X86-AVX-LABEL: blend_div_ss:505; X86-AVX: # %bb.0:506; X86-AVX-NEXT: vdivss {{[0-9]+}}(%esp), %xmm0, %xmm0507; X86-AVX-NEXT: retl508;509; X64-SSE-LABEL: blend_div_ss:510; X64-SSE: # %bb.0:511; X64-SSE-NEXT: divss %xmm1, %xmm0512; X64-SSE-NEXT: retq513;514; X64-AVX-LABEL: blend_div_ss:515; X64-AVX: # %bb.0:516; X64-AVX-NEXT: vdivss %xmm1, %xmm0, %xmm0517; X64-AVX-NEXT: retq518 519 %ext = extractelement <4 x float> %a, i32 0520 %op = fdiv float %ext, %b521 %ins = insertelement <4 x float> undef, float %op, i32 0522 %shuf = shufflevector <4 x float> %ins, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7>523 ret <4 x float> %shuf524}525 526define <2 x double> @blend_add_sd(<2 x double> %a, double %b) {527; X86-SSE-LABEL: blend_add_sd:528; X86-SSE: # %bb.0:529; X86-SSE-NEXT: addsd {{[0-9]+}}(%esp), %xmm0530; X86-SSE-NEXT: retl531;532; X86-AVX-LABEL: blend_add_sd:533; X86-AVX: # %bb.0:534; X86-AVX-NEXT: vaddsd {{[0-9]+}}(%esp), %xmm0, %xmm0535; X86-AVX-NEXT: retl536;537; X64-SSE-LABEL: blend_add_sd:538; X64-SSE: # %bb.0:539; X64-SSE-NEXT: addsd %xmm1, %xmm0540; X64-SSE-NEXT: retq541;542; X64-AVX-LABEL: blend_add_sd:543; X64-AVX: # %bb.0:544; X64-AVX-NEXT: vaddsd %xmm1, %xmm0, %xmm0545; X64-AVX-NEXT: retq546 547 %ext = extractelement <2 x double> %a, i32 0548 %op = fadd double %b, %ext549 %ins = insertelement <2 x double> undef, double %op, i32 0550 %shuf = shufflevector <2 x double> %ins, <2 x double> %a, <2 x i32> <i32 0, i32 3>551 ret <2 x double> %shuf552}553 554define <2 x double> @blend_sub_sd(<2 x double> %a, double %b) {555; X86-SSE-LABEL: blend_sub_sd:556; X86-SSE: # %bb.0:557; X86-SSE-NEXT: subsd {{[0-9]+}}(%esp), %xmm0558; X86-SSE-NEXT: retl559;560; X86-AVX-LABEL: blend_sub_sd:561; X86-AVX: # %bb.0:562; X86-AVX-NEXT: vsubsd {{[0-9]+}}(%esp), %xmm0, %xmm0563; X86-AVX-NEXT: retl564;565; X64-SSE-LABEL: blend_sub_sd:566; X64-SSE: # %bb.0:567; X64-SSE-NEXT: subsd %xmm1, %xmm0568; X64-SSE-NEXT: retq569;570; X64-AVX-LABEL: blend_sub_sd:571; X64-AVX: # %bb.0:572; X64-AVX-NEXT: vsubsd %xmm1, %xmm0, %xmm0573; X64-AVX-NEXT: retq574 575 %ext = extractelement <2 x double> %a, i32 0576 %op = fsub double %ext, %b577 %ins = insertelement <2 x double> undef, double %op, i32 0578 %shuf = shufflevector <2 x double> %ins, <2 x double> %a, <2 x i32> <i32 0, i32 3>579 ret <2 x double> %shuf580}581 582define <2 x double> @blend_mul_sd(<2 x double> %a, double %b) {583; X86-SSE-LABEL: blend_mul_sd:584; X86-SSE: # %bb.0:585; X86-SSE-NEXT: mulsd {{[0-9]+}}(%esp), %xmm0586; X86-SSE-NEXT: retl587;588; X86-AVX-LABEL: blend_mul_sd:589; X86-AVX: # %bb.0:590; X86-AVX-NEXT: vmulsd {{[0-9]+}}(%esp), %xmm0, %xmm0591; X86-AVX-NEXT: retl592;593; X64-SSE-LABEL: blend_mul_sd:594; X64-SSE: # %bb.0:595; X64-SSE-NEXT: mulsd %xmm1, %xmm0596; X64-SSE-NEXT: retq597;598; X64-AVX-LABEL: blend_mul_sd:599; X64-AVX: # %bb.0:600; X64-AVX-NEXT: vmulsd %xmm1, %xmm0, %xmm0601; X64-AVX-NEXT: retq602 603 %ext = extractelement <2 x double> %a, i32 0604 %op = fmul double %b, %ext605 %ins = insertelement <2 x double> undef, double %op, i32 0606 %shuf = shufflevector <2 x double> %ins, <2 x double> %a, <2 x i32> <i32 0, i32 3>607 ret <2 x double> %shuf608}609 610define <2 x double> @blend_div_sd(<2 x double> %a, double %b) {611; X86-SSE-LABEL: blend_div_sd:612; X86-SSE: # %bb.0:613; X86-SSE-NEXT: divsd {{[0-9]+}}(%esp), %xmm0614; X86-SSE-NEXT: retl615;616; X86-AVX-LABEL: blend_div_sd:617; X86-AVX: # %bb.0:618; X86-AVX-NEXT: vdivsd {{[0-9]+}}(%esp), %xmm0, %xmm0619; X86-AVX-NEXT: retl620;621; X64-SSE-LABEL: blend_div_sd:622; X64-SSE: # %bb.0:623; X64-SSE-NEXT: divsd %xmm1, %xmm0624; X64-SSE-NEXT: retq625;626; X64-AVX-LABEL: blend_div_sd:627; X64-AVX: # %bb.0:628; X64-AVX-NEXT: vdivsd %xmm1, %xmm0, %xmm0629; X64-AVX-NEXT: retq630 631 %ext = extractelement <2 x double> %a, i32 0632 %op = fdiv double %ext, %b633 %ins = insertelement <2 x double> undef, double %op, i32 0634 %shuf = shufflevector <2 x double> %ins, <2 x double> %a, <2 x i32> <i32 0, i32 3>635 ret <2 x double> %shuf636}637 638; Ensure that the backend selects SSE/AVX scalar fp instructions639; from a packed fp instruction plus a vector insert.640 641define <4 x float> @insert_test_add_ss(<4 x float> %a, <4 x float> %b) {642; SSE-LABEL: insert_test_add_ss:643; SSE: # %bb.0:644; SSE-NEXT: addss %xmm1, %xmm0645; SSE-NEXT: ret{{[l|q]}}646;647; AVX-LABEL: insert_test_add_ss:648; AVX: # %bb.0:649; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm0650; AVX-NEXT: ret{{[l|q]}}651 %1 = fadd <4 x float> %a, %b652 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7>653 ret <4 x float> %2654}655 656define <4 x float> @insert_test_sub_ss(<4 x float> %a, <4 x float> %b) {657; SSE-LABEL: insert_test_sub_ss:658; SSE: # %bb.0:659; SSE-NEXT: subss %xmm1, %xmm0660; SSE-NEXT: ret{{[l|q]}}661;662; AVX-LABEL: insert_test_sub_ss:663; AVX: # %bb.0:664; AVX-NEXT: vsubss %xmm1, %xmm0, %xmm0665; AVX-NEXT: ret{{[l|q]}}666 %1 = fsub <4 x float> %a, %b667 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7>668 ret <4 x float> %2669}670 671define <4 x float> @insert_test_mul_ss(<4 x float> %a, <4 x float> %b) {672; SSE-LABEL: insert_test_mul_ss:673; SSE: # %bb.0:674; SSE-NEXT: mulss %xmm1, %xmm0675; SSE-NEXT: ret{{[l|q]}}676;677; AVX-LABEL: insert_test_mul_ss:678; AVX: # %bb.0:679; AVX-NEXT: vmulss %xmm1, %xmm0, %xmm0680; AVX-NEXT: ret{{[l|q]}}681 %1 = fmul <4 x float> %a, %b682 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7>683 ret <4 x float> %2684}685 686define <4 x float> @insert_test_div_ss(<4 x float> %a, <4 x float> %b) {687; SSE-LABEL: insert_test_div_ss:688; SSE: # %bb.0:689; SSE-NEXT: divss %xmm1, %xmm0690; SSE-NEXT: ret{{[l|q]}}691;692; AVX-LABEL: insert_test_div_ss:693; AVX: # %bb.0:694; AVX-NEXT: vdivss %xmm1, %xmm0, %xmm0695; AVX-NEXT: ret{{[l|q]}}696 %1 = fdiv <4 x float> %a, %b697 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7>698 ret <4 x float> %2699}700 701define <2 x double> @insert_test_add_sd(<2 x double> %a, <2 x double> %b) {702; SSE-LABEL: insert_test_add_sd:703; SSE: # %bb.0:704; SSE-NEXT: addsd %xmm1, %xmm0705; SSE-NEXT: ret{{[l|q]}}706;707; AVX-LABEL: insert_test_add_sd:708; AVX: # %bb.0:709; AVX-NEXT: vaddsd %xmm1, %xmm0, %xmm0710; AVX-NEXT: ret{{[l|q]}}711 %1 = fadd <2 x double> %a, %b712 %2 = shufflevector <2 x double> %1, <2 x double> %a, <2 x i32> <i32 0, i32 3>713 ret <2 x double> %2714}715 716define <2 x double> @insert_test_sub_sd(<2 x double> %a, <2 x double> %b) {717; SSE-LABEL: insert_test_sub_sd:718; SSE: # %bb.0:719; SSE-NEXT: subsd %xmm1, %xmm0720; SSE-NEXT: ret{{[l|q]}}721;722; AVX-LABEL: insert_test_sub_sd:723; AVX: # %bb.0:724; AVX-NEXT: vsubsd %xmm1, %xmm0, %xmm0725; AVX-NEXT: ret{{[l|q]}}726 %1 = fsub <2 x double> %a, %b727 %2 = shufflevector <2 x double> %1, <2 x double> %a, <2 x i32> <i32 0, i32 3>728 ret <2 x double> %2729}730 731define <2 x double> @insert_test_mul_sd(<2 x double> %a, <2 x double> %b) {732; SSE-LABEL: insert_test_mul_sd:733; SSE: # %bb.0:734; SSE-NEXT: mulsd %xmm1, %xmm0735; SSE-NEXT: ret{{[l|q]}}736;737; AVX-LABEL: insert_test_mul_sd:738; AVX: # %bb.0:739; AVX-NEXT: vmulsd %xmm1, %xmm0, %xmm0740; AVX-NEXT: ret{{[l|q]}}741 %1 = fmul <2 x double> %a, %b742 %2 = shufflevector <2 x double> %1, <2 x double> %a, <2 x i32> <i32 0, i32 3>743 ret <2 x double> %2744}745 746define <2 x double> @insert_test_div_sd(<2 x double> %a, <2 x double> %b) {747; SSE-LABEL: insert_test_div_sd:748; SSE: # %bb.0:749; SSE-NEXT: divsd %xmm1, %xmm0750; SSE-NEXT: ret{{[l|q]}}751;752; AVX-LABEL: insert_test_div_sd:753; AVX: # %bb.0:754; AVX-NEXT: vdivsd %xmm1, %xmm0, %xmm0755; AVX-NEXT: ret{{[l|q]}}756 %1 = fdiv <2 x double> %a, %b757 %2 = shufflevector <2 x double> %1, <2 x double> %a, <2 x i32> <i32 0, i32 3>758 ret <2 x double> %2759}760 761define <4 x float> @insert_test2_add_ss(<4 x float> %a, <4 x float> %b) {762; SSE-LABEL: insert_test2_add_ss:763; SSE: # %bb.0:764; SSE-NEXT: addss %xmm0, %xmm1765; SSE-NEXT: movaps %xmm1, %xmm0766; SSE-NEXT: ret{{[l|q]}}767;768; AVX-LABEL: insert_test2_add_ss:769; AVX: # %bb.0:770; AVX-NEXT: vaddss %xmm0, %xmm1, %xmm0771; AVX-NEXT: ret{{[l|q]}}772 %1 = fadd <4 x float> %b, %a773 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 7>774 ret <4 x float> %2775}776 777define <4 x float> @insert_test2_sub_ss(<4 x float> %a, <4 x float> %b) {778; SSE-LABEL: insert_test2_sub_ss:779; SSE: # %bb.0:780; SSE-NEXT: subss %xmm0, %xmm1781; SSE-NEXT: movaps %xmm1, %xmm0782; SSE-NEXT: ret{{[l|q]}}783;784; AVX-LABEL: insert_test2_sub_ss:785; AVX: # %bb.0:786; AVX-NEXT: vsubss %xmm0, %xmm1, %xmm0787; AVX-NEXT: ret{{[l|q]}}788 %1 = fsub <4 x float> %b, %a789 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 7>790 ret <4 x float> %2791}792 793define <4 x float> @insert_test2_mul_ss(<4 x float> %a, <4 x float> %b) {794; SSE-LABEL: insert_test2_mul_ss:795; SSE: # %bb.0:796; SSE-NEXT: mulss %xmm0, %xmm1797; SSE-NEXT: movaps %xmm1, %xmm0798; SSE-NEXT: ret{{[l|q]}}799;800; AVX-LABEL: insert_test2_mul_ss:801; AVX: # %bb.0:802; AVX-NEXT: vmulss %xmm0, %xmm1, %xmm0803; AVX-NEXT: ret{{[l|q]}}804 %1 = fmul <4 x float> %b, %a805 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 7>806 ret <4 x float> %2807}808 809define <4 x float> @insert_test2_div_ss(<4 x float> %a, <4 x float> %b) {810; SSE-LABEL: insert_test2_div_ss:811; SSE: # %bb.0:812; SSE-NEXT: divss %xmm0, %xmm1813; SSE-NEXT: movaps %xmm1, %xmm0814; SSE-NEXT: ret{{[l|q]}}815;816; AVX-LABEL: insert_test2_div_ss:817; AVX: # %bb.0:818; AVX-NEXT: vdivss %xmm0, %xmm1, %xmm0819; AVX-NEXT: ret{{[l|q]}}820 %1 = fdiv <4 x float> %b, %a821 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 7>822 ret <4 x float> %2823}824 825define <2 x double> @insert_test2_add_sd(<2 x double> %a, <2 x double> %b) {826; SSE-LABEL: insert_test2_add_sd:827; SSE: # %bb.0:828; SSE-NEXT: addsd %xmm0, %xmm1829; SSE-NEXT: movapd %xmm1, %xmm0830; SSE-NEXT: ret{{[l|q]}}831;832; AVX-LABEL: insert_test2_add_sd:833; AVX: # %bb.0:834; AVX-NEXT: vaddsd %xmm0, %xmm1, %xmm0835; AVX-NEXT: ret{{[l|q]}}836 %1 = fadd <2 x double> %b, %a837 %2 = shufflevector <2 x double> %1, <2 x double> %b, <2 x i32> <i32 0, i32 3>838 ret <2 x double> %2839}840 841define <2 x double> @insert_test2_sub_sd(<2 x double> %a, <2 x double> %b) {842; SSE-LABEL: insert_test2_sub_sd:843; SSE: # %bb.0:844; SSE-NEXT: subsd %xmm0, %xmm1845; SSE-NEXT: movapd %xmm1, %xmm0846; SSE-NEXT: ret{{[l|q]}}847;848; AVX-LABEL: insert_test2_sub_sd:849; AVX: # %bb.0:850; AVX-NEXT: vsubsd %xmm0, %xmm1, %xmm0851; AVX-NEXT: ret{{[l|q]}}852 %1 = fsub <2 x double> %b, %a853 %2 = shufflevector <2 x double> %1, <2 x double> %b, <2 x i32> <i32 0, i32 3>854 ret <2 x double> %2855}856 857define <2 x double> @insert_test2_mul_sd(<2 x double> %a, <2 x double> %b) {858; SSE-LABEL: insert_test2_mul_sd:859; SSE: # %bb.0:860; SSE-NEXT: mulsd %xmm0, %xmm1861; SSE-NEXT: movapd %xmm1, %xmm0862; SSE-NEXT: ret{{[l|q]}}863;864; AVX-LABEL: insert_test2_mul_sd:865; AVX: # %bb.0:866; AVX-NEXT: vmulsd %xmm0, %xmm1, %xmm0867; AVX-NEXT: ret{{[l|q]}}868 %1 = fmul <2 x double> %b, %a869 %2 = shufflevector <2 x double> %1, <2 x double> %b, <2 x i32> <i32 0, i32 3>870 ret <2 x double> %2871}872 873define <2 x double> @insert_test2_div_sd(<2 x double> %a, <2 x double> %b) {874; SSE-LABEL: insert_test2_div_sd:875; SSE: # %bb.0:876; SSE-NEXT: divsd %xmm0, %xmm1877; SSE-NEXT: movapd %xmm1, %xmm0878; SSE-NEXT: ret{{[l|q]}}879;880; AVX-LABEL: insert_test2_div_sd:881; AVX: # %bb.0:882; AVX-NEXT: vdivsd %xmm0, %xmm1, %xmm0883; AVX-NEXT: ret{{[l|q]}}884 %1 = fdiv <2 x double> %b, %a885 %2 = shufflevector <2 x double> %1, <2 x double> %b, <2 x i32> <i32 0, i32 3>886 ret <2 x double> %2887}888 889define <4 x float> @insert_test3_add_ss(<4 x float> %a, <4 x float> %b) {890; SSE-LABEL: insert_test3_add_ss:891; SSE: # %bb.0:892; SSE-NEXT: addss %xmm1, %xmm0893; SSE-NEXT: ret{{[l|q]}}894;895; AVX-LABEL: insert_test3_add_ss:896; AVX: # %bb.0:897; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm0898; AVX-NEXT: ret{{[l|q]}}899 %1 = fadd <4 x float> %a, %b900 %2 = select <4 x i1> <i1 false, i1 true, i1 true, i1 true>, <4 x float> %a, <4 x float> %1901 ret <4 x float> %2902}903 904define <4 x float> @insert_test3_sub_ss(<4 x float> %a, <4 x float> %b) {905; SSE-LABEL: insert_test3_sub_ss:906; SSE: # %bb.0:907; SSE-NEXT: subss %xmm1, %xmm0908; SSE-NEXT: ret{{[l|q]}}909;910; AVX-LABEL: insert_test3_sub_ss:911; AVX: # %bb.0:912; AVX-NEXT: vsubss %xmm1, %xmm0, %xmm0913; AVX-NEXT: ret{{[l|q]}}914 %1 = fsub <4 x float> %a, %b915 %2 = select <4 x i1> <i1 false, i1 true, i1 true, i1 true>, <4 x float> %a, <4 x float> %1916 ret <4 x float> %2917}918 919define <4 x float> @insert_test3_mul_ss(<4 x float> %a, <4 x float> %b) {920; SSE-LABEL: insert_test3_mul_ss:921; SSE: # %bb.0:922; SSE-NEXT: mulss %xmm1, %xmm0923; SSE-NEXT: ret{{[l|q]}}924;925; AVX-LABEL: insert_test3_mul_ss:926; AVX: # %bb.0:927; AVX-NEXT: vmulss %xmm1, %xmm0, %xmm0928; AVX-NEXT: ret{{[l|q]}}929 %1 = fmul <4 x float> %a, %b930 %2 = select <4 x i1> <i1 false, i1 true, i1 true, i1 true>, <4 x float> %a, <4 x float> %1931 ret <4 x float> %2932}933 934define <4 x float> @insert_test3_div_ss(<4 x float> %a, <4 x float> %b) {935; SSE-LABEL: insert_test3_div_ss:936; SSE: # %bb.0:937; SSE-NEXT: divss %xmm1, %xmm0938; SSE-NEXT: ret{{[l|q]}}939;940; AVX-LABEL: insert_test3_div_ss:941; AVX: # %bb.0:942; AVX-NEXT: vdivss %xmm1, %xmm0, %xmm0943; AVX-NEXT: ret{{[l|q]}}944 %1 = fdiv <4 x float> %a, %b945 %2 = select <4 x i1> <i1 false, i1 true, i1 true, i1 true>, <4 x float> %a, <4 x float> %1946 ret <4 x float> %2947}948 949define <2 x double> @insert_test3_add_sd(<2 x double> %a, <2 x double> %b) {950; SSE-LABEL: insert_test3_add_sd:951; SSE: # %bb.0:952; SSE-NEXT: addsd %xmm1, %xmm0953; SSE-NEXT: ret{{[l|q]}}954;955; AVX-LABEL: insert_test3_add_sd:956; AVX: # %bb.0:957; AVX-NEXT: vaddsd %xmm1, %xmm0, %xmm0958; AVX-NEXT: ret{{[l|q]}}959 %1 = fadd <2 x double> %a, %b960 %2 = select <2 x i1> <i1 false, i1 true>, <2 x double> %a, <2 x double> %1961 ret <2 x double> %2962}963 964define <2 x double> @insert_test3_sub_sd(<2 x double> %a, <2 x double> %b) {965; SSE-LABEL: insert_test3_sub_sd:966; SSE: # %bb.0:967; SSE-NEXT: subsd %xmm1, %xmm0968; SSE-NEXT: ret{{[l|q]}}969;970; AVX-LABEL: insert_test3_sub_sd:971; AVX: # %bb.0:972; AVX-NEXT: vsubsd %xmm1, %xmm0, %xmm0973; AVX-NEXT: ret{{[l|q]}}974 %1 = fsub <2 x double> %a, %b975 %2 = select <2 x i1> <i1 false, i1 true>, <2 x double> %a, <2 x double> %1976 ret <2 x double> %2977}978 979define <2 x double> @insert_test3_mul_sd(<2 x double> %a, <2 x double> %b) {980; SSE-LABEL: insert_test3_mul_sd:981; SSE: # %bb.0:982; SSE-NEXT: mulsd %xmm1, %xmm0983; SSE-NEXT: ret{{[l|q]}}984;985; AVX-LABEL: insert_test3_mul_sd:986; AVX: # %bb.0:987; AVX-NEXT: vmulsd %xmm1, %xmm0, %xmm0988; AVX-NEXT: ret{{[l|q]}}989 %1 = fmul <2 x double> %a, %b990 %2 = select <2 x i1> <i1 false, i1 true>, <2 x double> %a, <2 x double> %1991 ret <2 x double> %2992}993 994define <2 x double> @insert_test3_div_sd(<2 x double> %a, <2 x double> %b) {995; SSE-LABEL: insert_test3_div_sd:996; SSE: # %bb.0:997; SSE-NEXT: divsd %xmm1, %xmm0998; SSE-NEXT: ret{{[l|q]}}999;1000; AVX-LABEL: insert_test3_div_sd:1001; AVX: # %bb.0:1002; AVX-NEXT: vdivsd %xmm1, %xmm0, %xmm01003; AVX-NEXT: ret{{[l|q]}}1004 %1 = fdiv <2 x double> %a, %b1005 %2 = select <2 x i1> <i1 false, i1 true>, <2 x double> %a, <2 x double> %11006 ret <2 x double> %21007}1008 1009define <4 x float> @insert_test4_add_ss(<4 x float> %a, <4 x float> %b) {1010; SSE-LABEL: insert_test4_add_ss:1011; SSE: # %bb.0:1012; SSE-NEXT: addss %xmm0, %xmm11013; SSE-NEXT: movaps %xmm1, %xmm01014; SSE-NEXT: ret{{[l|q]}}1015;1016; AVX-LABEL: insert_test4_add_ss:1017; AVX: # %bb.0:1018; AVX-NEXT: vaddss %xmm0, %xmm1, %xmm01019; AVX-NEXT: ret{{[l|q]}}1020 %1 = fadd <4 x float> %b, %a1021 %2 = select <4 x i1> <i1 false, i1 true, i1 true, i1 true>, <4 x float> %b, <4 x float> %11022 ret <4 x float> %21023}1024 1025define <4 x float> @insert_test4_sub_ss(<4 x float> %a, <4 x float> %b) {1026; SSE-LABEL: insert_test4_sub_ss:1027; SSE: # %bb.0:1028; SSE-NEXT: subss %xmm0, %xmm11029; SSE-NEXT: movaps %xmm1, %xmm01030; SSE-NEXT: ret{{[l|q]}}1031;1032; AVX-LABEL: insert_test4_sub_ss:1033; AVX: # %bb.0:1034; AVX-NEXT: vsubss %xmm0, %xmm1, %xmm01035; AVX-NEXT: ret{{[l|q]}}1036 %1 = fsub <4 x float> %b, %a1037 %2 = select <4 x i1> <i1 false, i1 true, i1 true, i1 true>, <4 x float> %b, <4 x float> %11038 ret <4 x float> %21039}1040 1041define <4 x float> @insert_test4_mul_ss(<4 x float> %a, <4 x float> %b) {1042; SSE-LABEL: insert_test4_mul_ss:1043; SSE: # %bb.0:1044; SSE-NEXT: mulss %xmm0, %xmm11045; SSE-NEXT: movaps %xmm1, %xmm01046; SSE-NEXT: ret{{[l|q]}}1047;1048; AVX-LABEL: insert_test4_mul_ss:1049; AVX: # %bb.0:1050; AVX-NEXT: vmulss %xmm0, %xmm1, %xmm01051; AVX-NEXT: ret{{[l|q]}}1052 %1 = fmul <4 x float> %b, %a1053 %2 = select <4 x i1> <i1 false, i1 true, i1 true, i1 true>, <4 x float> %b, <4 x float> %11054 ret <4 x float> %21055}1056 1057define <4 x float> @insert_test4_div_ss(<4 x float> %a, <4 x float> %b) {1058; SSE-LABEL: insert_test4_div_ss:1059; SSE: # %bb.0:1060; SSE-NEXT: divss %xmm0, %xmm11061; SSE-NEXT: movaps %xmm1, %xmm01062; SSE-NEXT: ret{{[l|q]}}1063;1064; AVX-LABEL: insert_test4_div_ss:1065; AVX: # %bb.0:1066; AVX-NEXT: vdivss %xmm0, %xmm1, %xmm01067; AVX-NEXT: ret{{[l|q]}}1068 %1 = fdiv <4 x float> %b, %a1069 %2 = select <4 x i1> <i1 false, i1 true, i1 true, i1 true>, <4 x float> %b, <4 x float> %11070 ret <4 x float> %21071}1072 1073define <2 x double> @insert_test4_add_sd(<2 x double> %a, <2 x double> %b) {1074; SSE-LABEL: insert_test4_add_sd:1075; SSE: # %bb.0:1076; SSE-NEXT: addsd %xmm0, %xmm11077; SSE-NEXT: movapd %xmm1, %xmm01078; SSE-NEXT: ret{{[l|q]}}1079;1080; AVX-LABEL: insert_test4_add_sd:1081; AVX: # %bb.0:1082; AVX-NEXT: vaddsd %xmm0, %xmm1, %xmm01083; AVX-NEXT: ret{{[l|q]}}1084 %1 = fadd <2 x double> %b, %a1085 %2 = select <2 x i1> <i1 false, i1 true>, <2 x double> %b, <2 x double> %11086 ret <2 x double> %21087}1088 1089define <2 x double> @insert_test4_sub_sd(<2 x double> %a, <2 x double> %b) {1090; SSE-LABEL: insert_test4_sub_sd:1091; SSE: # %bb.0:1092; SSE-NEXT: subsd %xmm0, %xmm11093; SSE-NEXT: movapd %xmm1, %xmm01094; SSE-NEXT: ret{{[l|q]}}1095;1096; AVX-LABEL: insert_test4_sub_sd:1097; AVX: # %bb.0:1098; AVX-NEXT: vsubsd %xmm0, %xmm1, %xmm01099; AVX-NEXT: ret{{[l|q]}}1100 %1 = fsub <2 x double> %b, %a1101 %2 = select <2 x i1> <i1 false, i1 true>, <2 x double> %b, <2 x double> %11102 ret <2 x double> %21103}1104 1105define <2 x double> @insert_test4_mul_sd(<2 x double> %a, <2 x double> %b) {1106; SSE-LABEL: insert_test4_mul_sd:1107; SSE: # %bb.0:1108; SSE-NEXT: mulsd %xmm0, %xmm11109; SSE-NEXT: movapd %xmm1, %xmm01110; SSE-NEXT: ret{{[l|q]}}1111;1112; AVX-LABEL: insert_test4_mul_sd:1113; AVX: # %bb.0:1114; AVX-NEXT: vmulsd %xmm0, %xmm1, %xmm01115; AVX-NEXT: ret{{[l|q]}}1116 %1 = fmul <2 x double> %b, %a1117 %2 = select <2 x i1> <i1 false, i1 true>, <2 x double> %b, <2 x double> %11118 ret <2 x double> %21119}1120 1121define <2 x double> @insert_test4_div_sd(<2 x double> %a, <2 x double> %b) {1122; SSE-LABEL: insert_test4_div_sd:1123; SSE: # %bb.0:1124; SSE-NEXT: divsd %xmm0, %xmm11125; SSE-NEXT: movapd %xmm1, %xmm01126; SSE-NEXT: ret{{[l|q]}}1127;1128; AVX-LABEL: insert_test4_div_sd:1129; AVX: # %bb.0:1130; AVX-NEXT: vdivsd %xmm0, %xmm1, %xmm01131; AVX-NEXT: ret{{[l|q]}}1132 %1 = fdiv <2 x double> %b, %a1133 %2 = select <2 x i1> <i1 false, i1 true>, <2 x double> %b, <2 x double> %11134 ret <2 x double> %21135}1136 1137define <4 x float> @insert_test5_add_ss(<4 x float> %a, <4 x float> %b) {1138; SSE-LABEL: insert_test5_add_ss:1139; SSE: # %bb.0:1140; SSE-NEXT: addss %xmm1, %xmm01141; SSE-NEXT: ret{{[l|q]}}1142;1143; AVX-LABEL: insert_test5_add_ss:1144; AVX: # %bb.0:1145; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm01146; AVX-NEXT: ret{{[l|q]}}1147 %1 = fadd <4 x float> %b, %a1148 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7>1149 ret <4 x float> %21150}1151 1152define <4 x float> @insert_test5_sub_ss(<4 x float> %a, <4 x float> %b) {1153; SSE-LABEL: insert_test5_sub_ss:1154; SSE: # %bb.0:1155; SSE-NEXT: subps %xmm0, %xmm11156; SSE-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]1157; SSE-NEXT: ret{{[l|q]}}1158;1159; AVX-LABEL: insert_test5_sub_ss:1160; AVX: # %bb.0:1161; AVX-NEXT: vsubps %xmm0, %xmm1, %xmm11162; AVX-NEXT: vmovss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]1163; AVX-NEXT: ret{{[l|q]}}1164 %1 = fsub <4 x float> %b, %a1165 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7>1166 ret <4 x float> %21167}1168 1169define <4 x float> @insert_test5_mul_ss(<4 x float> %a, <4 x float> %b) {1170; SSE-LABEL: insert_test5_mul_ss:1171; SSE: # %bb.0:1172; SSE-NEXT: mulss %xmm1, %xmm01173; SSE-NEXT: ret{{[l|q]}}1174;1175; AVX-LABEL: insert_test5_mul_ss:1176; AVX: # %bb.0:1177; AVX-NEXT: vmulss %xmm1, %xmm0, %xmm01178; AVX-NEXT: ret{{[l|q]}}1179 %1 = fmul <4 x float> %b, %a1180 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7>1181 ret <4 x float> %21182}1183 1184define <4 x float> @insert_test5_div_ss(<4 x float> %a, <4 x float> %b) {1185; SSE-LABEL: insert_test5_div_ss:1186; SSE: # %bb.0:1187; SSE-NEXT: divps %xmm0, %xmm11188; SSE-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]1189; SSE-NEXT: ret{{[l|q]}}1190;1191; AVX-LABEL: insert_test5_div_ss:1192; AVX: # %bb.0:1193; AVX-NEXT: vdivps %xmm0, %xmm1, %xmm11194; AVX-NEXT: vmovss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]1195; AVX-NEXT: ret{{[l|q]}}1196 %1 = fdiv <4 x float> %b, %a1197 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7>1198 ret <4 x float> %21199}1200 1201define <2 x double> @insert_test5_add_sd(<2 x double> %a, <2 x double> %b) {1202; SSE-LABEL: insert_test5_add_sd:1203; SSE: # %bb.0:1204; SSE-NEXT: addsd %xmm1, %xmm01205; SSE-NEXT: ret{{[l|q]}}1206;1207; AVX-LABEL: insert_test5_add_sd:1208; AVX: # %bb.0:1209; AVX-NEXT: vaddsd %xmm1, %xmm0, %xmm01210; AVX-NEXT: ret{{[l|q]}}1211 %1 = fadd <2 x double> %b, %a1212 %2 = shufflevector <2 x double> %1, <2 x double> %a, <2 x i32> <i32 0, i32 3>1213 ret <2 x double> %21214}1215 1216define <2 x double> @insert_test5_sub_sd(<2 x double> %a, <2 x double> %b) {1217; SSE-LABEL: insert_test5_sub_sd:1218; SSE: # %bb.0:1219; SSE-NEXT: subpd %xmm0, %xmm11220; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]1221; SSE-NEXT: ret{{[l|q]}}1222;1223; AVX-LABEL: insert_test5_sub_sd:1224; AVX: # %bb.0:1225; AVX-NEXT: vsubpd %xmm0, %xmm1, %xmm11226; AVX-NEXT: vmovsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]1227; AVX-NEXT: ret{{[l|q]}}1228 %1 = fsub <2 x double> %b, %a1229 %2 = shufflevector <2 x double> %1, <2 x double> %a, <2 x i32> <i32 0, i32 3>1230 ret <2 x double> %21231}1232 1233define <2 x double> @insert_test5_mul_sd(<2 x double> %a, <2 x double> %b) {1234; SSE-LABEL: insert_test5_mul_sd:1235; SSE: # %bb.0:1236; SSE-NEXT: mulsd %xmm1, %xmm01237; SSE-NEXT: ret{{[l|q]}}1238;1239; AVX-LABEL: insert_test5_mul_sd:1240; AVX: # %bb.0:1241; AVX-NEXT: vmulsd %xmm1, %xmm0, %xmm01242; AVX-NEXT: ret{{[l|q]}}1243 %1 = fmul <2 x double> %b, %a1244 %2 = shufflevector <2 x double> %1, <2 x double> %a, <2 x i32> <i32 0, i32 3>1245 ret <2 x double> %21246}1247 1248define <2 x double> @insert_test5_div_sd(<2 x double> %a, <2 x double> %b) {1249; SSE-LABEL: insert_test5_div_sd:1250; SSE: # %bb.0:1251; SSE-NEXT: divpd %xmm0, %xmm11252; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]1253; SSE-NEXT: ret{{[l|q]}}1254;1255; AVX-LABEL: insert_test5_div_sd:1256; AVX: # %bb.0:1257; AVX-NEXT: vdivpd %xmm0, %xmm1, %xmm11258; AVX-NEXT: vmovsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]1259; AVX-NEXT: ret{{[l|q]}}1260 %1 = fdiv <2 x double> %b, %a1261 %2 = shufflevector <2 x double> %1, <2 x double> %a, <2 x i32> <i32 0, i32 3>1262 ret <2 x double> %21263}1264 1265define <4 x float> @add_ss_mask(<4 x float> %a, <4 x float> %b, <4 x float> %c, i8 %mask) {1266; X86-SSE-LABEL: add_ss_mask:1267; X86-SSE: # %bb.0:1268; X86-SSE-NEXT: testb $1, {{[0-9]+}}(%esp)1269; X86-SSE-NEXT: jne .LBB70_11270; X86-SSE-NEXT: # %bb.2:1271; X86-SSE-NEXT: movss {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3]1272; X86-SSE-NEXT: retl1273; X86-SSE-NEXT: .LBB70_1:1274; X86-SSE-NEXT: addss %xmm0, %xmm11275; X86-SSE-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]1276; X86-SSE-NEXT: retl1277;1278; X86-AVX1-LABEL: add_ss_mask:1279; X86-AVX1: # %bb.0:1280; X86-AVX1-NEXT: testb $1, {{[0-9]+}}(%esp)1281; X86-AVX1-NEXT: je .LBB70_21282; X86-AVX1-NEXT: # %bb.1:1283; X86-AVX1-NEXT: vaddss %xmm1, %xmm0, %xmm21284; X86-AVX1-NEXT: .LBB70_2:1285; X86-AVX1-NEXT: vmovss {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3]1286; X86-AVX1-NEXT: retl1287;1288; X86-AVX512-LABEL: add_ss_mask:1289; X86-AVX512: # %bb.0:1290; X86-AVX512-NEXT: movzbl {{[0-9]+}}(%esp), %eax1291; X86-AVX512-NEXT: kmovw %eax, %k11292; X86-AVX512-NEXT: vaddss %xmm1, %xmm0, %xmm2 {%k1}1293; X86-AVX512-NEXT: vmovaps %xmm2, %xmm01294; X86-AVX512-NEXT: retl1295;1296; X64-SSE-LABEL: add_ss_mask:1297; X64-SSE: # %bb.0:1298; X64-SSE-NEXT: testb $1, %dil1299; X64-SSE-NEXT: jne .LBB70_11300; X64-SSE-NEXT: # %bb.2:1301; X64-SSE-NEXT: movss {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3]1302; X64-SSE-NEXT: retq1303; X64-SSE-NEXT: .LBB70_1:1304; X64-SSE-NEXT: addss %xmm0, %xmm11305; X64-SSE-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]1306; X64-SSE-NEXT: retq1307;1308; X64-AVX1-LABEL: add_ss_mask:1309; X64-AVX1: # %bb.0:1310; X64-AVX1-NEXT: testb $1, %dil1311; X64-AVX1-NEXT: je .LBB70_21312; X64-AVX1-NEXT: # %bb.1:1313; X64-AVX1-NEXT: vaddss %xmm1, %xmm0, %xmm21314; X64-AVX1-NEXT: .LBB70_2:1315; X64-AVX1-NEXT: vmovss {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3]1316; X64-AVX1-NEXT: retq1317;1318; X64-AVX512-LABEL: add_ss_mask:1319; X64-AVX512: # %bb.0:1320; X64-AVX512-NEXT: kmovw %edi, %k11321; X64-AVX512-NEXT: vaddss %xmm1, %xmm0, %xmm2 {%k1}1322; X64-AVX512-NEXT: vmovaps %xmm2, %xmm01323; X64-AVX512-NEXT: retq1324 %1 = extractelement <4 x float> %a, i64 01325 %2 = extractelement <4 x float> %b, i64 01326 %3 = fadd float %1, %21327 %4 = extractelement <4 x float> %c, i32 01328 %5 = bitcast i8 %mask to <8 x i1>1329 %6 = extractelement <8 x i1> %5, i64 01330 %7 = select i1 %6, float %3, float %41331 %8 = insertelement <4 x float> %a, float %7, i64 01332 ret <4 x float> %81333}1334 1335define <2 x double> @add_sd_mask(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {1336; X86-SSE-LABEL: add_sd_mask:1337; X86-SSE: # %bb.0:1338; X86-SSE-NEXT: testb $1, {{[0-9]+}}(%esp)1339; X86-SSE-NEXT: jne .LBB71_11340; X86-SSE-NEXT: # %bb.2:1341; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1]1342; X86-SSE-NEXT: retl1343; X86-SSE-NEXT: .LBB71_1:1344; X86-SSE-NEXT: addsd %xmm0, %xmm11345; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]1346; X86-SSE-NEXT: retl1347;1348; X86-AVX1-LABEL: add_sd_mask:1349; X86-AVX1: # %bb.0:1350; X86-AVX1-NEXT: testb $1, {{[0-9]+}}(%esp)1351; X86-AVX1-NEXT: je .LBB71_21352; X86-AVX1-NEXT: # %bb.1:1353; X86-AVX1-NEXT: vaddsd %xmm1, %xmm0, %xmm21354; X86-AVX1-NEXT: .LBB71_2:1355; X86-AVX1-NEXT: vmovsd {{.*#+}} xmm0 = xmm2[0],xmm0[1]1356; X86-AVX1-NEXT: retl1357;1358; X86-AVX512-LABEL: add_sd_mask:1359; X86-AVX512: # %bb.0:1360; X86-AVX512-NEXT: movzbl {{[0-9]+}}(%esp), %eax1361; X86-AVX512-NEXT: kmovw %eax, %k11362; X86-AVX512-NEXT: vaddsd %xmm1, %xmm0, %xmm2 {%k1}1363; X86-AVX512-NEXT: vmovapd %xmm2, %xmm01364; X86-AVX512-NEXT: retl1365;1366; X64-SSE-LABEL: add_sd_mask:1367; X64-SSE: # %bb.0:1368; X64-SSE-NEXT: testb $1, %dil1369; X64-SSE-NEXT: jne .LBB71_11370; X64-SSE-NEXT: # %bb.2:1371; X64-SSE-NEXT: movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1]1372; X64-SSE-NEXT: retq1373; X64-SSE-NEXT: .LBB71_1:1374; X64-SSE-NEXT: addsd %xmm0, %xmm11375; X64-SSE-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]1376; X64-SSE-NEXT: retq1377;1378; X64-AVX1-LABEL: add_sd_mask:1379; X64-AVX1: # %bb.0:1380; X64-AVX1-NEXT: testb $1, %dil1381; X64-AVX1-NEXT: je .LBB71_21382; X64-AVX1-NEXT: # %bb.1:1383; X64-AVX1-NEXT: vaddsd %xmm1, %xmm0, %xmm21384; X64-AVX1-NEXT: .LBB71_2:1385; X64-AVX1-NEXT: vmovsd {{.*#+}} xmm0 = xmm2[0],xmm0[1]1386; X64-AVX1-NEXT: retq1387;1388; X64-AVX512-LABEL: add_sd_mask:1389; X64-AVX512: # %bb.0:1390; X64-AVX512-NEXT: kmovw %edi, %k11391; X64-AVX512-NEXT: vaddsd %xmm1, %xmm0, %xmm2 {%k1}1392; X64-AVX512-NEXT: vmovapd %xmm2, %xmm01393; X64-AVX512-NEXT: retq1394 %1 = extractelement <2 x double> %a, i64 01395 %2 = extractelement <2 x double> %b, i64 01396 %3 = fadd double %1, %21397 %4 = extractelement <2 x double> %c, i32 01398 %5 = bitcast i8 %mask to <8 x i1>1399 %6 = extractelement <8 x i1> %5, i64 01400 %7 = select i1 %6, double %3, double %41401 %8 = insertelement <2 x double> %a, double %7, i64 01402 ret <2 x double> %81403}1404 1405define float @PR26515(<4 x float> %0) nounwind {1406; X86-SSE-LABEL: PR26515:1407; X86-SSE: # %bb.0:1408; X86-SSE-NEXT: pushl %eax1409; X86-SSE-NEXT: movaps %xmm0, %xmm11410; X86-SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]1411; X86-SSE-NEXT: addss %xmm0, %xmm11412; X86-SSE-NEXT: movss %xmm1, (%esp)1413; X86-SSE-NEXT: flds (%esp)1414; X86-SSE-NEXT: popl %eax1415; X86-SSE-NEXT: retl1416;1417; X86-AVX-LABEL: PR26515:1418; X86-AVX: # %bb.0:1419; X86-AVX-NEXT: pushl %eax1420; X86-AVX-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]1421; X86-AVX-NEXT: vaddss %xmm0, %xmm1, %xmm01422; X86-AVX-NEXT: vmovss %xmm0, (%esp)1423; X86-AVX-NEXT: flds (%esp)1424; X86-AVX-NEXT: popl %eax1425; X86-AVX-NEXT: retl1426;1427; X64-SSE-LABEL: PR26515:1428; X64-SSE: # %bb.0:1429; X64-SSE-NEXT: movaps %xmm0, %xmm11430; X64-SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]1431; X64-SSE-NEXT: addss %xmm1, %xmm01432; X64-SSE-NEXT: retq1433;1434; X64-AVX-LABEL: PR26515:1435; X64-AVX: # %bb.0:1436; X64-AVX-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]1437; X64-AVX-NEXT: vaddss %xmm0, %xmm1, %xmm01438; X64-AVX-NEXT: retq1439 %2 = shufflevector <4 x float> %0, <4 x float> poison, <4 x i32> <i32 2, i32 undef, i32 undef, i32 undef>1440 %3 = fadd <4 x float> %2, %01441 %4 = extractelement <4 x float> %3, i64 01442 ret float %41443}1444