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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=i686-unknown -mattr=-sse2,+sse | FileCheck %s --check-prefix=X863; RUN: llc < %s -mtriple=x86_64-unknown -mattr=-sse2,+sse | FileCheck %s --check-prefix=X644 5define float @f32_pos(float %a, float %b) nounwind {6; X86-LABEL: f32_pos:7; X86: # %bb.0:8; X86-NEXT: pushl %eax9; X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero10; X86-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm011; X86-NEXT: movss %xmm0, (%esp)12; X86-NEXT: flds (%esp)13; X86-NEXT: popl %eax14; X86-NEXT: retl15;16; X64-LABEL: f32_pos:17; X64: # %bb.0:18; X64-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm019; X64-NEXT: retq20 %tmp = tail call float @llvm.copysign.f32(float %a, float 1.0)21 ret float %tmp22}23 24define float @f32_neg(float %a, float %b) nounwind {25; X86-LABEL: f32_neg:26; X86: # %bb.0:27; X86-NEXT: pushl %eax28; X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero29; X86-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm030; X86-NEXT: movss %xmm0, (%esp)31; X86-NEXT: flds (%esp)32; X86-NEXT: popl %eax33; X86-NEXT: retl34;35; X64-LABEL: f32_neg:36; X64: # %bb.0:37; X64-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm038; X64-NEXT: retq39 %tmp = tail call float @llvm.copysign.f32(float %a, float -1.0)40 ret float %tmp41}42 43define <4 x float> @v4f32_pos(<4 x float> %a, <4 x float> %b) nounwind {44; X86-LABEL: v4f32_pos:45; X86: # %bb.0:46; X86-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm047; X86-NEXT: retl48;49; X64-LABEL: v4f32_pos:50; X64: # %bb.0:51; X64-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm052; X64-NEXT: retq53 %tmp = tail call <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>)54 ret <4 x float> %tmp55}56 57define <4 x float> @v4f32_neg(<4 x float> %a, <4 x float> %b) nounwind {58; X86-LABEL: v4f32_neg:59; X86: # %bb.0:60; X86-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm061; X86-NEXT: retl62;63; X64-LABEL: v4f32_neg:64; X64: # %bb.0:65; X64-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm066; X64-NEXT: retq67 %tmp = tail call <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> <float -1.0, float -1.0, float -1.0, float -1.0>)68 ret <4 x float> %tmp69}70 71define <4 x float> @v4f32_const_mag(<4 x float> %a, <4 x float> %b) nounwind {72; X86-LABEL: v4f32_const_mag:73; X86: # %bb.0:74; X86-NEXT: movaps %xmm1, %xmm075; X86-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm076; X86-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm077; X86-NEXT: retl78;79; X64-LABEL: v4f32_const_mag:80; X64: # %bb.0:81; X64-NEXT: movaps %xmm1, %xmm082; X64-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm083; X64-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm084; X64-NEXT: retq85 %tmp = tail call <4 x float> @llvm.copysign.v4f32(<4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, <4 x float> %b )86 ret <4 x float> %tmp87}88 89declare float @llvm.copysign.f32(float, float)90declare <4 x float> @llvm.copysign.v4f32(<4 x float>, <4 x float>)91