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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE413; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+avx2 | FileCheck %s --check-prefix=AVX4; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+avx512vl,avx512bw | FileCheck %s --check-prefix=AVX5 6define <8 x i16> @test_llvm_x86_sse41_pmovsxbw(ptr %a) {7; SSE41-LABEL: test_llvm_x86_sse41_pmovsxbw:8; SSE41: ## %bb.0:9; SSE41-NEXT: pmovsxbw (%rdi), %xmm010; SSE41-NEXT: retq11;12; AVX-LABEL: test_llvm_x86_sse41_pmovsxbw:13; AVX: ## %bb.0:14; AVX-NEXT: vpmovsxbw (%rdi), %xmm015; AVX-NEXT: retq16 %1 = load <16 x i8>, ptr %a, align 117 %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>18 %3 = sext <8 x i8> %2 to <8 x i16>19 ret <8 x i16> %320}21 22define <4 x i32> @test_llvm_x86_sse41_pmovsxbd(ptr %a) {23; SSE41-LABEL: test_llvm_x86_sse41_pmovsxbd:24; SSE41: ## %bb.0:25; SSE41-NEXT: pmovsxbd (%rdi), %xmm026; SSE41-NEXT: retq27;28; AVX-LABEL: test_llvm_x86_sse41_pmovsxbd:29; AVX: ## %bb.0:30; AVX-NEXT: vpmovsxbd (%rdi), %xmm031; AVX-NEXT: retq32 %1 = load <16 x i8>, ptr %a, align 133 %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>34 %3 = sext <4 x i8> %2 to <4 x i32>35 ret <4 x i32> %336}37 38define <2 x i64> @test_llvm_x86_sse41_pmovsxbq(ptr %a) {39; SSE41-LABEL: test_llvm_x86_sse41_pmovsxbq:40; SSE41: ## %bb.0:41; SSE41-NEXT: pmovsxbq (%rdi), %xmm042; SSE41-NEXT: retq43;44; AVX-LABEL: test_llvm_x86_sse41_pmovsxbq:45; AVX: ## %bb.0:46; AVX-NEXT: vpmovsxbq (%rdi), %xmm047; AVX-NEXT: retq48 %1 = load <16 x i8>, ptr %a, align 149 %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <2 x i32> <i32 0, i32 1>50 %3 = sext <2 x i8> %2 to <2 x i64>51 ret <2 x i64> %352}53 54define <4 x i32> @test_llvm_x86_sse41_pmovsxwd(ptr %a) {55; SSE41-LABEL: test_llvm_x86_sse41_pmovsxwd:56; SSE41: ## %bb.0:57; SSE41-NEXT: pmovsxwd (%rdi), %xmm058; SSE41-NEXT: retq59;60; AVX-LABEL: test_llvm_x86_sse41_pmovsxwd:61; AVX: ## %bb.0:62; AVX-NEXT: vpmovsxwd (%rdi), %xmm063; AVX-NEXT: retq64 %1 = load <8 x i16>, ptr %a, align 165 %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>66 %3 = sext <4 x i16> %2 to <4 x i32>67 ret <4 x i32> %368}69 70define <2 x i64> @test_llvm_x86_sse41_pmovsxwq(ptr %a) {71; SSE41-LABEL: test_llvm_x86_sse41_pmovsxwq:72; SSE41: ## %bb.0:73; SSE41-NEXT: pmovsxwq (%rdi), %xmm074; SSE41-NEXT: retq75;76; AVX-LABEL: test_llvm_x86_sse41_pmovsxwq:77; AVX: ## %bb.0:78; AVX-NEXT: vpmovsxwq (%rdi), %xmm079; AVX-NEXT: retq80 %1 = load <8 x i16>, ptr %a, align 181 %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <2 x i32> <i32 0, i32 1>82 %3 = sext <2 x i16> %2 to <2 x i64>83 ret <2 x i64> %384}85 86define <2 x i64> @test_llvm_x86_sse41_pmovsxdq(ptr %a) {87; SSE41-LABEL: test_llvm_x86_sse41_pmovsxdq:88; SSE41: ## %bb.0:89; SSE41-NEXT: pmovsxdq (%rdi), %xmm090; SSE41-NEXT: retq91;92; AVX-LABEL: test_llvm_x86_sse41_pmovsxdq:93; AVX: ## %bb.0:94; AVX-NEXT: vpmovsxdq (%rdi), %xmm095; AVX-NEXT: retq96 %1 = load <4 x i32>, ptr %a, align 197 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <2 x i32> <i32 0, i32 1>98 %3 = sext <2 x i32> %2 to <2 x i64>99 ret <2 x i64> %3100}101 102define <8 x i16> @test_llvm_x86_sse41_pmovzxbw(ptr %a) {103; SSE41-LABEL: test_llvm_x86_sse41_pmovzxbw:104; SSE41: ## %bb.0:105; SSE41-NEXT: pmovzxbw {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero106; SSE41-NEXT: retq107;108; AVX-LABEL: test_llvm_x86_sse41_pmovzxbw:109; AVX: ## %bb.0:110; AVX-NEXT: vpmovzxbw {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero111; AVX-NEXT: retq112 %1 = load <16 x i8>, ptr %a, align 1113 %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>114 %3 = zext <8 x i8> %2 to <8 x i16>115 ret <8 x i16> %3116}117 118define <4 x i32> @test_llvm_x86_sse41_pmovzxbd(ptr %a) {119; SSE41-LABEL: test_llvm_x86_sse41_pmovzxbd:120; SSE41: ## %bb.0:121; SSE41-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero122; SSE41-NEXT: retq123;124; AVX-LABEL: test_llvm_x86_sse41_pmovzxbd:125; AVX: ## %bb.0:126; AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero127; AVX-NEXT: retq128 %1 = load <16 x i8>, ptr %a, align 1129 %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>130 %3 = zext <4 x i8> %2 to <4 x i32>131 ret <4 x i32> %3132}133 134define <2 x i64> @test_llvm_x86_sse41_pmovzxbq(ptr %a) {135; SSE41-LABEL: test_llvm_x86_sse41_pmovzxbq:136; SSE41: ## %bb.0:137; SSE41-NEXT: pmovzxbq {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero138; SSE41-NEXT: retq139;140; AVX-LABEL: test_llvm_x86_sse41_pmovzxbq:141; AVX: ## %bb.0:142; AVX-NEXT: vpmovzxbq {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero143; AVX-NEXT: retq144 %1 = load <16 x i8>, ptr %a, align 1145 %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <2 x i32> <i32 0, i32 1>146 %3 = zext <2 x i8> %2 to <2 x i64>147 ret <2 x i64> %3148}149 150define <4 x i32> @test_llvm_x86_sse41_pmovzxwd(ptr %a) {151; SSE41-LABEL: test_llvm_x86_sse41_pmovzxwd:152; SSE41: ## %bb.0:153; SSE41-NEXT: pmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero154; SSE41-NEXT: retq155;156; AVX-LABEL: test_llvm_x86_sse41_pmovzxwd:157; AVX: ## %bb.0:158; AVX-NEXT: vpmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero159; AVX-NEXT: retq160 %1 = load <8 x i16>, ptr %a, align 1161 %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>162 %3 = zext <4 x i16> %2 to <4 x i32>163 ret <4 x i32> %3164}165 166define <2 x i64> @test_llvm_x86_sse41_pmovzxwq(ptr %a) {167; SSE41-LABEL: test_llvm_x86_sse41_pmovzxwq:168; SSE41: ## %bb.0:169; SSE41-NEXT: pmovzxwq {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero170; SSE41-NEXT: retq171;172; AVX-LABEL: test_llvm_x86_sse41_pmovzxwq:173; AVX: ## %bb.0:174; AVX-NEXT: vpmovzxwq {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero175; AVX-NEXT: retq176 %1 = load <8 x i16>, ptr %a, align 1177 %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <2 x i32> <i32 0, i32 1>178 %3 = zext <2 x i16> %2 to <2 x i64>179 ret <2 x i64> %3180}181 182define <2 x i64> @test_llvm_x86_sse41_pmovzxdq(ptr %a) {183; SSE41-LABEL: test_llvm_x86_sse41_pmovzxdq:184; SSE41: ## %bb.0:185; SSE41-NEXT: pmovzxdq {{.*#+}} xmm0 = mem[0],zero,mem[1],zero186; SSE41-NEXT: retq187;188; AVX-LABEL: test_llvm_x86_sse41_pmovzxdq:189; AVX: ## %bb.0:190; AVX-NEXT: vpmovzxdq {{.*#+}} xmm0 = mem[0],zero,mem[1],zero191; AVX-NEXT: retq192 %1 = load <4 x i32>, ptr %a, align 1193 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <2 x i32> <i32 0, i32 1>194 %3 = zext <2 x i32> %2 to <2 x i64>195 ret <2 x i64> %3196}197