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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -O3 -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+lwp < %s | FileCheck %s3 4target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"5target triple = "x86_64-unknown-unknown"6 7; Stack reload folding tests.8;9; By including a nop call with sideeffects we can force a partial register spill of the10; relevant registers and check that the reload is correctly folded into the instruction.11 12define i8 @stack_fold_lwpins_u32(i32 %a0, i32 %a1) {13; CHECK-LABEL: stack_fold_lwpins_u32:14; CHECK: # %bb.0:15; CHECK-NEXT: pushq %rbp16; CHECK-NEXT: .cfi_def_cfa_offset 1617; CHECK-NEXT: pushq %r1518; CHECK-NEXT: .cfi_def_cfa_offset 2419; CHECK-NEXT: pushq %r1420; CHECK-NEXT: .cfi_def_cfa_offset 3221; CHECK-NEXT: pushq %r1322; CHECK-NEXT: .cfi_def_cfa_offset 4023; CHECK-NEXT: pushq %r1224; CHECK-NEXT: .cfi_def_cfa_offset 4825; CHECK-NEXT: pushq %rbx26; CHECK-NEXT: .cfi_def_cfa_offset 5627; CHECK-NEXT: .cfi_offset %rbx, -5628; CHECK-NEXT: .cfi_offset %r12, -4829; CHECK-NEXT: .cfi_offset %r13, -4030; CHECK-NEXT: .cfi_offset %r14, -3231; CHECK-NEXT: .cfi_offset %r15, -2432; CHECK-NEXT: .cfi_offset %rbp, -1633; CHECK-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill34; CHECK-NEXT: movl %edi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill35; CHECK-NEXT: #APP36; CHECK-NEXT: nop37; CHECK-NEXT: #NO_APP38; CHECK-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload39; CHECK-NEXT: lwpins $2814, {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Folded Reload40; CHECK-NEXT: # imm = 0xAFE41; CHECK-NEXT: setb %al42; CHECK-NEXT: popq %rbx43; CHECK-NEXT: .cfi_def_cfa_offset 4844; CHECK-NEXT: popq %r1245; CHECK-NEXT: .cfi_def_cfa_offset 4046; CHECK-NEXT: popq %r1347; CHECK-NEXT: .cfi_def_cfa_offset 3248; CHECK-NEXT: popq %r1449; CHECK-NEXT: .cfi_def_cfa_offset 2450; CHECK-NEXT: popq %r1551; CHECK-NEXT: .cfi_def_cfa_offset 1652; CHECK-NEXT: popq %rbp53; CHECK-NEXT: .cfi_def_cfa_offset 854; CHECK-NEXT: retq55 %1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()56 %2 = tail call i8 @llvm.x86.lwpins32(i32 %a0, i32 %a1, i32 2814)57 ret i8 %258}59declare i8 @llvm.x86.lwpins32(i32, i32, i32)60 61define i8 @stack_fold_lwpins_u64(i64 %a0, i32 %a1) {62; CHECK-LABEL: stack_fold_lwpins_u64:63; CHECK: # %bb.0:64; CHECK-NEXT: pushq %rbp65; CHECK-NEXT: .cfi_def_cfa_offset 1666; CHECK-NEXT: pushq %r1567; CHECK-NEXT: .cfi_def_cfa_offset 2468; CHECK-NEXT: pushq %r1469; CHECK-NEXT: .cfi_def_cfa_offset 3270; CHECK-NEXT: pushq %r1371; CHECK-NEXT: .cfi_def_cfa_offset 4072; CHECK-NEXT: pushq %r1273; CHECK-NEXT: .cfi_def_cfa_offset 4874; CHECK-NEXT: pushq %rbx75; CHECK-NEXT: .cfi_def_cfa_offset 5676; CHECK-NEXT: .cfi_offset %rbx, -5677; CHECK-NEXT: .cfi_offset %r12, -4878; CHECK-NEXT: .cfi_offset %r13, -4079; CHECK-NEXT: .cfi_offset %r14, -3280; CHECK-NEXT: .cfi_offset %r15, -2481; CHECK-NEXT: .cfi_offset %rbp, -1682; CHECK-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill83; CHECK-NEXT: movq %rdi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill84; CHECK-NEXT: #APP85; CHECK-NEXT: nop86; CHECK-NEXT: #NO_APP87; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload88; CHECK-NEXT: lwpins $2814, {{[-0-9]+}}(%r{{[sb]}}p), %rax # 4-byte Folded Reload89; CHECK-NEXT: # imm = 0xAFE90; CHECK-NEXT: setb %al91; CHECK-NEXT: popq %rbx92; CHECK-NEXT: .cfi_def_cfa_offset 4893; CHECK-NEXT: popq %r1294; CHECK-NEXT: .cfi_def_cfa_offset 4095; CHECK-NEXT: popq %r1396; CHECK-NEXT: .cfi_def_cfa_offset 3297; CHECK-NEXT: popq %r1498; CHECK-NEXT: .cfi_def_cfa_offset 2499; CHECK-NEXT: popq %r15100; CHECK-NEXT: .cfi_def_cfa_offset 16101; CHECK-NEXT: popq %rbp102; CHECK-NEXT: .cfi_def_cfa_offset 8103; CHECK-NEXT: retq104 %1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()105 %2 = tail call i8 @llvm.x86.lwpins64(i64 %a0, i32 %a1, i32 2814)106 ret i8 %2107}108declare i8 @llvm.x86.lwpins64(i64, i32, i32)109 110define void @stack_fold_lwpval_u32(i32 %a0, i32 %a1) {111; CHECK-LABEL: stack_fold_lwpval_u32:112; CHECK: # %bb.0:113; CHECK-NEXT: pushq %rbp114; CHECK-NEXT: .cfi_def_cfa_offset 16115; CHECK-NEXT: pushq %r15116; CHECK-NEXT: .cfi_def_cfa_offset 24117; CHECK-NEXT: pushq %r14118; CHECK-NEXT: .cfi_def_cfa_offset 32119; CHECK-NEXT: pushq %r13120; CHECK-NEXT: .cfi_def_cfa_offset 40121; CHECK-NEXT: pushq %r12122; CHECK-NEXT: .cfi_def_cfa_offset 48123; CHECK-NEXT: pushq %rbx124; CHECK-NEXT: .cfi_def_cfa_offset 56125; CHECK-NEXT: .cfi_offset %rbx, -56126; CHECK-NEXT: .cfi_offset %r12, -48127; CHECK-NEXT: .cfi_offset %r13, -40128; CHECK-NEXT: .cfi_offset %r14, -32129; CHECK-NEXT: .cfi_offset %r15, -24130; CHECK-NEXT: .cfi_offset %rbp, -16131; CHECK-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill132; CHECK-NEXT: movl %edi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill133; CHECK-NEXT: #APP134; CHECK-NEXT: nop135; CHECK-NEXT: #NO_APP136; CHECK-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload137; CHECK-NEXT: lwpval $2814, {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Folded Reload138; CHECK-NEXT: # imm = 0xAFE139; CHECK-NEXT: popq %rbx140; CHECK-NEXT: .cfi_def_cfa_offset 48141; CHECK-NEXT: popq %r12142; CHECK-NEXT: .cfi_def_cfa_offset 40143; CHECK-NEXT: popq %r13144; CHECK-NEXT: .cfi_def_cfa_offset 32145; CHECK-NEXT: popq %r14146; CHECK-NEXT: .cfi_def_cfa_offset 24147; CHECK-NEXT: popq %r15148; CHECK-NEXT: .cfi_def_cfa_offset 16149; CHECK-NEXT: popq %rbp150; CHECK-NEXT: .cfi_def_cfa_offset 8151; CHECK-NEXT: retq152 %1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()153 tail call void @llvm.x86.lwpval32(i32 %a0, i32 %a1, i32 2814)154 ret void155}156declare void @llvm.x86.lwpval32(i32, i32, i32)157 158define void @stack_fold_lwpval_u64(i64 %a0, i32 %a1) {159; CHECK-LABEL: stack_fold_lwpval_u64:160; CHECK: # %bb.0:161; CHECK-NEXT: pushq %rbp162; CHECK-NEXT: .cfi_def_cfa_offset 16163; CHECK-NEXT: pushq %r15164; CHECK-NEXT: .cfi_def_cfa_offset 24165; CHECK-NEXT: pushq %r14166; CHECK-NEXT: .cfi_def_cfa_offset 32167; CHECK-NEXT: pushq %r13168; CHECK-NEXT: .cfi_def_cfa_offset 40169; CHECK-NEXT: pushq %r12170; CHECK-NEXT: .cfi_def_cfa_offset 48171; CHECK-NEXT: pushq %rbx172; CHECK-NEXT: .cfi_def_cfa_offset 56173; CHECK-NEXT: .cfi_offset %rbx, -56174; CHECK-NEXT: .cfi_offset %r12, -48175; CHECK-NEXT: .cfi_offset %r13, -40176; CHECK-NEXT: .cfi_offset %r14, -32177; CHECK-NEXT: .cfi_offset %r15, -24178; CHECK-NEXT: .cfi_offset %rbp, -16179; CHECK-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill180; CHECK-NEXT: movq %rdi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill181; CHECK-NEXT: #APP182; CHECK-NEXT: nop183; CHECK-NEXT: #NO_APP184; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload185; CHECK-NEXT: lwpval $2814, {{[-0-9]+}}(%r{{[sb]}}p), %rax # 4-byte Folded Reload186; CHECK-NEXT: # imm = 0xAFE187; CHECK-NEXT: popq %rbx188; CHECK-NEXT: .cfi_def_cfa_offset 48189; CHECK-NEXT: popq %r12190; CHECK-NEXT: .cfi_def_cfa_offset 40191; CHECK-NEXT: popq %r13192; CHECK-NEXT: .cfi_def_cfa_offset 32193; CHECK-NEXT: popq %r14194; CHECK-NEXT: .cfi_def_cfa_offset 24195; CHECK-NEXT: popq %r15196; CHECK-NEXT: .cfi_def_cfa_offset 16197; CHECK-NEXT: popq %rbp198; CHECK-NEXT: .cfi_def_cfa_offset 8199; CHECK-NEXT: retq200 %1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()201 tail call void @llvm.x86.lwpval64(i64 %a0, i32 %a1, i32 2814)202 ret void203}204declare void @llvm.x86.lwpval64(i64, i32, i32)205