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1; RUN: llc < %s -mcpu=generic -mtriple=x86_64-linux | FileCheck %s2 3; FIXME: Win64 does not support byval.4 5; Expect the entry point.6; CHECK-LABEL: tailcaller:7 8; Expect 2 rep;movs because of tail call byval lowering.9; CHECK: rep;10; CHECK: rep;11 12; A sequence of copyto/copyfrom virtual registers is used to deal with byval13; lowering appearing after moving arguments to registers. The following two14; checks verify that the register allocator changes those sequences to direct15; moves to argument register where it can (for registers that are not used in16; byval lowering - not rsi, not rdi, not rcx).17; Expect argument 4 to be moved directly to register edx.18; CHECK: movl $7, %edx19 20; Expect argument 6 to be moved directly to register r8.21; CHECK: movl $17, %r8d22 23; Expect not call but jmp to @tailcallee.24; CHECK: jmp tailcallee25 26; Expect the trailer.27; CHECK: .size tailcaller28 29%struct.s = type { i64, i64, i64, i64, i64, i64, i64, i64,30 i64, i64, i64, i64, i64, i64, i64, i64,31 i64, i64, i64, i64, i64, i64, i64, i64 }32 33declare tailcc i64 @tailcallee(ptr byval(%struct.s) %a, i64 %val, i64 %val2, i64 %val3, i64 %val4, i64 %val5)34 35 36define tailcc i64 @tailcaller(i64 %b, ptr byval(%struct.s) %a) {37entry:38 %tmp2 = getelementptr %struct.s, ptr %a, i32 0, i32 139 %tmp3 = load i64, ptr %tmp2, align 840 %tmp4 = tail call tailcc i64 @tailcallee(ptr byval(%struct.s) %a , i64 %tmp3, i64 %b, i64 7, i64 13, i64 17)41 ret i64 %tmp442}43