94 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE23; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE414 5; A single 16-bit load + a single 16-bit store6define void @load_2_i8(ptr %A) {7; SSE2-LABEL: load_2_i8:8; SSE2: # %bb.0:9; SSE2-NEXT: movzwl (%rdi), %eax10; SSE2-NEXT: movd %eax, %xmm011; SSE2-NEXT: paddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm012; SSE2-NEXT: movd %xmm0, %eax13; SSE2-NEXT: movw %ax, (%rdi)14; SSE2-NEXT: retq15;16; SSE41-LABEL: load_2_i8:17; SSE41: # %bb.0:18; SSE41-NEXT: movzwl (%rdi), %eax19; SSE41-NEXT: movd %eax, %xmm020; SSE41-NEXT: paddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm021; SSE41-NEXT: pextrw $0, %xmm0, (%rdi)22; SSE41-NEXT: retq23 %T = load <2 x i8>, ptr %A24 %G = add <2 x i8> %T, <i8 9, i8 7>25 store <2 x i8> %G, ptr %A26 ret void27}28 29; Read 32-bits30define void @load_2_i16(ptr %A) {31; CHECK-LABEL: load_2_i16:32; CHECK: # %bb.0:33; CHECK-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero34; CHECK-NEXT: paddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm035; CHECK-NEXT: movd %xmm0, (%rdi)36; CHECK-NEXT: retq37 %T = load <2 x i16>, ptr %A38 %G = add <2 x i16> %T, <i16 9, i16 7>39 store <2 x i16> %G, ptr %A40 ret void41}42 43define void @load_2_i32(ptr %A) {44; CHECK-LABEL: load_2_i32:45; CHECK: # %bb.0:46; CHECK-NEXT: movq {{.*#+}} xmm0 = mem[0],zero47; CHECK-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm048; CHECK-NEXT: movq %xmm0, (%rdi)49; CHECK-NEXT: retq50 %T = load <2 x i32>, ptr %A51 %G = add <2 x i32> %T, <i32 9, i32 7>52 store <2 x i32> %G, ptr %A53 ret void54}55 56define void @load_4_i8(ptr %A) {57; CHECK-LABEL: load_4_i8:58; CHECK: # %bb.0:59; CHECK-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero60; CHECK-NEXT: paddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm061; CHECK-NEXT: movd %xmm0, (%rdi)62; CHECK-NEXT: retq63 %T = load <4 x i8>, ptr %A64 %G = add <4 x i8> %T, <i8 1, i8 4, i8 9, i8 7>65 store <4 x i8> %G, ptr %A66 ret void67}68 69define void @load_4_i16(ptr %A) {70; CHECK-LABEL: load_4_i16:71; CHECK: # %bb.0:72; CHECK-NEXT: movq {{.*#+}} xmm0 = mem[0],zero73; CHECK-NEXT: paddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm074; CHECK-NEXT: movq %xmm0, (%rdi)75; CHECK-NEXT: retq76 %T = load <4 x i16>, ptr %A77 %G = add <4 x i16> %T, <i16 1, i16 4, i16 9, i16 7>78 store <4 x i16> %G, ptr %A79 ret void80}81 82define void @load_8_i8(ptr %A) {83; CHECK-LABEL: load_8_i8:84; CHECK: # %bb.0:85; CHECK-NEXT: movq {{.*#+}} xmm0 = mem[0],zero86; CHECK-NEXT: paddb %xmm0, %xmm087; CHECK-NEXT: movq %xmm0, (%rdi)88; CHECK-NEXT: retq89 %T = load <8 x i8>, ptr %A90 %G = add <8 x i8> %T, %T91 store <8 x i8> %G, ptr %A92 ret void93}94