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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=skylake-avx512 -mattr=prefer-256-bit | FileCheck %s3 4define void @test(ptr %a0) #0 {5; CHECK-LABEL: test:6; CHECK: # %bb.0:7; CHECK-NEXT: vmovdqu (%rdi), %ymm08; CHECK-NEXT: vmovq {{.*#+}} xmm1 = [0,4,0,0]9; CHECK-NEXT: vpblendd {{.*#+}} ymm0 = mem[0],ymm0[1,2,3,4,5,6,7]10; CHECK-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,u,u,u,u,u,u,u,u,u,u,u,u,u,u,16,20,u,u,u,u,u,u,u,u,u,u,u,u,u,u]11; CHECK-NEXT: vpermd %ymm0, %ymm1, %ymm012; CHECK-NEXT: vpternlogq {{.*#+}} xmm0 = ~xmm013; CHECK-NEXT: vpextrb $1, %xmm0, (%rax)14; CHECK-NEXT: vpextrb $4, %xmm0, (%rax)15; CHECK-NEXT: vpextrb $8, %xmm0, (%rax)16; CHECK-NEXT: vzeroupper17; CHECK-NEXT: retq18 %load = load <64 x i8>, ptr %a0, align 119 %shuf = shufflevector <64 x i8> %load, <64 x i8> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28, i32 32, i32 36, i32 40, i32 44, i32 48, i32 52, i32 56, i32 60>20 %xor = xor <16 x i8> %shuf, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>21 %i1 = extractelement <16 x i8> %xor, i32 122 %i2 = extractelement <16 x i8> %xor, i32 423 %i3 = extractelement <16 x i8> %xor, i32 824 store i8 %i1, ptr undef, align 125 store i8 %i2, ptr undef, align 126 store i8 %i3, ptr undef, align 127 ret void28}29 30attributes #0 = { "min-legal-vector-width"="0" "target-cpu"="skylake-avx512" }31