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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X86-SSE3; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx | FileCheck %s --check-prefix=X86-AVX4; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64-SSE5; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=X64-AVX6 7;PR290798 9define <4 x float> @mask_ucvt_4i32_4f32(<4 x i32> %a) {10; X86-SSE-LABEL: mask_ucvt_4i32_4f32:11; X86-SSE: # %bb.0:12; X86-SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm013; X86-SSE-NEXT: cvtdq2ps %xmm0, %xmm014; X86-SSE-NEXT: retl15;16; X86-AVX-LABEL: mask_ucvt_4i32_4f32:17; X86-AVX: # %bb.0:18; X86-AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm019; X86-AVX-NEXT: vcvtdq2ps %xmm0, %xmm020; X86-AVX-NEXT: retl21;22; X64-SSE-LABEL: mask_ucvt_4i32_4f32:23; X64-SSE: # %bb.0:24; X64-SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm025; X64-SSE-NEXT: cvtdq2ps %xmm0, %xmm026; X64-SSE-NEXT: retq27;28; X64-AVX-LABEL: mask_ucvt_4i32_4f32:29; X64-AVX: # %bb.0:30; X64-AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm031; X64-AVX-NEXT: vcvtdq2ps %xmm0, %xmm032; X64-AVX-NEXT: retq33 %and = and <4 x i32> %a, <i32 127, i32 255, i32 4095, i32 65595>34 %cvt = uitofp <4 x i32> %and to <4 x float>35 ret <4 x float> %cvt36}37 38define <4 x double> @mask_ucvt_4i32_4f64(<4 x i32> %a) {39; X86-SSE-LABEL: mask_ucvt_4i32_4f64:40; X86-SSE: # %bb.0:41; X86-SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm042; X86-SSE-NEXT: cvtdq2pd %xmm0, %xmm243; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]44; X86-SSE-NEXT: cvtdq2pd %xmm0, %xmm145; X86-SSE-NEXT: movaps %xmm2, %xmm046; X86-SSE-NEXT: retl47;48; X86-AVX-LABEL: mask_ucvt_4i32_4f64:49; X86-AVX: # %bb.0:50; X86-AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm051; X86-AVX-NEXT: vcvtdq2pd %xmm0, %ymm052; X86-AVX-NEXT: retl53;54; X64-SSE-LABEL: mask_ucvt_4i32_4f64:55; X64-SSE: # %bb.0:56; X64-SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm057; X64-SSE-NEXT: cvtdq2pd %xmm0, %xmm258; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]59; X64-SSE-NEXT: cvtdq2pd %xmm0, %xmm160; X64-SSE-NEXT: movaps %xmm2, %xmm061; X64-SSE-NEXT: retq62;63; X64-AVX-LABEL: mask_ucvt_4i32_4f64:64; X64-AVX: # %bb.0:65; X64-AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm066; X64-AVX-NEXT: vcvtdq2pd %xmm0, %ymm067; X64-AVX-NEXT: retq68 %and = and <4 x i32> %a, <i32 127, i32 255, i32 4095, i32 65595>69 %cvt = uitofp <4 x i32> %and to <4 x double>70 ret <4 x double> %cvt71}72 73; Regression noticed in D5638774define <4 x float> @lshr_truncate_mask_ucvt_4i64_4f32(ptr%p0) {75; X86-SSE-LABEL: lshr_truncate_mask_ucvt_4i64_4f32:76; X86-SSE: # %bb.0:77; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax78; X86-SSE-NEXT: movups (%eax), %xmm079; X86-SSE-NEXT: movups 16(%eax), %xmm180; X86-SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]81; X86-SSE-NEXT: psrld $16, %xmm082; X86-SSE-NEXT: cvtdq2ps %xmm0, %xmm083; X86-SSE-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm084; X86-SSE-NEXT: retl85;86; X86-AVX-LABEL: lshr_truncate_mask_ucvt_4i64_4f32:87; X86-AVX: # %bb.0:88; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax89; X86-AVX-NEXT: vmovups (%eax), %xmm090; X86-AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],mem[0,2]91; X86-AVX-NEXT: vpsrld $16, %xmm0, %xmm092; X86-AVX-NEXT: vcvtdq2ps %xmm0, %xmm093; X86-AVX-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm094; X86-AVX-NEXT: retl95;96; X64-SSE-LABEL: lshr_truncate_mask_ucvt_4i64_4f32:97; X64-SSE: # %bb.0:98; X64-SSE-NEXT: movups (%rdi), %xmm099; X64-SSE-NEXT: movups 16(%rdi), %xmm1100; X64-SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]101; X64-SSE-NEXT: psrld $16, %xmm0102; X64-SSE-NEXT: cvtdq2ps %xmm0, %xmm0103; X64-SSE-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0104; X64-SSE-NEXT: retq105;106; X64-AVX-LABEL: lshr_truncate_mask_ucvt_4i64_4f32:107; X64-AVX: # %bb.0:108; X64-AVX-NEXT: vmovups (%rdi), %xmm0109; X64-AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],mem[0,2]110; X64-AVX-NEXT: vpsrld $16, %xmm0, %xmm0111; X64-AVX-NEXT: vcvtdq2ps %xmm0, %xmm0112; X64-AVX-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0113; X64-AVX-NEXT: retq114 %load = load <4 x i64>, ptr %p0, align 2115 %lshr = lshr <4 x i64> %load, <i64 16, i64 16, i64 16, i64 16>116 %and = and <4 x i64> %lshr, <i64 65535, i64 65535, i64 65535, i64 65535>117 %uitofp = uitofp <4 x i64> %and to <4 x float>118 %fmul = fmul <4 x float> %uitofp, <float 0x3EF0001000000000, float 0x3EF0001000000000, float 0x3EF0001000000000, float 0x3EF0001000000000>119 ret <4 x float> %fmul120}121