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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=i386-apple-darwin8 -mattr=+sse2 | FileCheck %s --check-prefix=X863; RUN: llc < %s -mtriple=x86_64-apple-darwin8 -mattr=+sse2 | FileCheck %s --check-prefix=X644; rdar://60343965 6define void @test(i32 %x, ptr %y) nounwind {7; X86-LABEL: test:8; X86: ## %bb.0: ## %entry9; X86-NEXT: movl {{[0-9]+}}(%esp), %eax10; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx11; X86-NEXT: shrl $23, %ecx12; X86-NEXT: cvtsi2ss %ecx, %xmm013; X86-NEXT: movss %xmm0, (%eax)14; X86-NEXT: retl15;16; X64-LABEL: test:17; X64: ## %bb.0: ## %entry18; X64-NEXT: shrl $23, %edi19; X64-NEXT: cvtsi2ss %edi, %xmm020; X64-NEXT: movss %xmm0, (%rsi)21; X64-NEXT: retq22entry:23 lshr i32 %x, 2324 uitofp i32 %0 to float25 store float %1, ptr %y26 ret void27}28 29define float @test_without_nneg(i32 %x) nounwind {30; X86-LABEL: test_without_nneg:31; X86: ## %bb.0:32; X86-NEXT: pushl %eax33; X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero34; X86-NEXT: orpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm035; X86-NEXT: subsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm036; X86-NEXT: cvtsd2ss %xmm0, %xmm037; X86-NEXT: movss %xmm0, (%esp)38; X86-NEXT: flds (%esp)39; X86-NEXT: popl %eax40; X86-NEXT: retl41;42; X64-LABEL: test_without_nneg:43; X64: ## %bb.0:44; X64-NEXT: movl %edi, %eax45; X64-NEXT: cvtsi2ss %rax, %xmm046; X64-NEXT: retq47 %r = uitofp i32 %x to float48 ret float %r49}50 51define float @test_with_nneg(i32 %x) nounwind {52; X86-LABEL: test_with_nneg:53; X86: ## %bb.0:54; X86-NEXT: pushl %eax55; X86-NEXT: cvtsi2ssl {{[0-9]+}}(%esp), %xmm056; X86-NEXT: movss %xmm0, (%esp)57; X86-NEXT: flds (%esp)58; X86-NEXT: popl %eax59; X86-NEXT: retl60;61; X64-LABEL: test_with_nneg:62; X64: ## %bb.0:63; X64-NEXT: cvtsi2ss %edi, %xmm064; X64-NEXT: retq65 %r = uitofp nneg i32 %x to float66 ret float %r67}68 69define <4 x float> @test_with_nneg_vec(<4 x i32> %x) nounwind {70; X86-LABEL: test_with_nneg_vec:71; X86: ## %bb.0:72; X86-NEXT: cvtdq2ps %xmm0, %xmm073; X86-NEXT: retl74;75; X64-LABEL: test_with_nneg_vec:76; X64: ## %bb.0:77; X64-NEXT: cvtdq2ps %xmm0, %xmm078; X64-NEXT: retq79 %r = uitofp nneg <4 x i32> %x to <4 x float>80 ret <4 x float> %r81}82