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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s3 4define i32 @add_undef_rhs(i32 %x) {5; CHECK-LABEL: add_undef_rhs:6; CHECK: # %bb.0:7; CHECK-NEXT: retq8 %r = add i32 %x, undef9 ret i32 %r10}11 12define <4 x i32> @add_undef_rhs_vec(<4 x i32> %x) {13; CHECK-LABEL: add_undef_rhs_vec:14; CHECK: # %bb.0:15; CHECK-NEXT: retq16 %r = add <4 x i32> %x, undef17 ret <4 x i32> %r18}19 20define i32 @add_undef_lhs(i32 %x) {21; CHECK-LABEL: add_undef_lhs:22; CHECK: # %bb.0:23; CHECK-NEXT: retq24 %r = add i32 undef, %x25 ret i32 %r26}27 28define <4 x i32> @add_undef_lhs_vec(<4 x i32> %x) {29; CHECK-LABEL: add_undef_lhs_vec:30; CHECK: # %bb.0:31; CHECK-NEXT: retq32 %r = add <4 x i32> undef, %x33 ret <4 x i32> %r34}35 36define i32 @sub_undef_rhs(i32 %x) {37; CHECK-LABEL: sub_undef_rhs:38; CHECK: # %bb.0:39; CHECK-NEXT: retq40 %r = sub i32 %x, undef41 ret i32 %r42}43 44define <4 x i32> @sub_undef_rhs_vec(<4 x i32> %x) {45; CHECK-LABEL: sub_undef_rhs_vec:46; CHECK: # %bb.0:47; CHECK-NEXT: retq48 %r = sub <4 x i32> %x, undef49 ret <4 x i32> %r50}51 52define i32 @sub_undef_lhs(i32 %x) {53; CHECK-LABEL: sub_undef_lhs:54; CHECK: # %bb.0:55; CHECK-NEXT: retq56 %r = sub i32 undef, %x57 ret i32 %r58}59 60define <4 x i32> @sub_undef_lhs_vec(<4 x i32> %x) {61; CHECK-LABEL: sub_undef_lhs_vec:62; CHECK: # %bb.0:63; CHECK-NEXT: retq64 %r = sub <4 x i32> undef, %x65 ret <4 x i32> %r66}67 68define i32 @mul_undef_rhs(i32 %x) {69; CHECK-LABEL: mul_undef_rhs:70; CHECK: # %bb.0:71; CHECK-NEXT: xorl %eax, %eax72; CHECK-NEXT: retq73 %r = mul i32 %x, undef74 ret i32 %r75}76 77define <4 x i32> @mul_undef_rhs_vec(<4 x i32> %x) {78; CHECK-LABEL: mul_undef_rhs_vec:79; CHECK: # %bb.0:80; CHECK-NEXT: xorps %xmm0, %xmm081; CHECK-NEXT: retq82 %r = mul <4 x i32> %x, undef83 ret <4 x i32> %r84}85 86define i32 @mul_undef_lhs(i32 %x) {87; CHECK-LABEL: mul_undef_lhs:88; CHECK: # %bb.0:89; CHECK-NEXT: xorl %eax, %eax90; CHECK-NEXT: retq91 %r = mul i32 undef, %x92 ret i32 %r93}94 95define <4 x i32> @mul_undef_lhs_vec(<4 x i32> %x) {96; CHECK-LABEL: mul_undef_lhs_vec:97; CHECK: # %bb.0:98; CHECK-NEXT: xorps %xmm0, %xmm099; CHECK-NEXT: retq100 %r = mul <4 x i32> undef, %x101 ret <4 x i32> %r102}103 104define i32 @sdiv_undef_rhs(i32 %x) {105; CHECK-LABEL: sdiv_undef_rhs:106; CHECK: # %bb.0:107; CHECK-NEXT: retq108 %r = sdiv i32 %x, undef109 ret i32 %r110}111 112define <4 x i32> @sdiv_undef_rhs_vec(<4 x i32> %x) {113; CHECK-LABEL: sdiv_undef_rhs_vec:114; CHECK: # %bb.0:115; CHECK-NEXT: retq116 %r = sdiv <4 x i32> %x, undef117 ret <4 x i32> %r118}119 120define i32 @sdiv_undef_lhs(i32 %x) {121; CHECK-LABEL: sdiv_undef_lhs:122; CHECK: # %bb.0:123; CHECK-NEXT: xorl %eax, %eax124; CHECK-NEXT: retq125 %r = sdiv i32 undef, %x126 ret i32 %r127}128 129define <4 x i32> @sdiv_undef_lhs_vec(<4 x i32> %x) {130; CHECK-LABEL: sdiv_undef_lhs_vec:131; CHECK: # %bb.0:132; CHECK-NEXT: xorps %xmm0, %xmm0133; CHECK-NEXT: retq134 %r = sdiv <4 x i32> undef, %x135 ret <4 x i32> %r136}137 138define i32 @udiv_undef_rhs(i32 %x) {139; CHECK-LABEL: udiv_undef_rhs:140; CHECK: # %bb.0:141; CHECK-NEXT: retq142 %r = udiv i32 %x, undef143 ret i32 %r144}145 146define <4 x i32> @udiv_undef_rhs_vec(<4 x i32> %x) {147; CHECK-LABEL: udiv_undef_rhs_vec:148; CHECK: # %bb.0:149; CHECK-NEXT: retq150 %r = udiv <4 x i32> %x, undef151 ret <4 x i32> %r152}153 154define i32 @udiv_undef_lhs(i32 %x) {155; CHECK-LABEL: udiv_undef_lhs:156; CHECK: # %bb.0:157; CHECK-NEXT: xorl %eax, %eax158; CHECK-NEXT: retq159 %r = udiv i32 undef, %x160 ret i32 %r161}162 163define <4 x i32> @udiv_undef_lhs_vec(<4 x i32> %x) {164; CHECK-LABEL: udiv_undef_lhs_vec:165; CHECK: # %bb.0:166; CHECK-NEXT: xorps %xmm0, %xmm0167; CHECK-NEXT: retq168 %r = udiv <4 x i32> undef, %x169 ret <4 x i32> %r170}171 172define i32 @srem_undef_rhs(i32 %x) {173; CHECK-LABEL: srem_undef_rhs:174; CHECK: # %bb.0:175; CHECK-NEXT: retq176 %r = srem i32 %x, undef177 ret i32 %r178}179 180define <4 x i32> @srem_undef_rhs_vec(<4 x i32> %x) {181; CHECK-LABEL: srem_undef_rhs_vec:182; CHECK: # %bb.0:183; CHECK-NEXT: retq184 %r = srem <4 x i32> %x, undef185 ret <4 x i32> %r186}187 188define i32 @srem_undef_lhs(i32 %x) {189; CHECK-LABEL: srem_undef_lhs:190; CHECK: # %bb.0:191; CHECK-NEXT: xorl %eax, %eax192; CHECK-NEXT: retq193 %r = srem i32 undef, %x194 ret i32 %r195}196 197define <4 x i32> @srem_undef_lhs_vec(<4 x i32> %x) {198; CHECK-LABEL: srem_undef_lhs_vec:199; CHECK: # %bb.0:200; CHECK-NEXT: xorps %xmm0, %xmm0201; CHECK-NEXT: retq202 %r = srem <4 x i32> undef, %x203 ret <4 x i32> %r204}205 206define i32 @urem_undef_rhs(i32 %x) {207; CHECK-LABEL: urem_undef_rhs:208; CHECK: # %bb.0:209; CHECK-NEXT: retq210 %r = urem i32 %x, undef211 ret i32 %r212}213 214define <4 x i32> @urem_undef_rhs_vec(<4 x i32> %x) {215; CHECK-LABEL: urem_undef_rhs_vec:216; CHECK: # %bb.0:217; CHECK-NEXT: retq218 %r = urem <4 x i32> %x, undef219 ret <4 x i32> %r220}221 222define i32 @urem_undef_lhs(i32 %x) {223; CHECK-LABEL: urem_undef_lhs:224; CHECK: # %bb.0:225; CHECK-NEXT: xorl %eax, %eax226; CHECK-NEXT: retq227 %r = urem i32 undef, %x228 ret i32 %r229}230 231define <4 x i32> @urem_undef_lhs_vec(<4 x i32> %x) {232; CHECK-LABEL: urem_undef_lhs_vec:233; CHECK: # %bb.0:234; CHECK-NEXT: xorps %xmm0, %xmm0235; CHECK-NEXT: retq236 %r = urem <4 x i32> undef, %x237 ret <4 x i32> %r238}239 240define i32 @ashr_undef_rhs(i32 %x) {241; CHECK-LABEL: ashr_undef_rhs:242; CHECK: # %bb.0:243; CHECK-NEXT: retq244 %r = ashr i32 %x, undef245 ret i32 %r246}247 248define <4 x i32> @ashr_undef_rhs_vec(<4 x i32> %x) {249; CHECK-LABEL: ashr_undef_rhs_vec:250; CHECK: # %bb.0:251; CHECK-NEXT: retq252 %r = ashr <4 x i32> %x, undef253 ret <4 x i32> %r254}255 256define i32 @ashr_undef_lhs(i32 %x) {257; CHECK-LABEL: ashr_undef_lhs:258; CHECK: # %bb.0:259; CHECK-NEXT: xorl %eax, %eax260; CHECK-NEXT: retq261 %r = ashr i32 undef, %x262 ret i32 %r263}264 265define <4 x i32> @ashr_undef_lhs_vec(<4 x i32> %x) {266; CHECK-LABEL: ashr_undef_lhs_vec:267; CHECK: # %bb.0:268; CHECK-NEXT: xorps %xmm0, %xmm0269; CHECK-NEXT: retq270 %r = ashr <4 x i32> undef, %x271 ret <4 x i32> %r272}273 274define i32 @lshr_undef_rhs(i32 %x) {275; CHECK-LABEL: lshr_undef_rhs:276; CHECK: # %bb.0:277; CHECK-NEXT: retq278 %r = lshr i32 %x, undef279 ret i32 %r280}281 282define <4 x i32> @lshr_undef_rhs_vec(<4 x i32> %x) {283; CHECK-LABEL: lshr_undef_rhs_vec:284; CHECK: # %bb.0:285; CHECK-NEXT: retq286 %r = lshr <4 x i32> %x, undef287 ret <4 x i32> %r288}289 290define i32 @lshr_undef_lhs(i32 %x) {291; CHECK-LABEL: lshr_undef_lhs:292; CHECK: # %bb.0:293; CHECK-NEXT: xorl %eax, %eax294; CHECK-NEXT: retq295 %r = lshr i32 undef, %x296 ret i32 %r297}298 299define <4 x i32> @lshr_undef_lhs_vec(<4 x i32> %x) {300; CHECK-LABEL: lshr_undef_lhs_vec:301; CHECK: # %bb.0:302; CHECK-NEXT: xorps %xmm0, %xmm0303; CHECK-NEXT: retq304 %r = lshr <4 x i32> undef, %x305 ret <4 x i32> %r306}307 308define i32 @shl_undef_rhs(i32 %x) {309; CHECK-LABEL: shl_undef_rhs:310; CHECK: # %bb.0:311; CHECK-NEXT: retq312 %r = shl i32 %x, undef313 ret i32 %r314}315 316define <4 x i32> @shl_undef_rhs_vec(<4 x i32> %x) {317; CHECK-LABEL: shl_undef_rhs_vec:318; CHECK: # %bb.0:319; CHECK-NEXT: retq320 %r = shl <4 x i32> %x, undef321 ret <4 x i32> %r322}323 324define i32 @shl_undef_lhs(i32 %x) {325; CHECK-LABEL: shl_undef_lhs:326; CHECK: # %bb.0:327; CHECK-NEXT: xorl %eax, %eax328; CHECK-NEXT: retq329 %r = shl i32 undef, %x330 ret i32 %r331}332 333define <4 x i32> @shl_undef_lhs_vec(<4 x i32> %x) {334; CHECK-LABEL: shl_undef_lhs_vec:335; CHECK: # %bb.0:336; CHECK-NEXT: xorps %xmm0, %xmm0337; CHECK-NEXT: retq338 %r = shl <4 x i32> undef, %x339 ret <4 x i32> %r340}341 342define i32 @and_undef_rhs(i32 %x) {343; CHECK-LABEL: and_undef_rhs:344; CHECK: # %bb.0:345; CHECK-NEXT: xorl %eax, %eax346; CHECK-NEXT: retq347 %r = and i32 %x, undef348 ret i32 %r349}350 351define <4 x i32> @and_undef_rhs_vec(<4 x i32> %x) {352; CHECK-LABEL: and_undef_rhs_vec:353; CHECK: # %bb.0:354; CHECK-NEXT: xorps %xmm0, %xmm0355; CHECK-NEXT: retq356 %r = and <4 x i32> %x, undef357 ret <4 x i32> %r358}359 360define i32 @and_undef_lhs(i32 %x) {361; CHECK-LABEL: and_undef_lhs:362; CHECK: # %bb.0:363; CHECK-NEXT: xorl %eax, %eax364; CHECK-NEXT: retq365 %r = and i32 undef, %x366 ret i32 %r367}368 369define <4 x i32> @and_undef_lhs_vec(<4 x i32> %x) {370; CHECK-LABEL: and_undef_lhs_vec:371; CHECK: # %bb.0:372; CHECK-NEXT: xorps %xmm0, %xmm0373; CHECK-NEXT: retq374 %r = and <4 x i32> undef, %x375 ret <4 x i32> %r376}377 378define i32 @or_undef_rhs(i32 %x) {379; CHECK-LABEL: or_undef_rhs:380; CHECK: # %bb.0:381; CHECK-NEXT: movl $-1, %eax382; CHECK-NEXT: retq383 %r = or i32 %x, undef384 ret i32 %r385}386 387define <4 x i32> @or_undef_rhs_vec(<4 x i32> %x) {388; CHECK-LABEL: or_undef_rhs_vec:389; CHECK: # %bb.0:390; CHECK-NEXT: pcmpeqd %xmm0, %xmm0391; CHECK-NEXT: retq392 %r = or <4 x i32> %x, undef393 ret <4 x i32> %r394}395 396define i32 @or_undef_lhs(i32 %x) {397; CHECK-LABEL: or_undef_lhs:398; CHECK: # %bb.0:399; CHECK-NEXT: movl $-1, %eax400; CHECK-NEXT: retq401 %r = or i32 undef, %x402 ret i32 %r403}404 405define <4 x i32> @or_undef_lhs_vec(<4 x i32> %x) {406; CHECK-LABEL: or_undef_lhs_vec:407; CHECK: # %bb.0:408; CHECK-NEXT: pcmpeqd %xmm0, %xmm0409; CHECK-NEXT: retq410 %r = or <4 x i32> undef, %x411 ret <4 x i32> %r412}413 414define i32 @xor_undef_rhs(i32 %x) {415; CHECK-LABEL: xor_undef_rhs:416; CHECK: # %bb.0:417; CHECK-NEXT: retq418 %r = xor i32 %x, undef419 ret i32 %r420}421 422define <4 x i32> @xor_undef_rhs_vec(<4 x i32> %x) {423; CHECK-LABEL: xor_undef_rhs_vec:424; CHECK: # %bb.0:425; CHECK-NEXT: retq426 %r = xor <4 x i32> %x, undef427 ret <4 x i32> %r428}429 430define i32 @xor_undef_lhs(i32 %x) {431; CHECK-LABEL: xor_undef_lhs:432; CHECK: # %bb.0:433; CHECK-NEXT: retq434 %r = xor i32 undef, %x435 ret i32 %r436}437 438define <4 x i32> @xor_undef_lhs_vec(<4 x i32> %x) {439; CHECK-LABEL: xor_undef_lhs_vec:440; CHECK: # %bb.0:441; CHECK-NEXT: retq442 %r = xor <4 x i32> undef, %x443 ret <4 x i32> %r444}445 446; This would crash because the shift amount is an i8 operand,447; but the result of the shift is i32. We can't just propagate448; the existing undef as the result.449 450define i1 @undef_operand_size_not_same_as_result() {451; CHECK-LABEL: undef_operand_size_not_same_as_result:452; CHECK: # %bb.0:453; CHECK-NEXT: retq454 %sh = shl i32 7, undef455 %cmp = icmp eq i32 0, %sh456 ret i1 %cmp457}458 459