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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py3# RUN: llc -mtriple=x86_64-- -passes early-machinelicm -mcpu=skx -verify-machineinstrs -o - %s | FileCheck %s4--- |5 @x = dso_local global i32 0, align 46 @z = dso_local local_unnamed_addr global [1024 x i32] zeroinitializer, align 167 @y = dso_local local_unnamed_addr constant ptr null, align 88 9 ; Function Attrs: nofree norecurse nosync nounwind uwtable writeonly mustprogress10 define dso_local void @_Z3foov() local_unnamed_addr #0 {11 %1 = load ptr, ptr @y, align 8, !tbaa !312 %2 = icmp eq ptr %1, @x13 %3 = zext i1 %2 to i3214 br label %515 4: ; preds = %516 ret void17 5: ; preds = %5, %018 %lsr.iv = phi i64 [ %lsr.iv.next, %5 ], [ -4096, %0 ]19 %uglygep = getelementptr i8, ptr @z, i64 %lsr.iv20 %scevgep = getelementptr i32, ptr %uglygep, i64 102421 store i32 %3, ptr %scevgep, align 4, !tbaa !722 %lsr.iv.next = add nsw i64 %lsr.iv, 423 %6 = icmp eq i64 %lsr.iv.next, 024 br i1 %6, label %4, label %5, !llvm.loop !925 }26 27 attributes #0 = { nofree norecurse nosync nounwind uwtable writeonly mustprogress "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+x87,-aes,-avx,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512f,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxvnni,-f16c,-fma,-fma4,-gfni,-kl,-pclmul,-sha,-sse,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-vaes,-vpclmulqdq,-widekl,-xop" "tune-cpu"="generic" }28 29 !llvm.module.flags = !{!0, !1}30 !llvm.ident = !{!2}31 !0 = !{i32 1, !"wchar_size", i32 4}32 !1 = !{i32 7, !"uwtable", i32 1}33 !2 = !{!"clang version 13.0.0 (https://github.com/llvm/llvm-project.git c42dd5dbb015afaef99cf876195c474c63c2393e)"}34 !3 = !{!4, !4, i64 0}35 !4 = !{!"any pointer", !5, i64 0}36 !5 = !{!"omnipotent char", !6, i64 0}37 !6 = !{!"Simple C++ TBAA"}38 !7 = !{!8, !8, i64 0}39 !8 = !{!"int", !5, i64 0}40 !9 = distinct !{!9, !10, !11}41 !10 = !{!"llvm.loop.mustprogress"}42 !11 = !{!"llvm.loop.unroll.disable"}43 44...45---46name: _Z3foov47alignment: 1648exposesReturnsTwice: false49legalized: false50regBankSelected: false51selected: false52failedISel: false53tracksRegLiveness: true54hasWinCFI: false55registers: []56liveins: []57frameInfo:58 isFrameAddressTaken: false59 isReturnAddressTaken: false60 hasStackMap: false61 hasPatchPoint: false62 stackSize: 063 offsetAdjustment: 064 maxAlignment: 165 adjustsStack: false66 hasCalls: false67 stackProtector: ''68 maxCallFrameSize: 429496729569 cvBytesOfCalleeSavedRegisters: 070 hasOpaqueSPAdjustment: false71 hasVAStart: false72 hasMustTailInVarArgFunc: false73 hasTailCall: false74 localFrameSize: 075 savePoint: []76 restorePoint: []77fixedStack: []78stack: []79callSites: []80debugValueSubstitutions: []81constants: []82machineFunctionInfo: {}83body: |84 ; CHECK-LABEL: name: _Z3foov85 ; CHECK: bb.0 (%ir-block.0):86 ; CHECK-NEXT: successors: %bb.2(0x80000000)87 ; CHECK-NEXT: {{ $}}88 ; CHECK-NEXT: renamable $eax = MOV32r0 implicit-def dead $eflags89 ; CHECK-NEXT: renamable $rcx = MOV64ri32 -409690 ; CHECK-NEXT: [[MOV64ri32_:%[0-9]+]]:gr64 = MOV64ri32 -409691 ; CHECK-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm $rip, 1, $noreg, @y, $noreg :: (dereferenceable invariant load (s64) from @y, !tbaa !3)92 ; CHECK-NEXT: JMP_1 %bb.293 ; CHECK-NEXT: {{ $}}94 ; CHECK-NEXT: bb.1 (%ir-block.4):95 ; CHECK-NEXT: RET 096 ; CHECK-NEXT: {{ $}}97 ; CHECK-NEXT: bb.2 (%ir-block.5):98 ; CHECK-NEXT: successors: %bb.1(0x04000000), %bb.2(0x7c000000)99 ; CHECK-NEXT: liveins: $eax, $rcx100 ; CHECK-NEXT: {{ $}}101 ; CHECK-NEXT: CMP64ri32 [[MOV64rm]], @x, implicit-def $eflags102 ; CHECK-NEXT: renamable $al = SETCCr 4, implicit killed $eflags, implicit killed $eax, implicit-def $eax103 ; CHECK-NEXT: MOV32mr renamable $rcx, 1, $noreg, @z + 4096, $noreg, renamable $eax :: (store (s32) into %ir.scevgep, !tbaa !7)104 ; CHECK-NEXT: renamable $rcx = ADD64ri8 killed renamable $rcx, 4, implicit-def $eflags105 ; CHECK-NEXT: JCC_1 %bb.1, 4, implicit killed $eflags106 ; CHECK-NEXT: JMP_1 %bb.2107 bb.0 (%ir-block.0):108 successors: %bb.2(0x80000000)109 renamable $eax = MOV32r0 implicit-def dead $eflags110 renamable $rcx = MOV64ri32 -4096111 JMP_1 %bb.2112 bb.1 (%ir-block.4):113 RET 0114 bb.2 (%ir-block.5):115 successors: %bb.1(0x04000000), %bb.2(0x7c000000)116 liveins: $eax, $rcx117 %2:gr64 = MOV64ri32 -4096118 CMP64mi32 $rip, 1, $noreg, @y, $noreg, @x, implicit-def $eflags :: (dereferenceable invariant load (s64) from @y, !tbaa !3)119 renamable $al = SETCCr 4, implicit killed $eflags, implicit killed $eax, implicit-def $eax120 MOV32mr renamable $rcx, 1, $noreg, @z + 4096, $noreg, renamable $eax :: (store (s32) into %ir.scevgep, !tbaa !7)121 renamable $rcx = ADD64ri8 killed renamable $rcx, 4, implicit-def $eflags122 JCC_1 %bb.1, 4, implicit killed $eflags123 JMP_1 %bb.2124 125...126