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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,SSE23; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,SSE44; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1OR2,AVX15; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX1OR2,AVX26; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=AVX,AVX5127 8define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) {9; SSE-LABEL: fold_urem_vec_1:10; SSE: # %bb.0:11; SSE-NEXT: pextrw $1, %xmm0, %eax12; SSE-NEXT: movl %eax, %ecx13; SSE-NEXT: shrl $2, %ecx14; SSE-NEXT: imull $16913, %ecx, %ecx # imm = 0x421115; SSE-NEXT: shrl $19, %ecx16; SSE-NEXT: imull $124, %ecx, %ecx17; SSE-NEXT: subl %ecx, %eax18; SSE-NEXT: movd %xmm0, %ecx19; SSE-NEXT: movzwl %cx, %edx20; SSE-NEXT: imull $44151, %edx, %edx # imm = 0xAC7721; SSE-NEXT: shrl $22, %edx22; SSE-NEXT: imull $95, %edx, %edx23; SSE-NEXT: subl %edx, %ecx24; SSE-NEXT: movd %ecx, %xmm125; SSE-NEXT: pinsrw $1, %eax, %xmm126; SSE-NEXT: pextrw $2, %xmm0, %eax27; SSE-NEXT: movl %eax, %ecx28; SSE-NEXT: shrl %ecx29; SSE-NEXT: imull $2675, %ecx, %ecx # imm = 0xA7330; SSE-NEXT: shrl $17, %ecx31; SSE-NEXT: imull $98, %ecx, %ecx32; SSE-NEXT: subl %ecx, %eax33; SSE-NEXT: pinsrw $2, %eax, %xmm134; SSE-NEXT: pextrw $3, %xmm0, %eax35; SSE-NEXT: imull $1373, %eax, %ecx # imm = 0x55D36; SSE-NEXT: shrl $16, %ecx37; SSE-NEXT: movl %eax, %edx38; SSE-NEXT: subl %ecx, %edx39; SSE-NEXT: movzwl %dx, %edx40; SSE-NEXT: shrl %edx41; SSE-NEXT: addl %ecx, %edx42; SSE-NEXT: shrl $9, %edx43; SSE-NEXT: imull $1003, %edx, %ecx # imm = 0x3EB44; SSE-NEXT: subl %ecx, %eax45; SSE-NEXT: pinsrw $3, %eax, %xmm146; SSE-NEXT: movdqa %xmm1, %xmm047; SSE-NEXT: retq48;49; AVX-LABEL: fold_urem_vec_1:50; AVX: # %bb.0:51; AVX-NEXT: vpextrw $1, %xmm0, %eax52; AVX-NEXT: movl %eax, %ecx53; AVX-NEXT: shrl $2, %ecx54; AVX-NEXT: imull $16913, %ecx, %ecx # imm = 0x421155; AVX-NEXT: shrl $19, %ecx56; AVX-NEXT: imull $124, %ecx, %ecx57; AVX-NEXT: subl %ecx, %eax58; AVX-NEXT: vmovd %xmm0, %ecx59; AVX-NEXT: movzwl %cx, %edx60; AVX-NEXT: imull $44151, %edx, %edx # imm = 0xAC7761; AVX-NEXT: shrl $22, %edx62; AVX-NEXT: imull $95, %edx, %edx63; AVX-NEXT: subl %edx, %ecx64; AVX-NEXT: vmovd %ecx, %xmm165; AVX-NEXT: vpinsrw $1, %eax, %xmm1, %xmm166; AVX-NEXT: vpextrw $2, %xmm0, %eax67; AVX-NEXT: movl %eax, %ecx68; AVX-NEXT: shrl %ecx69; AVX-NEXT: imull $2675, %ecx, %ecx # imm = 0xA7370; AVX-NEXT: shrl $17, %ecx71; AVX-NEXT: imull $98, %ecx, %ecx72; AVX-NEXT: subl %ecx, %eax73; AVX-NEXT: vpinsrw $2, %eax, %xmm1, %xmm174; AVX-NEXT: vpextrw $3, %xmm0, %eax75; AVX-NEXT: imull $1373, %eax, %ecx # imm = 0x55D76; AVX-NEXT: shrl $16, %ecx77; AVX-NEXT: movl %eax, %edx78; AVX-NEXT: subl %ecx, %edx79; AVX-NEXT: movzwl %dx, %edx80; AVX-NEXT: shrl %edx81; AVX-NEXT: addl %ecx, %edx82; AVX-NEXT: shrl $9, %edx83; AVX-NEXT: imull $1003, %edx, %ecx # imm = 0x3EB84; AVX-NEXT: subl %ecx, %eax85; AVX-NEXT: vpinsrw $3, %eax, %xmm1, %xmm086; AVX-NEXT: retq87 %1 = urem <4 x i16> %x, <i16 95, i16 124, i16 98, i16 1003>88 ret <4 x i16> %189}90 91define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) {92; SSE-LABEL: fold_urem_vec_2:93; SSE: # %bb.0:94; SSE-NEXT: movdqa {{.*#+}} xmm1 = [44151,44151,44151,44151,44151,44151,44151,44151]95; SSE-NEXT: pmulhuw %xmm0, %xmm196; SSE-NEXT: psrlw $6, %xmm197; SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [95,95,95,95,95,95,95,95]98; SSE-NEXT: psubw %xmm1, %xmm099; SSE-NEXT: retq100;101; AVX-LABEL: fold_urem_vec_2:102; AVX: # %bb.0:103; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 # [44151,44151,44151,44151,44151,44151,44151,44151]104; AVX-NEXT: vpsrlw $6, %xmm1, %xmm1105; AVX-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [95,95,95,95,95,95,95,95]106; AVX-NEXT: vpsubw %xmm1, %xmm0, %xmm0107; AVX-NEXT: retq108 %1 = urem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>109 ret <4 x i16> %1110}111 112 113; Don't fold if we can combine urem with udiv.114define <4 x i16> @combine_urem_udiv(<4 x i16> %x) {115; SSE2-LABEL: combine_urem_udiv:116; SSE2: # %bb.0:117; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [44151,44151,44151,44151,44151,44151,44151,44151]118; SSE2-NEXT: pmulhuw %xmm0, %xmm1119; SSE2-NEXT: psrlw $6, %xmm1120; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [95,95,95,95,95,95,95,95]121; SSE2-NEXT: pmullw %xmm1, %xmm2122; SSE2-NEXT: psubw %xmm2, %xmm0123; SSE2-NEXT: paddw %xmm1, %xmm0124; SSE2-NEXT: retq125;126; SSE4-LABEL: combine_urem_udiv:127; SSE4: # %bb.0:128; SSE4-NEXT: movdqa {{.*#+}} xmm1 = [44151,44151,44151,44151,44151,44151,44151,44151]129; SSE4-NEXT: pmulhuw %xmm0, %xmm1130; SSE4-NEXT: psrlw $6, %xmm1131; SSE4-NEXT: pmovsxbw {{.*#+}} xmm2 = [95,95,95,95,95,95,95,95]132; SSE4-NEXT: pmullw %xmm1, %xmm2133; SSE4-NEXT: psubw %xmm2, %xmm0134; SSE4-NEXT: paddw %xmm1, %xmm0135; SSE4-NEXT: retq136;137; AVX-LABEL: combine_urem_udiv:138; AVX: # %bb.0:139; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 # [44151,44151,44151,44151,44151,44151,44151,44151]140; AVX-NEXT: vpsrlw $6, %xmm1, %xmm1141; AVX-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm2 # [95,95,95,95,95,95,95,95]142; AVX-NEXT: vpsubw %xmm2, %xmm0, %xmm0143; AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0144; AVX-NEXT: retq145 %1 = urem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>146 %2 = udiv <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>147 %3 = add <4 x i16> %1, %2148 ret <4 x i16> %3149}150 151; Don't fold for divisors that are a power of two.152define <4 x i16> @dont_fold_urem_power_of_two(<4 x i16> %x) {153; SSE2-LABEL: dont_fold_urem_power_of_two:154; SSE2: # %bb.0:155; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [63,63,63,63]156; SSE2-NEXT: pand %xmm0, %xmm1157; SSE2-NEXT: pextrw $1, %xmm0, %eax158; SSE2-NEXT: andl $31, %eax159; SSE2-NEXT: pinsrw $1, %eax, %xmm1160; SSE2-NEXT: pextrw $2, %xmm0, %eax161; SSE2-NEXT: andl $7, %eax162; SSE2-NEXT: pinsrw $2, %eax, %xmm1163; SSE2-NEXT: pextrw $3, %xmm0, %eax164; SSE2-NEXT: imull $44151, %eax, %ecx # imm = 0xAC77165; SSE2-NEXT: shrl $22, %ecx166; SSE2-NEXT: imull $95, %ecx, %ecx167; SSE2-NEXT: subl %ecx, %eax168; SSE2-NEXT: pinsrw $3, %eax, %xmm1169; SSE2-NEXT: movdqa %xmm1, %xmm0170; SSE2-NEXT: retq171;172; SSE4-LABEL: dont_fold_urem_power_of_two:173; SSE4: # %bb.0:174; SSE4-NEXT: pmovsxbd {{.*#+}} xmm1 = [63,63,63,63]175; SSE4-NEXT: pand %xmm0, %xmm1176; SSE4-NEXT: pextrw $1, %xmm0, %eax177; SSE4-NEXT: andl $31, %eax178; SSE4-NEXT: pinsrw $1, %eax, %xmm1179; SSE4-NEXT: pextrw $2, %xmm0, %eax180; SSE4-NEXT: andl $7, %eax181; SSE4-NEXT: pinsrw $2, %eax, %xmm1182; SSE4-NEXT: pextrw $3, %xmm0, %eax183; SSE4-NEXT: imull $44151, %eax, %ecx # imm = 0xAC77184; SSE4-NEXT: shrl $22, %ecx185; SSE4-NEXT: imull $95, %ecx, %ecx186; SSE4-NEXT: subl %ecx, %eax187; SSE4-NEXT: pinsrw $3, %eax, %xmm1188; SSE4-NEXT: movdqa %xmm1, %xmm0189; SSE4-NEXT: retq190;191; AVX1-LABEL: dont_fold_urem_power_of_two:192; AVX1: # %bb.0:193; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1194; AVX1-NEXT: vpextrw $1, %xmm0, %eax195; AVX1-NEXT: andl $31, %eax196; AVX1-NEXT: vpinsrw $1, %eax, %xmm1, %xmm1197; AVX1-NEXT: vpextrw $2, %xmm0, %eax198; AVX1-NEXT: andl $7, %eax199; AVX1-NEXT: vpinsrw $2, %eax, %xmm1, %xmm1200; AVX1-NEXT: vpextrw $3, %xmm0, %eax201; AVX1-NEXT: imull $44151, %eax, %ecx # imm = 0xAC77202; AVX1-NEXT: shrl $22, %ecx203; AVX1-NEXT: imull $95, %ecx, %ecx204; AVX1-NEXT: subl %ecx, %eax205; AVX1-NEXT: vpinsrw $3, %eax, %xmm1, %xmm0206; AVX1-NEXT: retq207;208; AVX2-LABEL: dont_fold_urem_power_of_two:209; AVX2: # %bb.0:210; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [63,63,63,63]211; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm1212; AVX2-NEXT: vpextrw $1, %xmm0, %eax213; AVX2-NEXT: andl $31, %eax214; AVX2-NEXT: vpinsrw $1, %eax, %xmm1, %xmm1215; AVX2-NEXT: vpextrw $2, %xmm0, %eax216; AVX2-NEXT: andl $7, %eax217; AVX2-NEXT: vpinsrw $2, %eax, %xmm1, %xmm1218; AVX2-NEXT: vpextrw $3, %xmm0, %eax219; AVX2-NEXT: imull $44151, %eax, %ecx # imm = 0xAC77220; AVX2-NEXT: shrl $22, %ecx221; AVX2-NEXT: imull $95, %ecx, %ecx222; AVX2-NEXT: subl %ecx, %eax223; AVX2-NEXT: vpinsrw $3, %eax, %xmm1, %xmm0224; AVX2-NEXT: retq225;226; AVX512-LABEL: dont_fold_urem_power_of_two:227; AVX512: # %bb.0:228; AVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm1229; AVX512-NEXT: vpextrw $1, %xmm0, %eax230; AVX512-NEXT: andl $31, %eax231; AVX512-NEXT: vpinsrw $1, %eax, %xmm1, %xmm1232; AVX512-NEXT: vpextrw $2, %xmm0, %eax233; AVX512-NEXT: andl $7, %eax234; AVX512-NEXT: vpinsrw $2, %eax, %xmm1, %xmm1235; AVX512-NEXT: vpextrw $3, %xmm0, %eax236; AVX512-NEXT: imull $44151, %eax, %ecx # imm = 0xAC77237; AVX512-NEXT: shrl $22, %ecx238; AVX512-NEXT: imull $95, %ecx, %ecx239; AVX512-NEXT: subl %ecx, %eax240; AVX512-NEXT: vpinsrw $3, %eax, %xmm1, %xmm0241; AVX512-NEXT: retq242 %1 = urem <4 x i16> %x, <i16 64, i16 32, i16 8, i16 95>243 ret <4 x i16> %1244}245 246; Don't fold if the divisor is one.247define <4 x i16> @dont_fold_urem_one(<4 x i16> %x) {248; SSE-LABEL: dont_fold_urem_one:249; SSE: # %bb.0:250; SSE-NEXT: pextrw $2, %xmm0, %eax251; SSE-NEXT: imull $25645, %eax, %ecx # imm = 0x642D252; SSE-NEXT: shrl $16, %ecx253; SSE-NEXT: movl %eax, %edx254; SSE-NEXT: subl %ecx, %edx255; SSE-NEXT: movzwl %dx, %edx256; SSE-NEXT: shrl %edx257; SSE-NEXT: addl %ecx, %edx258; SSE-NEXT: shrl $4, %edx259; SSE-NEXT: leal (%rdx,%rdx,2), %ecx260; SSE-NEXT: shll $3, %ecx261; SSE-NEXT: subl %ecx, %edx262; SSE-NEXT: addl %eax, %edx263; SSE-NEXT: pextrw $1, %xmm0, %eax264; SSE-NEXT: imull $51307, %eax, %ecx # imm = 0xC86B265; SSE-NEXT: shrl $25, %ecx266; SSE-NEXT: imull $654, %ecx, %ecx # imm = 0x28E267; SSE-NEXT: subl %ecx, %eax268; SSE-NEXT: pxor %xmm1, %xmm1269; SSE-NEXT: pinsrw $1, %eax, %xmm1270; SSE-NEXT: pinsrw $2, %edx, %xmm1271; SSE-NEXT: pextrw $3, %xmm0, %eax272; SSE-NEXT: imull $12375, %eax, %ecx # imm = 0x3057273; SSE-NEXT: shrl $26, %ecx274; SSE-NEXT: imull $5423, %ecx, %ecx # imm = 0x152F275; SSE-NEXT: subl %ecx, %eax276; SSE-NEXT: pinsrw $3, %eax, %xmm1277; SSE-NEXT: movdqa %xmm1, %xmm0278; SSE-NEXT: retq279;280; AVX1OR2-LABEL: dont_fold_urem_one:281; AVX1OR2: # %bb.0:282; AVX1OR2-NEXT: vpextrw $2, %xmm0, %eax283; AVX1OR2-NEXT: imull $25645, %eax, %ecx # imm = 0x642D284; AVX1OR2-NEXT: shrl $16, %ecx285; AVX1OR2-NEXT: movl %eax, %edx286; AVX1OR2-NEXT: subl %ecx, %edx287; AVX1OR2-NEXT: movzwl %dx, %edx288; AVX1OR2-NEXT: shrl %edx289; AVX1OR2-NEXT: addl %ecx, %edx290; AVX1OR2-NEXT: shrl $4, %edx291; AVX1OR2-NEXT: leal (%rdx,%rdx,2), %ecx292; AVX1OR2-NEXT: shll $3, %ecx293; AVX1OR2-NEXT: subl %ecx, %edx294; AVX1OR2-NEXT: addl %eax, %edx295; AVX1OR2-NEXT: vpextrw $1, %xmm0, %eax296; AVX1OR2-NEXT: imull $51307, %eax, %ecx # imm = 0xC86B297; AVX1OR2-NEXT: shrl $25, %ecx298; AVX1OR2-NEXT: imull $654, %ecx, %ecx # imm = 0x28E299; AVX1OR2-NEXT: subl %ecx, %eax300; AVX1OR2-NEXT: vpxor %xmm1, %xmm1, %xmm1301; AVX1OR2-NEXT: vpinsrw $1, %eax, %xmm1, %xmm1302; AVX1OR2-NEXT: vpinsrw $2, %edx, %xmm1, %xmm1303; AVX1OR2-NEXT: vpextrw $3, %xmm0, %eax304; AVX1OR2-NEXT: imull $12375, %eax, %ecx # imm = 0x3057305; AVX1OR2-NEXT: shrl $26, %ecx306; AVX1OR2-NEXT: imull $5423, %ecx, %ecx # imm = 0x152F307; AVX1OR2-NEXT: subl %ecx, %eax308; AVX1OR2-NEXT: vpinsrw $3, %eax, %xmm1, %xmm0309; AVX1OR2-NEXT: retq310;311; AVX512-LABEL: dont_fold_urem_one:312; AVX512: # %bb.0:313; AVX512-NEXT: vpextrw $2, %xmm0, %eax314; AVX512-NEXT: imull $25645, %eax, %ecx # imm = 0x642D315; AVX512-NEXT: shrl $16, %ecx316; AVX512-NEXT: movl %eax, %edx317; AVX512-NEXT: subl %ecx, %edx318; AVX512-NEXT: movzwl %dx, %edx319; AVX512-NEXT: shrl %edx320; AVX512-NEXT: addl %ecx, %edx321; AVX512-NEXT: shrl $4, %edx322; AVX512-NEXT: leal (%rdx,%rdx,2), %ecx323; AVX512-NEXT: shll $3, %ecx324; AVX512-NEXT: subl %ecx, %edx325; AVX512-NEXT: vpextrw $1, %xmm0, %ecx326; AVX512-NEXT: addl %eax, %edx327; AVX512-NEXT: imull $51307, %ecx, %eax # imm = 0xC86B328; AVX512-NEXT: shrl $25, %eax329; AVX512-NEXT: imull $654, %eax, %eax # imm = 0x28E330; AVX512-NEXT: subl %eax, %ecx331; AVX512-NEXT: vpxor %xmm1, %xmm1, %xmm1332; AVX512-NEXT: vpinsrw $1, %ecx, %xmm1, %xmm1333; AVX512-NEXT: vpinsrw $2, %edx, %xmm1, %xmm1334; AVX512-NEXT: vpextrw $3, %xmm0, %eax335; AVX512-NEXT: imull $12375, %eax, %ecx # imm = 0x3057336; AVX512-NEXT: shrl $26, %ecx337; AVX512-NEXT: imull $5423, %ecx, %ecx # imm = 0x152F338; AVX512-NEXT: subl %ecx, %eax339; AVX512-NEXT: vpinsrw $3, %eax, %xmm1, %xmm0340; AVX512-NEXT: retq341 %1 = urem <4 x i16> %x, <i16 1, i16 654, i16 23, i16 5423>342 ret <4 x i16> %1343}344 345; Don't fold if the divisor is 2^16.346define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) {347; CHECK-LABEL: dont_fold_urem_i16_smax:348; CHECK: # %bb.0:349; CHECK-NEXT: retq350; SSE-LABEL: dont_fold_urem_i16_smax:351; SSE: # %bb.0:352; SSE-NEXT: retq353;354; AVX-LABEL: dont_fold_urem_i16_smax:355; AVX: # %bb.0:356; AVX-NEXT: retq357 %1 = urem <4 x i16> %x, <i16 1, i16 65536, i16 23, i16 5423>358 ret <4 x i16> %1359}360 361; Don't fold i64 urem.362define <4 x i64> @dont_fold_urem_i64(<4 x i64> %x) {363; SSE2-LABEL: dont_fold_urem_i64:364; SSE2: # %bb.0:365; SSE2-NEXT: movdqa %xmm1, %xmm2366; SSE2-NEXT: movq %xmm1, %rcx367; SSE2-NEXT: movabsq $7218291159277650633, %rdx # imm = 0x642C8590B21642C9368; SSE2-NEXT: movq %rcx, %rax369; SSE2-NEXT: mulq %rdx370; SSE2-NEXT: movq %rcx, %rax371; SSE2-NEXT: subq %rdx, %rax372; SSE2-NEXT: shrq %rax373; SSE2-NEXT: addq %rdx, %rax374; SSE2-NEXT: shrq $4, %rax375; SSE2-NEXT: leaq (%rax,%rax,2), %rdx376; SSE2-NEXT: shlq $3, %rdx377; SSE2-NEXT: subq %rdx, %rax378; SSE2-NEXT: addq %rcx, %rax379; SSE2-NEXT: movq %rax, %xmm1380; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,2,3]381; SSE2-NEXT: movq %xmm2, %rcx382; SSE2-NEXT: movabsq $-4513890722074972339, %rdx # imm = 0xC15B704DCBCA2F4D383; SSE2-NEXT: movq %rcx, %rax384; SSE2-NEXT: mulq %rdx385; SSE2-NEXT: shrq $12, %rdx386; SSE2-NEXT: imulq $5423, %rdx, %rax # imm = 0x152F387; SSE2-NEXT: subq %rax, %rcx388; SSE2-NEXT: movq %rcx, %xmm2389; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]390; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]391; SSE2-NEXT: movq %xmm0, %rcx392; SSE2-NEXT: movq %rcx, %rax393; SSE2-NEXT: shrq %rax394; SSE2-NEXT: movabsq $7220743857598845893, %rdx # imm = 0x64353C48064353C5395; SSE2-NEXT: mulq %rdx396; SSE2-NEXT: shrq $7, %rdx397; SSE2-NEXT: imulq $654, %rdx, %rax # imm = 0x28E398; SSE2-NEXT: subq %rax, %rcx399; SSE2-NEXT: movq %rcx, %xmm0400; SSE2-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]401; SSE2-NEXT: retq402;403; SSE4-LABEL: dont_fold_urem_i64:404; SSE4: # %bb.0:405; SSE4-NEXT: movq %xmm1, %rcx406; SSE4-NEXT: movabsq $7218291159277650633, %rdx # imm = 0x642C8590B21642C9407; SSE4-NEXT: movq %rcx, %rax408; SSE4-NEXT: mulq %rdx409; SSE4-NEXT: movq %rcx, %rax410; SSE4-NEXT: subq %rdx, %rax411; SSE4-NEXT: shrq %rax412; SSE4-NEXT: addq %rdx, %rax413; SSE4-NEXT: shrq $4, %rax414; SSE4-NEXT: leaq (%rax,%rax,2), %rdx415; SSE4-NEXT: shlq $3, %rdx416; SSE4-NEXT: subq %rdx, %rax417; SSE4-NEXT: addq %rcx, %rax418; SSE4-NEXT: movq %rax, %xmm2419; SSE4-NEXT: pextrq $1, %xmm1, %rcx420; SSE4-NEXT: movabsq $-4513890722074972339, %rdx # imm = 0xC15B704DCBCA2F4D421; SSE4-NEXT: movq %rcx, %rax422; SSE4-NEXT: mulq %rdx423; SSE4-NEXT: shrq $12, %rdx424; SSE4-NEXT: imulq $5423, %rdx, %rax # imm = 0x152F425; SSE4-NEXT: subq %rax, %rcx426; SSE4-NEXT: movq %rcx, %xmm1427; SSE4-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]428; SSE4-NEXT: pextrq $1, %xmm0, %rcx429; SSE4-NEXT: movq %rcx, %rax430; SSE4-NEXT: shrq %rax431; SSE4-NEXT: movabsq $7220743857598845893, %rdx # imm = 0x64353C48064353C5432; SSE4-NEXT: mulq %rdx433; SSE4-NEXT: shrq $7, %rdx434; SSE4-NEXT: imulq $654, %rdx, %rax # imm = 0x28E435; SSE4-NEXT: subq %rax, %rcx436; SSE4-NEXT: movq %rcx, %xmm0437; SSE4-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]438; SSE4-NEXT: movdqa %xmm2, %xmm1439; SSE4-NEXT: retq440;441; AVX1-LABEL: dont_fold_urem_i64:442; AVX1: # %bb.0:443; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1444; AVX1-NEXT: vmovq %xmm1, %rcx445; AVX1-NEXT: movabsq $7218291159277650633, %rdx # imm = 0x642C8590B21642C9446; AVX1-NEXT: movq %rcx, %rax447; AVX1-NEXT: mulq %rdx448; AVX1-NEXT: movq %rcx, %rax449; AVX1-NEXT: subq %rdx, %rax450; AVX1-NEXT: shrq %rax451; AVX1-NEXT: addq %rdx, %rax452; AVX1-NEXT: shrq $4, %rax453; AVX1-NEXT: leaq (%rax,%rax,2), %rdx454; AVX1-NEXT: shlq $3, %rdx455; AVX1-NEXT: subq %rdx, %rax456; AVX1-NEXT: addq %rcx, %rax457; AVX1-NEXT: vmovq %rax, %xmm2458; AVX1-NEXT: vpextrq $1, %xmm1, %rcx459; AVX1-NEXT: movabsq $-4513890722074972339, %rdx # imm = 0xC15B704DCBCA2F4D460; AVX1-NEXT: movq %rcx, %rax461; AVX1-NEXT: mulq %rdx462; AVX1-NEXT: shrq $12, %rdx463; AVX1-NEXT: imulq $5423, %rdx, %rax # imm = 0x152F464; AVX1-NEXT: subq %rax, %rcx465; AVX1-NEXT: vmovq %rcx, %xmm1466; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]467; AVX1-NEXT: vpextrq $1, %xmm0, %rcx468; AVX1-NEXT: movq %rcx, %rax469; AVX1-NEXT: shrq %rax470; AVX1-NEXT: movabsq $7220743857598845893, %rdx # imm = 0x64353C48064353C5471; AVX1-NEXT: mulq %rdx472; AVX1-NEXT: shrq $7, %rdx473; AVX1-NEXT: imulq $654, %rdx, %rax # imm = 0x28E474; AVX1-NEXT: subq %rax, %rcx475; AVX1-NEXT: vmovq %rcx, %xmm0476; AVX1-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]477; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0478; AVX1-NEXT: retq479;480; AVX2-LABEL: dont_fold_urem_i64:481; AVX2: # %bb.0:482; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1483; AVX2-NEXT: vmovq %xmm1, %rcx484; AVX2-NEXT: movabsq $7218291159277650633, %rdx # imm = 0x642C8590B21642C9485; AVX2-NEXT: movq %rcx, %rax486; AVX2-NEXT: mulq %rdx487; AVX2-NEXT: movq %rcx, %rax488; AVX2-NEXT: subq %rdx, %rax489; AVX2-NEXT: shrq %rax490; AVX2-NEXT: addq %rdx, %rax491; AVX2-NEXT: shrq $4, %rax492; AVX2-NEXT: leaq (%rax,%rax,2), %rdx493; AVX2-NEXT: shlq $3, %rdx494; AVX2-NEXT: subq %rdx, %rax495; AVX2-NEXT: addq %rcx, %rax496; AVX2-NEXT: vmovq %rax, %xmm2497; AVX2-NEXT: vpextrq $1, %xmm1, %rcx498; AVX2-NEXT: movabsq $-4513890722074972339, %rdx # imm = 0xC15B704DCBCA2F4D499; AVX2-NEXT: movq %rcx, %rax500; AVX2-NEXT: mulq %rdx501; AVX2-NEXT: shrq $12, %rdx502; AVX2-NEXT: imulq $5423, %rdx, %rax # imm = 0x152F503; AVX2-NEXT: subq %rax, %rcx504; AVX2-NEXT: vmovq %rcx, %xmm1505; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]506; AVX2-NEXT: vpextrq $1, %xmm0, %rcx507; AVX2-NEXT: movq %rcx, %rax508; AVX2-NEXT: shrq %rax509; AVX2-NEXT: movabsq $7220743857598845893, %rdx # imm = 0x64353C48064353C5510; AVX2-NEXT: mulq %rdx511; AVX2-NEXT: shrq $7, %rdx512; AVX2-NEXT: imulq $654, %rdx, %rax # imm = 0x28E513; AVX2-NEXT: subq %rax, %rcx514; AVX2-NEXT: vmovq %rcx, %xmm0515; AVX2-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]516; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0517; AVX2-NEXT: retq518;519; AVX512-LABEL: dont_fold_urem_i64:520; AVX512: # %bb.0:521; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1522; AVX512-NEXT: vmovq %xmm1, %rdx523; AVX512-NEXT: movabsq $7218291159277650633, %rax # imm = 0x642C8590B21642C9524; AVX512-NEXT: mulxq %rax, %rax, %rax525; AVX512-NEXT: movq %rdx, %rcx526; AVX512-NEXT: subq %rax, %rcx527; AVX512-NEXT: shrq %rcx528; AVX512-NEXT: addq %rax, %rcx529; AVX512-NEXT: shrq $4, %rcx530; AVX512-NEXT: leaq (%rcx,%rcx,2), %rax531; AVX512-NEXT: shlq $3, %rax532; AVX512-NEXT: subq %rax, %rcx533; AVX512-NEXT: addq %rdx, %rcx534; AVX512-NEXT: vpextrq $1, %xmm1, %rdx535; AVX512-NEXT: movabsq $-4513890722074972339, %rax # imm = 0xC15B704DCBCA2F4D536; AVX512-NEXT: mulxq %rax, %rax, %rax537; AVX512-NEXT: vmovq %rcx, %xmm1538; AVX512-NEXT: shrq $12, %rax539; AVX512-NEXT: imulq $5423, %rax, %rax # imm = 0x152F540; AVX512-NEXT: subq %rax, %rdx541; AVX512-NEXT: vmovq %rdx, %xmm2542; AVX512-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]543; AVX512-NEXT: vpextrq $1, %xmm0, %rax544; AVX512-NEXT: movq %rax, %rdx545; AVX512-NEXT: shrq %rdx546; AVX512-NEXT: movabsq $7220743857598845893, %rcx # imm = 0x64353C48064353C5547; AVX512-NEXT: mulxq %rcx, %rcx, %rcx548; AVX512-NEXT: shrq $7, %rcx549; AVX512-NEXT: imulq $654, %rcx, %rcx # imm = 0x28E550; AVX512-NEXT: subq %rcx, %rax551; AVX512-NEXT: vmovq %rax, %xmm0552; AVX512-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]553; AVX512-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0554; AVX512-NEXT: retq555 %1 = urem <4 x i64> %x, <i64 1, i64 654, i64 23, i64 5423>556 ret <4 x i64> %1557}558