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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-linux -mcpu=penryn | FileCheck %s --check-prefixes=CHECK,X643; RUN: llc < %s -mtriple=i386-linux-gnu -mcpu=yonah | FileCheck %s --check-prefixes=CHECK,X864 5; PR75186define void @test1(<2 x float> %Q, ptr%P2) nounwind {7; X64-LABEL: test1:8; X64: # %bb.0:9; X64-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]10; X64-NEXT: addss %xmm0, %xmm111; X64-NEXT: movss %xmm1, (%rdi)12; X64-NEXT: retq13;14; X86-LABEL: test1:15; X86: # %bb.0:16; X86-NEXT: movl {{[0-9]+}}(%esp), %eax17; X86-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]18; X86-NEXT: addss %xmm0, %xmm119; X86-NEXT: movss %xmm1, (%eax)20; X86-NEXT: retl21 %a = extractelement <2 x float> %Q, i32 022 %b = extractelement <2 x float> %Q, i32 123 %c = fadd float %a, %b24 store float %c, ptr %P225 ret void26}27 28define <2 x float> @test2(<2 x float> %Q, <2 x float> %R, ptr%P) nounwind {29; CHECK-LABEL: test2:30; CHECK: # %bb.0:31; CHECK-NEXT: addps %xmm1, %xmm032; CHECK-NEXT: ret{{[l|q]}}33 %Z = fadd <2 x float> %Q, %R34 ret <2 x float> %Z35}36 37define <2 x float> @test3(<4 x float> %A) nounwind {38; CHECK-LABEL: test3:39; CHECK: # %bb.0:40; CHECK-NEXT: addps %xmm0, %xmm041; CHECK-NEXT: ret{{[l|q]}}42 %B = shufflevector <4 x float> %A, <4 x float> undef, <2 x i32> <i32 0, i32 1>43 %C = fadd <2 x float> %B, %B44 ret <2 x float> %C45}46 47define <2 x float> @test4(<2 x float> %A) nounwind {48; CHECK-LABEL: test4:49; CHECK: # %bb.0:50; CHECK-NEXT: addps %xmm0, %xmm051; CHECK-NEXT: ret{{[l|q]}}52 %C = fadd <2 x float> %A, %A53 ret <2 x float> %C54}55 56define <4 x float> @test5(<4 x float> %A) nounwind {57; CHECK-LABEL: test5:58; CHECK: # %bb.0:59; CHECK-NEXT: addps %xmm0, %xmm060; CHECK-NEXT: addps %xmm0, %xmm061; CHECK-NEXT: ret{{[l|q]}}62 %B = shufflevector <4 x float> %A, <4 x float> undef, <2 x i32> <i32 0, i32 1>63 %C = fadd <2 x float> %B, %B64 br label %BB65 66BB:67 %D = fadd <2 x float> %C, %C68 %E = shufflevector <2 x float> %D, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>69 ret <4 x float> %E70}71 72 73