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1; RUN: llc < %s -mtriple=x86_64-apple-macosx10.10.0 -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE22; RUN: llc < %s -mtriple=x86_64-apple-macosx10.10.0 -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX3 4; Assertions have been enhanced from utils/update_llc_test_checks.py to show the constant pool values.5; Use a macosx triple to make sure the format of those constant strings is exact.6 7; CHECK: [[SIGNMASK1:L.+]]:8; CHECK-NEXT: .long 0x800000009; CHECK-NEXT: .long 0x8000000010; CHECK-NEXT: .long 0x8000000011; CHECK-NEXT: .long 0x8000000012 13; CHECK: [[MAGMASK1:L.+]]:14; CHECK-NEXT: .long 0x7fffffff15; CHECK-NEXT: .long 0x7fffffff16; CHECK-NEXT: .long 0x7fffffff17; CHECK-NEXT: .long 0x7fffffff18 19define <4 x float> @v4f32(<4 x float> %a, <4 x float> %b) nounwind {20; SSE2-LABEL: v4f32:21; SSE2: # %bb.0:22; SSE2-NEXT: andps [[SIGNMASK1]](%rip), %xmm123; SSE2-NEXT: andps [[MAGMASK1]](%rip), %xmm024; SSE2-NEXT: orps %xmm1, %xmm025; SSE2-NEXT: retq26;27; AVX-LABEL: v4f32:28; AVX: # %bb.0:29; AVX-NEXT: vandps [[SIGNMASK1]](%rip), %xmm1, %xmm130; AVX-NEXT: vandps [[MAGMASK1]](%rip), %xmm0, %xmm031; AVX-NEXT: vorps %xmm1, %xmm0, %xmm032; AVX-NEXT: retq33;34 %tmp = tail call <4 x float> @llvm.copysign.v4f32( <4 x float> %a, <4 x float> %b )35 ret <4 x float> %tmp36}37 38; SSE2: [[MAGMASK2:L.+]]:39; SSE2-NEXT: .long 0x7fffffff40; SSE2-NEXT: .long 0x7fffffff41; SSE2-NEXT: .long 0x7fffffff42; SSE2-NEXT: .long 0x7fffffff43 44; AVX: [[SIGNMASK2:L.+]]:45; AVX-NEXT: .long 0x8000000046; AVX-NEXT: .long 0x8000000047; AVX-NEXT: .long 0x8000000048; AVX-NEXT: .long 0x8000000049; AVX-NEXT: .long 0x8000000050; AVX-NEXT: .long 0x8000000051; AVX-NEXT: .long 0x8000000052; AVX-NEXT: .long 0x8000000053 54; AVX: [[MAGMASK2:L.+]]:55; AVX-NEXT: .long 0x7fffffff56; AVX-NEXT: .long 0x7fffffff57; AVX-NEXT: .long 0x7fffffff58; AVX-NEXT: .long 0x7fffffff59; AVX-NEXT: .long 0x7fffffff60; AVX-NEXT: .long 0x7fffffff61; AVX-NEXT: .long 0x7fffffff62; AVX-NEXT: .long 0x7fffffff63 64define <8 x float> @v8f32(<8 x float> %a, <8 x float> %b) nounwind {65; SSE2-LABEL: v8f32:66; SSE2: # %bb.0:67; SSE2-NEXT: movaps [[MAGMASK2]](%rip), %xmm468; SSE2-NEXT: movaps %xmm4, %xmm569; SSE2-NEXT: andnps %xmm2, %xmm570; SSE2-NEXT: andps %xmm4, %xmm071; SSE2-NEXT: orps %xmm5, %xmm072; SSE2-NEXT: andps %xmm4, %xmm173; SSE2-NEXT: andnps %xmm3, %xmm474; SSE2-NEXT: orps %xmm4, %xmm175; SSE2-NEXT: retq76;77; AVX-LABEL: v8f32:78; AVX: # %bb.0:79; AVX-NEXT: vandps [[SIGNMASK2]](%rip), %ymm1, %ymm180; AVX-NEXT: vandps [[MAGMASK2]](%rip), %ymm0, %ymm081; AVX-NEXT: vorps %ymm1, %ymm0, %ymm082; AVX-NEXT: retq83;84 %tmp = tail call <8 x float> @llvm.copysign.v8f32( <8 x float> %a, <8 x float> %b )85 ret <8 x float> %tmp86}87 88; CHECK: [[SIGNMASK3:L.+]]:89; CHECK-NEXT: .quad 0x800000000000000090; CHECK-NEXT: .quad 0x800000000000000091 92; CHECK: [[MAGMASK3:L.+]]:93; CHECK-NEXT: .quad 0x7fffffffffffffff94; CHECK-NEXT: .quad 0x7fffffffffffffff95 96define <2 x double> @v2f64(<2 x double> %a, <2 x double> %b) nounwind {97; SSE2-LABEL: v2f64:98; SSE2: # %bb.0:99; SSE2-NEXT: andps [[SIGNMASK3]](%rip), %xmm1100; SSE2-NEXT: andps [[MAGMASK3]](%rip), %xmm0101; SSE2-NEXT: orps %xmm1, %xmm0102; SSE2-NEXT: retq103;104; AVX-LABEL: v2f64:105; AVX: # %bb.0:106; AVX-NEXT: vandps [[SIGNMASK3]](%rip), %xmm1, %xmm1107; AVX-NEXT: vandps [[MAGMASK3]](%rip), %xmm0, %xmm0108; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0109; AVX-NEXT: retq110;111 %tmp = tail call <2 x double> @llvm.copysign.v2f64( <2 x double> %a, <2 x double> %b )112 ret <2 x double> %tmp113}114 115; SSE2: [[MAGMASK4:L.+]]:116; SSE2-NEXT: .quad 0x7fffffffffffffff117; SSE2-NEXT: .quad 0x7fffffffffffffff118 119; AVX: [[SIGNMASK4:L.+]]:120; AVX-NEXT: .quad 0x8000000000000000121; AVX-NEXT: .quad 0x8000000000000000122; AVX-NEXT: .quad 0x8000000000000000123; AVX-NEXT: .quad 0x8000000000000000124 125; AVX: [[MAGMASK4:L.+]]:126; AVX-NEXT: .quad 0x7fffffffffffffff127; AVX-NEXT: .quad 0x7fffffffffffffff128; AVX-NEXT: .quad 0x7fffffffffffffff129; AVX-NEXT: .quad 0x7fffffffffffffff130 131define <4 x double> @v4f64(<4 x double> %a, <4 x double> %b) nounwind {132; SSE2-LABEL: v4f64:133; SSE2: # %bb.0:134; SSE2-NEXT: movaps [[MAGMASK4]](%rip), %xmm4135; SSE2-NEXT: movaps %xmm4, %xmm5136; SSE2-NEXT: andnps %xmm2, %xmm5137; SSE2-NEXT: andps %xmm4, %xmm0138; SSE2-NEXT: orps %xmm5, %xmm0139; SSE2-NEXT: andps %xmm4, %xmm1140; SSE2-NEXT: andnps %xmm3, %xmm4141; SSE2-NEXT: orps %xmm4, %xmm1142; SSE2-NEXT: retq143;144; AVX-LABEL: v4f64:145; AVX: # %bb.0:146; AVX-NEXT: vandps [[SIGNMASK4]](%rip), %ymm1, %ymm1147; AVX-NEXT: vandps [[MAGMASK4]](%rip), %ymm0, %ymm0148; AVX-NEXT: vorps %ymm1, %ymm0, %ymm0149; AVX-NEXT: retq150;151 %tmp = tail call <4 x double> @llvm.copysign.v4f64( <4 x double> %a, <4 x double> %b )152 ret <4 x double> %tmp153}154 155declare <4 x float> @llvm.copysign.v4f32(<4 x float> %Mag, <4 x float> %Sgn)156declare <8 x float> @llvm.copysign.v8f32(<8 x float> %Mag, <8 x float> %Sgn)157declare <2 x double> @llvm.copysign.v2f64(<2 x double> %Mag, <2 x double> %Sgn)158declare <4 x double> @llvm.copysign.v4f64(<4 x double> %Mag, <4 x double> %Sgn)159 160