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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -disable-peephole -mtriple=i686-unknown-unknown -mattr=+sse2 -O3 | FileCheck %s --check-prefix=SSE-323; RUN: llc < %s -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+sse2 -O3 | FileCheck %s --check-prefix=SSE-644; RUN: llc < %s -disable-peephole -mtriple=i686-unknown-unknown -mattr=+avx -O3 | FileCheck %s --check-prefixes=AVX,AVX-325; RUN: llc < %s -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+avx -O3 | FileCheck %s --check-prefixes=AVX,AVX-646; RUN: llc < %s -disable-peephole -mtriple=i686-unknown-unknown -mattr=+avx512f -O3 | FileCheck %s --check-prefixes=AVX512F,AVX512F-327; RUN: llc < %s -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+avx512f -O3 | FileCheck %s --check-prefixes=AVX512F,AVX512F-648; RUN: llc < %s -disable-peephole -mtriple=i686-unknown-unknown -mattr=+avx512vl -O3 | FileCheck %s --check-prefixes=AVX512VL,AVX512VL-329; RUN: llc < %s -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+avx512vl -O3 | FileCheck %s --check-prefixes=AVX512VL,AVX512VL-6410; RUN: llc < %s -disable-peephole -mtriple=i686-unknown-unknown -mattr=avx512dq -O3 | FileCheck %s --check-prefixes=AVX512DQ,AVX512DQ-3211; RUN: llc < %s -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=avx512dq -O3 | FileCheck %s --check-prefixes=AVX512DQ,AVX512DQ-6412; RUN: llc < %s -disable-peephole -mtriple=i686-unknown-unknown -mattr=avx512dq,avx512vl -O3 | FileCheck %s --check-prefixes=AVX512VLDQ,AVX512VLDQ-3213; RUN: llc < %s -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=avx512dq,avx512vl -O3 | FileCheck %s --check-prefixes=AVX512VLDQ,AVX512VLDQ-6414 15declare <2 x i64> @llvm.experimental.constrained.fptosi.v2i64.v2f64(<2 x double>, metadata)16declare <2 x i64> @llvm.experimental.constrained.fptoui.v2i64.v2f64(<2 x double>, metadata)17declare <2 x i64> @llvm.experimental.constrained.fptosi.v2i64.v2f32(<2 x float>, metadata)18declare <2 x i64> @llvm.experimental.constrained.fptoui.v2i64.v2f32(<2 x float>, metadata)19declare <2 x i32> @llvm.experimental.constrained.fptosi.v2i32.v2f64(<2 x double>, metadata)20declare <2 x i32> @llvm.experimental.constrained.fptoui.v2i32.v2f64(<2 x double>, metadata)21declare <2 x i32> @llvm.experimental.constrained.fptosi.v2i32.v2f32(<2 x float>, metadata)22declare <2 x i32> @llvm.experimental.constrained.fptoui.v2i32.v2f32(<2 x float>, metadata)23declare <2 x i16> @llvm.experimental.constrained.fptosi.v2i16.v2f64(<2 x double>, metadata)24declare <2 x i16> @llvm.experimental.constrained.fptoui.v2i16.v2f64(<2 x double>, metadata)25declare <2 x i16> @llvm.experimental.constrained.fptosi.v2i16.v2f32(<2 x float>, metadata)26declare <2 x i16> @llvm.experimental.constrained.fptoui.v2i16.v2f32(<2 x float>, metadata)27declare <2 x i8> @llvm.experimental.constrained.fptosi.v2i8.v2f64(<2 x double>, metadata)28declare <2 x i8> @llvm.experimental.constrained.fptoui.v2i8.v2f64(<2 x double>, metadata)29declare <2 x i8> @llvm.experimental.constrained.fptosi.v2i8.v2f32(<2 x float>, metadata)30declare <2 x i8> @llvm.experimental.constrained.fptoui.v2i8.v2f32(<2 x float>, metadata)31declare <2 x i1> @llvm.experimental.constrained.fptosi.v2i1.v2f64(<2 x double>, metadata)32declare <2 x i1> @llvm.experimental.constrained.fptoui.v2i1.v2f64(<2 x double>, metadata)33declare <2 x i1> @llvm.experimental.constrained.fptosi.v2i1.v2f32(<2 x float>, metadata)34declare <2 x i1> @llvm.experimental.constrained.fptoui.v2i1.v2f32(<2 x float>, metadata)35declare <4 x i32> @llvm.experimental.constrained.fptosi.v4i32.v4f32(<4 x float>, metadata)36declare <4 x i32> @llvm.experimental.constrained.fptoui.v4i32.v4f32(<4 x float>, metadata)37declare <4 x i16> @llvm.experimental.constrained.fptosi.v4i16.v4f32(<4 x float>, metadata)38declare <4 x i16> @llvm.experimental.constrained.fptoui.v4i16.v4f32(<4 x float>, metadata)39declare <4 x i8> @llvm.experimental.constrained.fptosi.v4i8.v4f32(<4 x float>, metadata)40declare <4 x i8> @llvm.experimental.constrained.fptoui.v4i8.v4f32(<4 x float>, metadata)41declare <4 x i1> @llvm.experimental.constrained.fptosi.v4i1.v4f32(<4 x float>, metadata)42declare <4 x i1> @llvm.experimental.constrained.fptoui.v4i1.v4f32(<4 x float>, metadata)43 44define <2 x i64> @strict_vector_fptosi_v2f64_to_v2i64(<2 x double> %a) #0 {45; SSE-32-LABEL: strict_vector_fptosi_v2f64_to_v2i64:46; SSE-32: # %bb.0:47; SSE-32-NEXT: pushl %ebp48; SSE-32-NEXT: .cfi_def_cfa_offset 849; SSE-32-NEXT: .cfi_offset %ebp, -850; SSE-32-NEXT: movl %esp, %ebp51; SSE-32-NEXT: .cfi_def_cfa_register %ebp52; SSE-32-NEXT: andl $-8, %esp53; SSE-32-NEXT: subl $24, %esp54; SSE-32-NEXT: movhps %xmm0, {{[0-9]+}}(%esp)55; SSE-32-NEXT: movlps %xmm0, {{[0-9]+}}(%esp)56; SSE-32-NEXT: fldl {{[0-9]+}}(%esp)57; SSE-32-NEXT: wait58; SSE-32-NEXT: fnstcw {{[0-9]+}}(%esp)59; SSE-32-NEXT: movzwl {{[0-9]+}}(%esp), %eax60; SSE-32-NEXT: orl $3072, %eax # imm = 0xC0061; SSE-32-NEXT: movw %ax, {{[0-9]+}}(%esp)62; SSE-32-NEXT: fldcw {{[0-9]+}}(%esp)63; SSE-32-NEXT: fistpll {{[0-9]+}}(%esp)64; SSE-32-NEXT: fldcw {{[0-9]+}}(%esp)65; SSE-32-NEXT: fldl {{[0-9]+}}(%esp)66; SSE-32-NEXT: wait67; SSE-32-NEXT: fnstcw (%esp)68; SSE-32-NEXT: movzwl (%esp), %eax69; SSE-32-NEXT: orl $3072, %eax # imm = 0xC0070; SSE-32-NEXT: movw %ax, {{[0-9]+}}(%esp)71; SSE-32-NEXT: fldcw {{[0-9]+}}(%esp)72; SSE-32-NEXT: fistpll {{[0-9]+}}(%esp)73; SSE-32-NEXT: fldcw (%esp)74; SSE-32-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero75; SSE-32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero76; SSE-32-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]77; SSE-32-NEXT: movl %ebp, %esp78; SSE-32-NEXT: popl %ebp79; SSE-32-NEXT: .cfi_def_cfa %esp, 480; SSE-32-NEXT: retl81;82; SSE-64-LABEL: strict_vector_fptosi_v2f64_to_v2i64:83; SSE-64: # %bb.0:84; SSE-64-NEXT: cvttsd2si %xmm0, %rax85; SSE-64-NEXT: movq %rax, %xmm186; SSE-64-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]87; SSE-64-NEXT: cvttsd2si %xmm0, %rax88; SSE-64-NEXT: movq %rax, %xmm089; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]90; SSE-64-NEXT: movdqa %xmm1, %xmm091; SSE-64-NEXT: retq92;93; AVX-32-LABEL: strict_vector_fptosi_v2f64_to_v2i64:94; AVX-32: # %bb.0:95; AVX-32-NEXT: pushl %ebp96; AVX-32-NEXT: .cfi_def_cfa_offset 897; AVX-32-NEXT: .cfi_offset %ebp, -898; AVX-32-NEXT: movl %esp, %ebp99; AVX-32-NEXT: .cfi_def_cfa_register %ebp100; AVX-32-NEXT: andl $-8, %esp101; AVX-32-NEXT: subl $16, %esp102; AVX-32-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)103; AVX-32-NEXT: vmovhps %xmm0, (%esp)104; AVX-32-NEXT: fldl {{[0-9]+}}(%esp)105; AVX-32-NEXT: fisttpll {{[0-9]+}}(%esp)106; AVX-32-NEXT: fldl (%esp)107; AVX-32-NEXT: fisttpll (%esp)108; AVX-32-NEXT: wait109; AVX-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero110; AVX-32-NEXT: vpinsrd $1, {{[0-9]+}}(%esp), %xmm0, %xmm0111; AVX-32-NEXT: vpinsrd $2, (%esp), %xmm0, %xmm0112; AVX-32-NEXT: vpinsrd $3, {{[0-9]+}}(%esp), %xmm0, %xmm0113; AVX-32-NEXT: movl %ebp, %esp114; AVX-32-NEXT: popl %ebp115; AVX-32-NEXT: .cfi_def_cfa %esp, 4116; AVX-32-NEXT: retl117;118; AVX-64-LABEL: strict_vector_fptosi_v2f64_to_v2i64:119; AVX-64: # %bb.0:120; AVX-64-NEXT: vcvttsd2si %xmm0, %rax121; AVX-64-NEXT: vmovq %rax, %xmm1122; AVX-64-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]123; AVX-64-NEXT: vcvttsd2si %xmm0, %rax124; AVX-64-NEXT: vmovq %rax, %xmm0125; AVX-64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]126; AVX-64-NEXT: retq127;128; AVX512F-32-LABEL: strict_vector_fptosi_v2f64_to_v2i64:129; AVX512F-32: # %bb.0:130; AVX512F-32-NEXT: pushl %ebp131; AVX512F-32-NEXT: .cfi_def_cfa_offset 8132; AVX512F-32-NEXT: .cfi_offset %ebp, -8133; AVX512F-32-NEXT: movl %esp, %ebp134; AVX512F-32-NEXT: .cfi_def_cfa_register %ebp135; AVX512F-32-NEXT: andl $-8, %esp136; AVX512F-32-NEXT: subl $16, %esp137; AVX512F-32-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)138; AVX512F-32-NEXT: vmovhps %xmm0, (%esp)139; AVX512F-32-NEXT: fldl {{[0-9]+}}(%esp)140; AVX512F-32-NEXT: fisttpll {{[0-9]+}}(%esp)141; AVX512F-32-NEXT: fldl (%esp)142; AVX512F-32-NEXT: fisttpll (%esp)143; AVX512F-32-NEXT: wait144; AVX512F-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero145; AVX512F-32-NEXT: vpinsrd $1, {{[0-9]+}}(%esp), %xmm0, %xmm0146; AVX512F-32-NEXT: vpinsrd $2, (%esp), %xmm0, %xmm0147; AVX512F-32-NEXT: vpinsrd $3, {{[0-9]+}}(%esp), %xmm0, %xmm0148; AVX512F-32-NEXT: movl %ebp, %esp149; AVX512F-32-NEXT: popl %ebp150; AVX512F-32-NEXT: .cfi_def_cfa %esp, 4151; AVX512F-32-NEXT: retl152;153; AVX512F-64-LABEL: strict_vector_fptosi_v2f64_to_v2i64:154; AVX512F-64: # %bb.0:155; AVX512F-64-NEXT: vcvttsd2si %xmm0, %rax156; AVX512F-64-NEXT: vmovq %rax, %xmm1157; AVX512F-64-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]158; AVX512F-64-NEXT: vcvttsd2si %xmm0, %rax159; AVX512F-64-NEXT: vmovq %rax, %xmm0160; AVX512F-64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]161; AVX512F-64-NEXT: retq162;163; AVX512VL-32-LABEL: strict_vector_fptosi_v2f64_to_v2i64:164; AVX512VL-32: # %bb.0:165; AVX512VL-32-NEXT: pushl %ebp166; AVX512VL-32-NEXT: .cfi_def_cfa_offset 8167; AVX512VL-32-NEXT: .cfi_offset %ebp, -8168; AVX512VL-32-NEXT: movl %esp, %ebp169; AVX512VL-32-NEXT: .cfi_def_cfa_register %ebp170; AVX512VL-32-NEXT: andl $-8, %esp171; AVX512VL-32-NEXT: subl $16, %esp172; AVX512VL-32-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)173; AVX512VL-32-NEXT: vmovhps %xmm0, (%esp)174; AVX512VL-32-NEXT: fldl {{[0-9]+}}(%esp)175; AVX512VL-32-NEXT: fisttpll {{[0-9]+}}(%esp)176; AVX512VL-32-NEXT: fldl (%esp)177; AVX512VL-32-NEXT: fisttpll (%esp)178; AVX512VL-32-NEXT: wait179; AVX512VL-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero180; AVX512VL-32-NEXT: vpinsrd $1, {{[0-9]+}}(%esp), %xmm0, %xmm0181; AVX512VL-32-NEXT: vpinsrd $2, (%esp), %xmm0, %xmm0182; AVX512VL-32-NEXT: vpinsrd $3, {{[0-9]+}}(%esp), %xmm0, %xmm0183; AVX512VL-32-NEXT: movl %ebp, %esp184; AVX512VL-32-NEXT: popl %ebp185; AVX512VL-32-NEXT: .cfi_def_cfa %esp, 4186; AVX512VL-32-NEXT: retl187;188; AVX512VL-64-LABEL: strict_vector_fptosi_v2f64_to_v2i64:189; AVX512VL-64: # %bb.0:190; AVX512VL-64-NEXT: vcvttsd2si %xmm0, %rax191; AVX512VL-64-NEXT: vmovq %rax, %xmm1192; AVX512VL-64-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]193; AVX512VL-64-NEXT: vcvttsd2si %xmm0, %rax194; AVX512VL-64-NEXT: vmovq %rax, %xmm0195; AVX512VL-64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]196; AVX512VL-64-NEXT: retq197;198; AVX512DQ-LABEL: strict_vector_fptosi_v2f64_to_v2i64:199; AVX512DQ: # %bb.0:200; AVX512DQ-NEXT: vmovaps %xmm0, %xmm0201; AVX512DQ-NEXT: vcvttpd2qq %zmm0, %zmm0202; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0203; AVX512DQ-NEXT: vzeroupper204; AVX512DQ-NEXT: ret{{[l|q]}}205;206; AVX512VLDQ-LABEL: strict_vector_fptosi_v2f64_to_v2i64:207; AVX512VLDQ: # %bb.0:208; AVX512VLDQ-NEXT: vcvttpd2qq %xmm0, %xmm0209; AVX512VLDQ-NEXT: ret{{[l|q]}}210 %ret = call <2 x i64> @llvm.experimental.constrained.fptosi.v2i64.v2f64(<2 x double> %a,211 metadata !"fpexcept.strict") #0212 ret <2 x i64> %ret213}214 215define <2 x i64> @strict_vector_fptoui_v2f64_to_v2i64(<2 x double> %a) #0 {216; SSE-32-LABEL: strict_vector_fptoui_v2f64_to_v2i64:217; SSE-32: # %bb.0:218; SSE-32-NEXT: pushl %ebp219; SSE-32-NEXT: .cfi_def_cfa_offset 8220; SSE-32-NEXT: .cfi_offset %ebp, -8221; SSE-32-NEXT: movl %esp, %ebp222; SSE-32-NEXT: .cfi_def_cfa_register %ebp223; SSE-32-NEXT: andl $-8, %esp224; SSE-32-NEXT: subl $24, %esp225; SSE-32-NEXT: movsd {{.*#+}} xmm1 = [9.2233720368547758E+18,0.0E+0]226; SSE-32-NEXT: comisd %xmm1, %xmm0227; SSE-32-NEXT: movapd %xmm1, %xmm2228; SSE-32-NEXT: jae .LBB1_2229; SSE-32-NEXT: # %bb.1:230; SSE-32-NEXT: xorpd %xmm2, %xmm2231; SSE-32-NEXT: .LBB1_2:232; SSE-32-NEXT: movapd %xmm0, %xmm3233; SSE-32-NEXT: subsd %xmm2, %xmm3234; SSE-32-NEXT: movsd %xmm3, {{[0-9]+}}(%esp)235; SSE-32-NEXT: setae %al236; SSE-32-NEXT: fldl {{[0-9]+}}(%esp)237; SSE-32-NEXT: wait238; SSE-32-NEXT: fnstcw {{[0-9]+}}(%esp)239; SSE-32-NEXT: movzwl {{[0-9]+}}(%esp), %ecx240; SSE-32-NEXT: orl $3072, %ecx # imm = 0xC00241; SSE-32-NEXT: movw %cx, {{[0-9]+}}(%esp)242; SSE-32-NEXT: fldcw {{[0-9]+}}(%esp)243; SSE-32-NEXT: fistpll {{[0-9]+}}(%esp)244; SSE-32-NEXT: fldcw {{[0-9]+}}(%esp)245; SSE-32-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]246; SSE-32-NEXT: comisd %xmm1, %xmm0247; SSE-32-NEXT: jae .LBB1_4248; SSE-32-NEXT: # %bb.3:249; SSE-32-NEXT: xorpd %xmm1, %xmm1250; SSE-32-NEXT: .LBB1_4:251; SSE-32-NEXT: subsd %xmm1, %xmm0252; SSE-32-NEXT: movsd %xmm0, {{[0-9]+}}(%esp)253; SSE-32-NEXT: setae %cl254; SSE-32-NEXT: fldl {{[0-9]+}}(%esp)255; SSE-32-NEXT: wait256; SSE-32-NEXT: fnstcw (%esp)257; SSE-32-NEXT: movzwl (%esp), %edx258; SSE-32-NEXT: orl $3072, %edx # imm = 0xC00259; SSE-32-NEXT: movw %dx, {{[0-9]+}}(%esp)260; SSE-32-NEXT: fldcw {{[0-9]+}}(%esp)261; SSE-32-NEXT: fistpll {{[0-9]+}}(%esp)262; SSE-32-NEXT: fldcw (%esp)263; SSE-32-NEXT: movzbl %al, %eax264; SSE-32-NEXT: shll $31, %eax265; SSE-32-NEXT: xorl {{[0-9]+}}(%esp), %eax266; SSE-32-NEXT: movd %eax, %xmm1267; SSE-32-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero268; SSE-32-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]269; SSE-32-NEXT: movzbl %cl, %eax270; SSE-32-NEXT: shll $31, %eax271; SSE-32-NEXT: xorl {{[0-9]+}}(%esp), %eax272; SSE-32-NEXT: movd %eax, %xmm1273; SSE-32-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero274; SSE-32-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]275; SSE-32-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]276; SSE-32-NEXT: movl %ebp, %esp277; SSE-32-NEXT: popl %ebp278; SSE-32-NEXT: .cfi_def_cfa %esp, 4279; SSE-32-NEXT: retl280;281; SSE-64-LABEL: strict_vector_fptoui_v2f64_to_v2i64:282; SSE-64: # %bb.0:283; SSE-64-NEXT: movsd {{.*#+}} xmm3 = [9.2233720368547758E+18,0.0E+0]284; SSE-64-NEXT: comisd %xmm3, %xmm0285; SSE-64-NEXT: xorpd %xmm2, %xmm2286; SSE-64-NEXT: xorpd %xmm1, %xmm1287; SSE-64-NEXT: jb .LBB1_2288; SSE-64-NEXT: # %bb.1:289; SSE-64-NEXT: movapd %xmm3, %xmm1290; SSE-64-NEXT: .LBB1_2:291; SSE-64-NEXT: movapd %xmm0, %xmm4292; SSE-64-NEXT: subsd %xmm1, %xmm4293; SSE-64-NEXT: cvttsd2si %xmm4, %rax294; SSE-64-NEXT: setae %cl295; SSE-64-NEXT: movzbl %cl, %ecx296; SSE-64-NEXT: shlq $63, %rcx297; SSE-64-NEXT: xorq %rax, %rcx298; SSE-64-NEXT: movq %rcx, %xmm1299; SSE-64-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]300; SSE-64-NEXT: comisd %xmm3, %xmm0301; SSE-64-NEXT: jb .LBB1_4302; SSE-64-NEXT: # %bb.3:303; SSE-64-NEXT: movapd %xmm3, %xmm2304; SSE-64-NEXT: .LBB1_4:305; SSE-64-NEXT: subsd %xmm2, %xmm0306; SSE-64-NEXT: cvttsd2si %xmm0, %rax307; SSE-64-NEXT: setae %cl308; SSE-64-NEXT: movzbl %cl, %ecx309; SSE-64-NEXT: shlq $63, %rcx310; SSE-64-NEXT: xorq %rax, %rcx311; SSE-64-NEXT: movq %rcx, %xmm0312; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]313; SSE-64-NEXT: movdqa %xmm1, %xmm0314; SSE-64-NEXT: retq315;316; AVX-32-LABEL: strict_vector_fptoui_v2f64_to_v2i64:317; AVX-32: # %bb.0:318; AVX-32-NEXT: pushl %ebp319; AVX-32-NEXT: .cfi_def_cfa_offset 8320; AVX-32-NEXT: .cfi_offset %ebp, -8321; AVX-32-NEXT: movl %esp, %ebp322; AVX-32-NEXT: .cfi_def_cfa_register %ebp323; AVX-32-NEXT: andl $-8, %esp324; AVX-32-NEXT: subl $16, %esp325; AVX-32-NEXT: vshufpd {{.*#+}} xmm2 = xmm0[1,0]326; AVX-32-NEXT: vmovsd {{.*#+}} xmm1 = [9.2233720368547758E+18,0.0E+0]327; AVX-32-NEXT: vcomisd %xmm1, %xmm2328; AVX-32-NEXT: vmovapd %xmm1, %xmm3329; AVX-32-NEXT: jae .LBB1_2330; AVX-32-NEXT: # %bb.1:331; AVX-32-NEXT: vxorpd %xmm3, %xmm3, %xmm3332; AVX-32-NEXT: .LBB1_2:333; AVX-32-NEXT: vsubsd %xmm3, %xmm2, %xmm2334; AVX-32-NEXT: vmovsd %xmm2, (%esp)335; AVX-32-NEXT: fldl (%esp)336; AVX-32-NEXT: fisttpll (%esp)337; AVX-32-NEXT: wait338; AVX-32-NEXT: setae %al339; AVX-32-NEXT: movzbl %al, %eax340; AVX-32-NEXT: shll $31, %eax341; AVX-32-NEXT: xorl {{[0-9]+}}(%esp), %eax342; AVX-32-NEXT: vcomisd %xmm1, %xmm0343; AVX-32-NEXT: jae .LBB1_4344; AVX-32-NEXT: # %bb.3:345; AVX-32-NEXT: vxorpd %xmm1, %xmm1, %xmm1346; AVX-32-NEXT: .LBB1_4:347; AVX-32-NEXT: vsubsd %xmm1, %xmm0, %xmm0348; AVX-32-NEXT: vmovsd %xmm0, {{[0-9]+}}(%esp)349; AVX-32-NEXT: fldl {{[0-9]+}}(%esp)350; AVX-32-NEXT: fisttpll {{[0-9]+}}(%esp)351; AVX-32-NEXT: wait352; AVX-32-NEXT: setae %cl353; AVX-32-NEXT: movzbl %cl, %ecx354; AVX-32-NEXT: shll $31, %ecx355; AVX-32-NEXT: xorl {{[0-9]+}}(%esp), %ecx356; AVX-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero357; AVX-32-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm0358; AVX-32-NEXT: vpinsrd $2, (%esp), %xmm0, %xmm0359; AVX-32-NEXT: vpinsrd $3, %eax, %xmm0, %xmm0360; AVX-32-NEXT: movl %ebp, %esp361; AVX-32-NEXT: popl %ebp362; AVX-32-NEXT: .cfi_def_cfa %esp, 4363; AVX-32-NEXT: retl364;365; AVX-64-LABEL: strict_vector_fptoui_v2f64_to_v2i64:366; AVX-64: # %bb.0:367; AVX-64-NEXT: vmovsd {{.*#+}} xmm1 = [9.2233720368547758E+18,0.0E+0]368; AVX-64-NEXT: vcomisd %xmm1, %xmm0369; AVX-64-NEXT: vxorpd %xmm2, %xmm2, %xmm2370; AVX-64-NEXT: vxorpd %xmm3, %xmm3, %xmm3371; AVX-64-NEXT: jb .LBB1_2372; AVX-64-NEXT: # %bb.1:373; AVX-64-NEXT: vmovapd %xmm1, %xmm3374; AVX-64-NEXT: .LBB1_2:375; AVX-64-NEXT: vsubsd %xmm3, %xmm0, %xmm3376; AVX-64-NEXT: vcvttsd2si %xmm3, %rax377; AVX-64-NEXT: setae %cl378; AVX-64-NEXT: movzbl %cl, %ecx379; AVX-64-NEXT: shlq $63, %rcx380; AVX-64-NEXT: xorq %rax, %rcx381; AVX-64-NEXT: vmovq %rcx, %xmm3382; AVX-64-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]383; AVX-64-NEXT: vcomisd %xmm1, %xmm0384; AVX-64-NEXT: jb .LBB1_4385; AVX-64-NEXT: # %bb.3:386; AVX-64-NEXT: vmovapd %xmm1, %xmm2387; AVX-64-NEXT: .LBB1_4:388; AVX-64-NEXT: vsubsd %xmm2, %xmm0, %xmm0389; AVX-64-NEXT: vcvttsd2si %xmm0, %rax390; AVX-64-NEXT: setae %cl391; AVX-64-NEXT: movzbl %cl, %ecx392; AVX-64-NEXT: shlq $63, %rcx393; AVX-64-NEXT: xorq %rax, %rcx394; AVX-64-NEXT: vmovq %rcx, %xmm0395; AVX-64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm3[0],xmm0[0]396; AVX-64-NEXT: retq397;398; AVX512F-32-LABEL: strict_vector_fptoui_v2f64_to_v2i64:399; AVX512F-32: # %bb.0:400; AVX512F-32-NEXT: pushl %ebp401; AVX512F-32-NEXT: .cfi_def_cfa_offset 8402; AVX512F-32-NEXT: .cfi_offset %ebp, -8403; AVX512F-32-NEXT: movl %esp, %ebp404; AVX512F-32-NEXT: .cfi_def_cfa_register %ebp405; AVX512F-32-NEXT: andl $-8, %esp406; AVX512F-32-NEXT: subl $16, %esp407; AVX512F-32-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]408; AVX512F-32-NEXT: vmovsd {{.*#+}} xmm2 = [9.2233720368547758E+18,0.0E+0]409; AVX512F-32-NEXT: xorl %eax, %eax410; AVX512F-32-NEXT: vcomisd %xmm2, %xmm1411; AVX512F-32-NEXT: setae %al412; AVX512F-32-NEXT: kmovw %eax, %k1413; AVX512F-32-NEXT: vmovsd %xmm2, %xmm2, %xmm3 {%k1} {z}414; AVX512F-32-NEXT: vsubsd %xmm3, %xmm1, %xmm1415; AVX512F-32-NEXT: vmovsd %xmm1, (%esp)416; AVX512F-32-NEXT: xorl %ecx, %ecx417; AVX512F-32-NEXT: vcomisd %xmm2, %xmm0418; AVX512F-32-NEXT: setae %cl419; AVX512F-32-NEXT: kmovw %ecx, %k1420; AVX512F-32-NEXT: vmovsd %xmm2, %xmm2, %xmm1 {%k1} {z}421; AVX512F-32-NEXT: vsubsd %xmm1, %xmm0, %xmm0422; AVX512F-32-NEXT: vmovsd %xmm0, {{[0-9]+}}(%esp)423; AVX512F-32-NEXT: fldl (%esp)424; AVX512F-32-NEXT: fisttpll (%esp)425; AVX512F-32-NEXT: fldl {{[0-9]+}}(%esp)426; AVX512F-32-NEXT: fisttpll {{[0-9]+}}(%esp)427; AVX512F-32-NEXT: wait428; AVX512F-32-NEXT: shll $31, %eax429; AVX512F-32-NEXT: xorl {{[0-9]+}}(%esp), %eax430; AVX512F-32-NEXT: shll $31, %ecx431; AVX512F-32-NEXT: xorl {{[0-9]+}}(%esp), %ecx432; AVX512F-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero433; AVX512F-32-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm0434; AVX512F-32-NEXT: vpinsrd $2, (%esp), %xmm0, %xmm0435; AVX512F-32-NEXT: vpinsrd $3, %eax, %xmm0, %xmm0436; AVX512F-32-NEXT: movl %ebp, %esp437; AVX512F-32-NEXT: popl %ebp438; AVX512F-32-NEXT: .cfi_def_cfa %esp, 4439; AVX512F-32-NEXT: retl440;441; AVX512F-64-LABEL: strict_vector_fptoui_v2f64_to_v2i64:442; AVX512F-64: # %bb.0:443; AVX512F-64-NEXT: vcvttsd2usi %xmm0, %rax444; AVX512F-64-NEXT: vmovq %rax, %xmm1445; AVX512F-64-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]446; AVX512F-64-NEXT: vcvttsd2usi %xmm0, %rax447; AVX512F-64-NEXT: vmovq %rax, %xmm0448; AVX512F-64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]449; AVX512F-64-NEXT: retq450;451; AVX512VL-32-LABEL: strict_vector_fptoui_v2f64_to_v2i64:452; AVX512VL-32: # %bb.0:453; AVX512VL-32-NEXT: pushl %ebp454; AVX512VL-32-NEXT: .cfi_def_cfa_offset 8455; AVX512VL-32-NEXT: .cfi_offset %ebp, -8456; AVX512VL-32-NEXT: movl %esp, %ebp457; AVX512VL-32-NEXT: .cfi_def_cfa_register %ebp458; AVX512VL-32-NEXT: andl $-8, %esp459; AVX512VL-32-NEXT: subl $16, %esp460; AVX512VL-32-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]461; AVX512VL-32-NEXT: vmovsd {{.*#+}} xmm2 = [9.2233720368547758E+18,0.0E+0]462; AVX512VL-32-NEXT: xorl %eax, %eax463; AVX512VL-32-NEXT: vcomisd %xmm2, %xmm1464; AVX512VL-32-NEXT: setae %al465; AVX512VL-32-NEXT: kmovw %eax, %k1466; AVX512VL-32-NEXT: vmovsd %xmm2, %xmm2, %xmm3 {%k1} {z}467; AVX512VL-32-NEXT: vsubsd %xmm3, %xmm1, %xmm1468; AVX512VL-32-NEXT: vmovsd %xmm1, (%esp)469; AVX512VL-32-NEXT: xorl %ecx, %ecx470; AVX512VL-32-NEXT: vcomisd %xmm2, %xmm0471; AVX512VL-32-NEXT: setae %cl472; AVX512VL-32-NEXT: kmovw %ecx, %k1473; AVX512VL-32-NEXT: vmovsd %xmm2, %xmm2, %xmm1 {%k1} {z}474; AVX512VL-32-NEXT: vsubsd %xmm1, %xmm0, %xmm0475; AVX512VL-32-NEXT: vmovsd %xmm0, {{[0-9]+}}(%esp)476; AVX512VL-32-NEXT: fldl (%esp)477; AVX512VL-32-NEXT: fisttpll (%esp)478; AVX512VL-32-NEXT: fldl {{[0-9]+}}(%esp)479; AVX512VL-32-NEXT: fisttpll {{[0-9]+}}(%esp)480; AVX512VL-32-NEXT: wait481; AVX512VL-32-NEXT: shll $31, %eax482; AVX512VL-32-NEXT: xorl {{[0-9]+}}(%esp), %eax483; AVX512VL-32-NEXT: shll $31, %ecx484; AVX512VL-32-NEXT: xorl {{[0-9]+}}(%esp), %ecx485; AVX512VL-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero486; AVX512VL-32-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm0487; AVX512VL-32-NEXT: vpinsrd $2, (%esp), %xmm0, %xmm0488; AVX512VL-32-NEXT: vpinsrd $3, %eax, %xmm0, %xmm0489; AVX512VL-32-NEXT: movl %ebp, %esp490; AVX512VL-32-NEXT: popl %ebp491; AVX512VL-32-NEXT: .cfi_def_cfa %esp, 4492; AVX512VL-32-NEXT: retl493;494; AVX512VL-64-LABEL: strict_vector_fptoui_v2f64_to_v2i64:495; AVX512VL-64: # %bb.0:496; AVX512VL-64-NEXT: vcvttsd2usi %xmm0, %rax497; AVX512VL-64-NEXT: vmovq %rax, %xmm1498; AVX512VL-64-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]499; AVX512VL-64-NEXT: vcvttsd2usi %xmm0, %rax500; AVX512VL-64-NEXT: vmovq %rax, %xmm0501; AVX512VL-64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]502; AVX512VL-64-NEXT: retq503;504; AVX512DQ-LABEL: strict_vector_fptoui_v2f64_to_v2i64:505; AVX512DQ: # %bb.0:506; AVX512DQ-NEXT: vmovaps %xmm0, %xmm0507; AVX512DQ-NEXT: vcvttpd2uqq %zmm0, %zmm0508; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0509; AVX512DQ-NEXT: vzeroupper510; AVX512DQ-NEXT: ret{{[l|q]}}511;512; AVX512VLDQ-LABEL: strict_vector_fptoui_v2f64_to_v2i64:513; AVX512VLDQ: # %bb.0:514; AVX512VLDQ-NEXT: vcvttpd2uqq %xmm0, %xmm0515; AVX512VLDQ-NEXT: ret{{[l|q]}}516 %ret = call <2 x i64> @llvm.experimental.constrained.fptoui.v2i64.v2f64(<2 x double> %a,517 metadata !"fpexcept.strict") #0518 ret <2 x i64> %ret519}520 521define <2 x i64> @strict_vector_fptosi_v2f32_to_v2i64(<2 x float> %a) #0 {522; SSE-32-LABEL: strict_vector_fptosi_v2f32_to_v2i64:523; SSE-32: # %bb.0:524; SSE-32-NEXT: pushl %ebp525; SSE-32-NEXT: .cfi_def_cfa_offset 8526; SSE-32-NEXT: .cfi_offset %ebp, -8527; SSE-32-NEXT: movl %esp, %ebp528; SSE-32-NEXT: .cfi_def_cfa_register %ebp529; SSE-32-NEXT: andl $-8, %esp530; SSE-32-NEXT: subl $24, %esp531; SSE-32-NEXT: movss %xmm0, {{[0-9]+}}(%esp)532; SSE-32-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]533; SSE-32-NEXT: movss %xmm0, {{[0-9]+}}(%esp)534; SSE-32-NEXT: flds {{[0-9]+}}(%esp)535; SSE-32-NEXT: wait536; SSE-32-NEXT: fnstcw {{[0-9]+}}(%esp)537; SSE-32-NEXT: movzwl {{[0-9]+}}(%esp), %eax538; SSE-32-NEXT: orl $3072, %eax # imm = 0xC00539; SSE-32-NEXT: movw %ax, {{[0-9]+}}(%esp)540; SSE-32-NEXT: fldcw {{[0-9]+}}(%esp)541; SSE-32-NEXT: fistpll {{[0-9]+}}(%esp)542; SSE-32-NEXT: fldcw {{[0-9]+}}(%esp)543; SSE-32-NEXT: flds {{[0-9]+}}(%esp)544; SSE-32-NEXT: wait545; SSE-32-NEXT: fnstcw (%esp)546; SSE-32-NEXT: movzwl (%esp), %eax547; SSE-32-NEXT: orl $3072, %eax # imm = 0xC00548; SSE-32-NEXT: movw %ax, {{[0-9]+}}(%esp)549; SSE-32-NEXT: fldcw {{[0-9]+}}(%esp)550; SSE-32-NEXT: fistpll {{[0-9]+}}(%esp)551; SSE-32-NEXT: fldcw (%esp)552; SSE-32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero553; SSE-32-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero554; SSE-32-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]555; SSE-32-NEXT: movl %ebp, %esp556; SSE-32-NEXT: popl %ebp557; SSE-32-NEXT: .cfi_def_cfa %esp, 4558; SSE-32-NEXT: retl559;560; SSE-64-LABEL: strict_vector_fptosi_v2f32_to_v2i64:561; SSE-64: # %bb.0:562; SSE-64-NEXT: cvttss2si %xmm0, %rax563; SSE-64-NEXT: movq %rax, %xmm1564; SSE-64-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]565; SSE-64-NEXT: cvttss2si %xmm0, %rax566; SSE-64-NEXT: movq %rax, %xmm0567; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]568; SSE-64-NEXT: movdqa %xmm1, %xmm0569; SSE-64-NEXT: retq570;571; AVX-32-LABEL: strict_vector_fptosi_v2f32_to_v2i64:572; AVX-32: # %bb.0:573; AVX-32-NEXT: pushl %ebp574; AVX-32-NEXT: .cfi_def_cfa_offset 8575; AVX-32-NEXT: .cfi_offset %ebp, -8576; AVX-32-NEXT: movl %esp, %ebp577; AVX-32-NEXT: .cfi_def_cfa_register %ebp578; AVX-32-NEXT: andl $-8, %esp579; AVX-32-NEXT: subl $16, %esp580; AVX-32-NEXT: vmovss %xmm0, (%esp)581; AVX-32-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp)582; AVX-32-NEXT: flds (%esp)583; AVX-32-NEXT: fisttpll (%esp)584; AVX-32-NEXT: flds {{[0-9]+}}(%esp)585; AVX-32-NEXT: fisttpll {{[0-9]+}}(%esp)586; AVX-32-NEXT: wait587; AVX-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero588; AVX-32-NEXT: vpinsrd $1, {{[0-9]+}}(%esp), %xmm0, %xmm0589; AVX-32-NEXT: vpinsrd $2, {{[0-9]+}}(%esp), %xmm0, %xmm0590; AVX-32-NEXT: vpinsrd $3, {{[0-9]+}}(%esp), %xmm0, %xmm0591; AVX-32-NEXT: movl %ebp, %esp592; AVX-32-NEXT: popl %ebp593; AVX-32-NEXT: .cfi_def_cfa %esp, 4594; AVX-32-NEXT: retl595;596; AVX-64-LABEL: strict_vector_fptosi_v2f32_to_v2i64:597; AVX-64: # %bb.0:598; AVX-64-NEXT: vcvttss2si %xmm0, %rax599; AVX-64-NEXT: vmovq %rax, %xmm1600; AVX-64-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]601; AVX-64-NEXT: vcvttss2si %xmm0, %rax602; AVX-64-NEXT: vmovq %rax, %xmm0603; AVX-64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]604; AVX-64-NEXT: retq605;606; AVX512F-32-LABEL: strict_vector_fptosi_v2f32_to_v2i64:607; AVX512F-32: # %bb.0:608; AVX512F-32-NEXT: pushl %ebp609; AVX512F-32-NEXT: .cfi_def_cfa_offset 8610; AVX512F-32-NEXT: .cfi_offset %ebp, -8611; AVX512F-32-NEXT: movl %esp, %ebp612; AVX512F-32-NEXT: .cfi_def_cfa_register %ebp613; AVX512F-32-NEXT: andl $-8, %esp614; AVX512F-32-NEXT: subl $16, %esp615; AVX512F-32-NEXT: vmovd %xmm0, (%esp)616; AVX512F-32-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp)617; AVX512F-32-NEXT: flds (%esp)618; AVX512F-32-NEXT: fisttpll (%esp)619; AVX512F-32-NEXT: flds {{[0-9]+}}(%esp)620; AVX512F-32-NEXT: fisttpll {{[0-9]+}}(%esp)621; AVX512F-32-NEXT: wait622; AVX512F-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero623; AVX512F-32-NEXT: vpinsrd $1, {{[0-9]+}}(%esp), %xmm0, %xmm0624; AVX512F-32-NEXT: vpinsrd $2, {{[0-9]+}}(%esp), %xmm0, %xmm0625; AVX512F-32-NEXT: vpinsrd $3, {{[0-9]+}}(%esp), %xmm0, %xmm0626; AVX512F-32-NEXT: movl %ebp, %esp627; AVX512F-32-NEXT: popl %ebp628; AVX512F-32-NEXT: .cfi_def_cfa %esp, 4629; AVX512F-32-NEXT: retl630;631; AVX512F-64-LABEL: strict_vector_fptosi_v2f32_to_v2i64:632; AVX512F-64: # %bb.0:633; AVX512F-64-NEXT: vcvttss2si %xmm0, %rax634; AVX512F-64-NEXT: vmovq %rax, %xmm1635; AVX512F-64-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]636; AVX512F-64-NEXT: vcvttss2si %xmm0, %rax637; AVX512F-64-NEXT: vmovq %rax, %xmm0638; AVX512F-64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]639; AVX512F-64-NEXT: retq640;641; AVX512VL-32-LABEL: strict_vector_fptosi_v2f32_to_v2i64:642; AVX512VL-32: # %bb.0:643; AVX512VL-32-NEXT: pushl %ebp644; AVX512VL-32-NEXT: .cfi_def_cfa_offset 8645; AVX512VL-32-NEXT: .cfi_offset %ebp, -8646; AVX512VL-32-NEXT: movl %esp, %ebp647; AVX512VL-32-NEXT: .cfi_def_cfa_register %ebp648; AVX512VL-32-NEXT: andl $-8, %esp649; AVX512VL-32-NEXT: subl $16, %esp650; AVX512VL-32-NEXT: vmovd %xmm0, (%esp)651; AVX512VL-32-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp)652; AVX512VL-32-NEXT: flds (%esp)653; AVX512VL-32-NEXT: fisttpll (%esp)654; AVX512VL-32-NEXT: flds {{[0-9]+}}(%esp)655; AVX512VL-32-NEXT: fisttpll {{[0-9]+}}(%esp)656; AVX512VL-32-NEXT: wait657; AVX512VL-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero658; AVX512VL-32-NEXT: vpinsrd $1, {{[0-9]+}}(%esp), %xmm0, %xmm0659; AVX512VL-32-NEXT: vpinsrd $2, {{[0-9]+}}(%esp), %xmm0, %xmm0660; AVX512VL-32-NEXT: vpinsrd $3, {{[0-9]+}}(%esp), %xmm0, %xmm0661; AVX512VL-32-NEXT: movl %ebp, %esp662; AVX512VL-32-NEXT: popl %ebp663; AVX512VL-32-NEXT: .cfi_def_cfa %esp, 4664; AVX512VL-32-NEXT: retl665;666; AVX512VL-64-LABEL: strict_vector_fptosi_v2f32_to_v2i64:667; AVX512VL-64: # %bb.0:668; AVX512VL-64-NEXT: vcvttss2si %xmm0, %rax669; AVX512VL-64-NEXT: vmovq %rax, %xmm1670; AVX512VL-64-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]671; AVX512VL-64-NEXT: vcvttss2si %xmm0, %rax672; AVX512VL-64-NEXT: vmovq %rax, %xmm0673; AVX512VL-64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]674; AVX512VL-64-NEXT: retq675;676; AVX512DQ-LABEL: strict_vector_fptosi_v2f32_to_v2i64:677; AVX512DQ: # %bb.0:678; AVX512DQ-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero679; AVX512DQ-NEXT: vcvttps2qq %ymm0, %zmm0680; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0681; AVX512DQ-NEXT: vzeroupper682; AVX512DQ-NEXT: ret{{[l|q]}}683;684; AVX512VLDQ-LABEL: strict_vector_fptosi_v2f32_to_v2i64:685; AVX512VLDQ: # %bb.0:686; AVX512VLDQ-NEXT: vcvttps2qq %xmm0, %xmm0687; AVX512VLDQ-NEXT: ret{{[l|q]}}688 %ret = call <2 x i64> @llvm.experimental.constrained.fptosi.v2i64.v2f32(<2 x float> %a,689 metadata !"fpexcept.strict") #0690 ret <2 x i64> %ret691}692 693define <2 x i64> @strict_vector_fptosi_v2f32_to_v2i64_load128(ptr %x) strictfp {694; SSE-32-LABEL: strict_vector_fptosi_v2f32_to_v2i64_load128:695; SSE-32: # %bb.0:696; SSE-32-NEXT: pushl %ebp697; SSE-32-NEXT: .cfi_def_cfa_offset 8698; SSE-32-NEXT: .cfi_offset %ebp, -8699; SSE-32-NEXT: movl %esp, %ebp700; SSE-32-NEXT: .cfi_def_cfa_register %ebp701; SSE-32-NEXT: andl $-8, %esp702; SSE-32-NEXT: subl $24, %esp703; SSE-32-NEXT: movl 8(%ebp), %eax704; SSE-32-NEXT: movaps (%eax), %xmm0705; SSE-32-NEXT: movss %xmm0, {{[0-9]+}}(%esp)706; SSE-32-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]707; SSE-32-NEXT: movss %xmm0, {{[0-9]+}}(%esp)708; SSE-32-NEXT: flds {{[0-9]+}}(%esp)709; SSE-32-NEXT: wait710; SSE-32-NEXT: fnstcw {{[0-9]+}}(%esp)711; SSE-32-NEXT: movzwl {{[0-9]+}}(%esp), %eax712; SSE-32-NEXT: orl $3072, %eax # imm = 0xC00713; SSE-32-NEXT: movw %ax, {{[0-9]+}}(%esp)714; SSE-32-NEXT: fldcw {{[0-9]+}}(%esp)715; SSE-32-NEXT: fistpll {{[0-9]+}}(%esp)716; SSE-32-NEXT: fldcw {{[0-9]+}}(%esp)717; SSE-32-NEXT: flds {{[0-9]+}}(%esp)718; SSE-32-NEXT: wait719; SSE-32-NEXT: fnstcw (%esp)720; SSE-32-NEXT: movzwl (%esp), %eax721; SSE-32-NEXT: orl $3072, %eax # imm = 0xC00722; SSE-32-NEXT: movw %ax, {{[0-9]+}}(%esp)723; SSE-32-NEXT: fldcw {{[0-9]+}}(%esp)724; SSE-32-NEXT: fistpll {{[0-9]+}}(%esp)725; SSE-32-NEXT: fldcw (%esp)726; SSE-32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero727; SSE-32-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero728; SSE-32-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]729; SSE-32-NEXT: movl %ebp, %esp730; SSE-32-NEXT: popl %ebp731; SSE-32-NEXT: .cfi_def_cfa %esp, 4732; SSE-32-NEXT: retl733;734; SSE-64-LABEL: strict_vector_fptosi_v2f32_to_v2i64_load128:735; SSE-64: # %bb.0:736; SSE-64-NEXT: movaps (%rdi), %xmm1737; SSE-64-NEXT: cvttss2si %xmm1, %rax738; SSE-64-NEXT: movq %rax, %xmm0739; SSE-64-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,1,1]740; SSE-64-NEXT: cvttss2si %xmm1, %rax741; SSE-64-NEXT: movq %rax, %xmm1742; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]743; SSE-64-NEXT: retq744;745; AVX-32-LABEL: strict_vector_fptosi_v2f32_to_v2i64_load128:746; AVX-32: # %bb.0:747; AVX-32-NEXT: pushl %ebp748; AVX-32-NEXT: .cfi_def_cfa_offset 8749; AVX-32-NEXT: .cfi_offset %ebp, -8750; AVX-32-NEXT: movl %esp, %ebp751; AVX-32-NEXT: .cfi_def_cfa_register %ebp752; AVX-32-NEXT: andl $-8, %esp753; AVX-32-NEXT: subl $16, %esp754; AVX-32-NEXT: movl 8(%ebp), %eax755; AVX-32-NEXT: vmovaps (%eax), %xmm0756; AVX-32-NEXT: vmovss %xmm0, (%esp)757; AVX-32-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp)758; AVX-32-NEXT: flds (%esp)759; AVX-32-NEXT: fisttpll (%esp)760; AVX-32-NEXT: flds {{[0-9]+}}(%esp)761; AVX-32-NEXT: fisttpll {{[0-9]+}}(%esp)762; AVX-32-NEXT: wait763; AVX-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero764; AVX-32-NEXT: vpinsrd $1, {{[0-9]+}}(%esp), %xmm0, %xmm0765; AVX-32-NEXT: vpinsrd $2, {{[0-9]+}}(%esp), %xmm0, %xmm0766; AVX-32-NEXT: vpinsrd $3, {{[0-9]+}}(%esp), %xmm0, %xmm0767; AVX-32-NEXT: movl %ebp, %esp768; AVX-32-NEXT: popl %ebp769; AVX-32-NEXT: .cfi_def_cfa %esp, 4770; AVX-32-NEXT: retl771;772; AVX-64-LABEL: strict_vector_fptosi_v2f32_to_v2i64_load128:773; AVX-64: # %bb.0:774; AVX-64-NEXT: vcvttss2si 4(%rdi), %rax775; AVX-64-NEXT: vmovq %rax, %xmm0776; AVX-64-NEXT: vcvttss2si (%rdi), %rax777; AVX-64-NEXT: vmovq %rax, %xmm1778; AVX-64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]779; AVX-64-NEXT: retq780;781; AVX512F-32-LABEL: strict_vector_fptosi_v2f32_to_v2i64_load128:782; AVX512F-32: # %bb.0:783; AVX512F-32-NEXT: pushl %ebp784; AVX512F-32-NEXT: .cfi_def_cfa_offset 8785; AVX512F-32-NEXT: .cfi_offset %ebp, -8786; AVX512F-32-NEXT: movl %esp, %ebp787; AVX512F-32-NEXT: .cfi_def_cfa_register %ebp788; AVX512F-32-NEXT: andl $-8, %esp789; AVX512F-32-NEXT: subl $16, %esp790; AVX512F-32-NEXT: movl 8(%ebp), %eax791; AVX512F-32-NEXT: vmovdqa (%eax), %xmm0792; AVX512F-32-NEXT: vmovd %xmm0, (%esp)793; AVX512F-32-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp)794; AVX512F-32-NEXT: flds (%esp)795; AVX512F-32-NEXT: fisttpll (%esp)796; AVX512F-32-NEXT: flds {{[0-9]+}}(%esp)797; AVX512F-32-NEXT: fisttpll {{[0-9]+}}(%esp)798; AVX512F-32-NEXT: wait799; AVX512F-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero800; AVX512F-32-NEXT: vpinsrd $1, {{[0-9]+}}(%esp), %xmm0, %xmm0801; AVX512F-32-NEXT: vpinsrd $2, {{[0-9]+}}(%esp), %xmm0, %xmm0802; AVX512F-32-NEXT: vpinsrd $3, {{[0-9]+}}(%esp), %xmm0, %xmm0803; AVX512F-32-NEXT: movl %ebp, %esp804; AVX512F-32-NEXT: popl %ebp805; AVX512F-32-NEXT: .cfi_def_cfa %esp, 4806; AVX512F-32-NEXT: retl807;808; AVX512F-64-LABEL: strict_vector_fptosi_v2f32_to_v2i64_load128:809; AVX512F-64: # %bb.0:810; AVX512F-64-NEXT: vcvttss2si 4(%rdi), %rax811; AVX512F-64-NEXT: vmovq %rax, %xmm0812; AVX512F-64-NEXT: vcvttss2si (%rdi), %rax813; AVX512F-64-NEXT: vmovq %rax, %xmm1814; AVX512F-64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]815; AVX512F-64-NEXT: retq816;817; AVX512VL-32-LABEL: strict_vector_fptosi_v2f32_to_v2i64_load128:818; AVX512VL-32: # %bb.0:819; AVX512VL-32-NEXT: pushl %ebp820; AVX512VL-32-NEXT: .cfi_def_cfa_offset 8821; AVX512VL-32-NEXT: .cfi_offset %ebp, -8822; AVX512VL-32-NEXT: movl %esp, %ebp823; AVX512VL-32-NEXT: .cfi_def_cfa_register %ebp824; AVX512VL-32-NEXT: andl $-8, %esp825; AVX512VL-32-NEXT: subl $16, %esp826; AVX512VL-32-NEXT: movl 8(%ebp), %eax827; AVX512VL-32-NEXT: vmovdqa (%eax), %xmm0828; AVX512VL-32-NEXT: vmovd %xmm0, (%esp)829; AVX512VL-32-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp)830; AVX512VL-32-NEXT: flds (%esp)831; AVX512VL-32-NEXT: fisttpll (%esp)832; AVX512VL-32-NEXT: flds {{[0-9]+}}(%esp)833; AVX512VL-32-NEXT: fisttpll {{[0-9]+}}(%esp)834; AVX512VL-32-NEXT: wait835; AVX512VL-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero836; AVX512VL-32-NEXT: vpinsrd $1, {{[0-9]+}}(%esp), %xmm0, %xmm0837; AVX512VL-32-NEXT: vpinsrd $2, {{[0-9]+}}(%esp), %xmm0, %xmm0838; AVX512VL-32-NEXT: vpinsrd $3, {{[0-9]+}}(%esp), %xmm0, %xmm0839; AVX512VL-32-NEXT: movl %ebp, %esp840; AVX512VL-32-NEXT: popl %ebp841; AVX512VL-32-NEXT: .cfi_def_cfa %esp, 4842; AVX512VL-32-NEXT: retl843;844; AVX512VL-64-LABEL: strict_vector_fptosi_v2f32_to_v2i64_load128:845; AVX512VL-64: # %bb.0:846; AVX512VL-64-NEXT: vcvttss2si 4(%rdi), %rax847; AVX512VL-64-NEXT: vmovq %rax, %xmm0848; AVX512VL-64-NEXT: vcvttss2si (%rdi), %rax849; AVX512VL-64-NEXT: vmovq %rax, %xmm1850; AVX512VL-64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]851; AVX512VL-64-NEXT: retq852;853; AVX512DQ-32-LABEL: strict_vector_fptosi_v2f32_to_v2i64_load128:854; AVX512DQ-32: # %bb.0:855; AVX512DQ-32-NEXT: movl {{[0-9]+}}(%esp), %eax856; AVX512DQ-32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero857; AVX512DQ-32-NEXT: vcvttps2qq %ymm0, %zmm0858; AVX512DQ-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0859; AVX512DQ-32-NEXT: vzeroupper860; AVX512DQ-32-NEXT: retl861;862; AVX512DQ-64-LABEL: strict_vector_fptosi_v2f32_to_v2i64_load128:863; AVX512DQ-64: # %bb.0:864; AVX512DQ-64-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero865; AVX512DQ-64-NEXT: vcvttps2qq %ymm0, %zmm0866; AVX512DQ-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0867; AVX512DQ-64-NEXT: vzeroupper868; AVX512DQ-64-NEXT: retq869;870; AVX512VLDQ-32-LABEL: strict_vector_fptosi_v2f32_to_v2i64_load128:871; AVX512VLDQ-32: # %bb.0:872; AVX512VLDQ-32-NEXT: movl {{[0-9]+}}(%esp), %eax873; AVX512VLDQ-32-NEXT: vcvttps2qq (%eax), %xmm0874; AVX512VLDQ-32-NEXT: retl875;876; AVX512VLDQ-64-LABEL: strict_vector_fptosi_v2f32_to_v2i64_load128:877; AVX512VLDQ-64: # %bb.0:878; AVX512VLDQ-64-NEXT: vcvttps2qq (%rdi), %xmm0879; AVX512VLDQ-64-NEXT: retq880 %a = load <4 x float>, ptr %x881 %b = shufflevector <4 x float> %a, <4 x float> undef, <2 x i32> <i32 0, i32 1>882 %c = call <2 x i64> @llvm.experimental.constrained.fptosi.v2i64.v2f32(<2 x float> %b, metadata !"fpexcept.strict") #0883 ret <2 x i64> %c884}885 886define <2 x i64> @strict_vector_fptoui_v2f32_to_v2i64(<2 x float> %a) #0 {887; SSE-32-LABEL: strict_vector_fptoui_v2f32_to_v2i64:888; SSE-32: # %bb.0:889; SSE-32-NEXT: pushl %ebp890; SSE-32-NEXT: .cfi_def_cfa_offset 8891; SSE-32-NEXT: .cfi_offset %ebp, -8892; SSE-32-NEXT: movl %esp, %ebp893; SSE-32-NEXT: .cfi_def_cfa_register %ebp894; SSE-32-NEXT: andl $-8, %esp895; SSE-32-NEXT: subl $24, %esp896; SSE-32-NEXT: movss {{.*#+}} xmm1 = [9.22337203E+18,0.0E+0,0.0E+0,0.0E+0]897; SSE-32-NEXT: comiss %xmm1, %xmm0898; SSE-32-NEXT: movaps %xmm1, %xmm2899; SSE-32-NEXT: jae .LBB4_2900; SSE-32-NEXT: # %bb.1:901; SSE-32-NEXT: xorps %xmm2, %xmm2902; SSE-32-NEXT: .LBB4_2:903; SSE-32-NEXT: movaps %xmm0, %xmm3904; SSE-32-NEXT: subss %xmm2, %xmm3905; SSE-32-NEXT: movss %xmm3, {{[0-9]+}}(%esp)906; SSE-32-NEXT: setae %al907; SSE-32-NEXT: flds {{[0-9]+}}(%esp)908; SSE-32-NEXT: wait909; SSE-32-NEXT: fnstcw {{[0-9]+}}(%esp)910; SSE-32-NEXT: movzwl {{[0-9]+}}(%esp), %ecx911; SSE-32-NEXT: orl $3072, %ecx # imm = 0xC00912; SSE-32-NEXT: movw %cx, {{[0-9]+}}(%esp)913; SSE-32-NEXT: fldcw {{[0-9]+}}(%esp)914; SSE-32-NEXT: fistpll {{[0-9]+}}(%esp)915; SSE-32-NEXT: fldcw {{[0-9]+}}(%esp)916; SSE-32-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]917; SSE-32-NEXT: comiss %xmm1, %xmm0918; SSE-32-NEXT: jae .LBB4_4919; SSE-32-NEXT: # %bb.3:920; SSE-32-NEXT: xorps %xmm1, %xmm1921; SSE-32-NEXT: .LBB4_4:922; SSE-32-NEXT: subss %xmm1, %xmm0923; SSE-32-NEXT: movss %xmm0, {{[0-9]+}}(%esp)924; SSE-32-NEXT: setae %cl925; SSE-32-NEXT: flds {{[0-9]+}}(%esp)926; SSE-32-NEXT: wait927; SSE-32-NEXT: fnstcw (%esp)928; SSE-32-NEXT: movzwl (%esp), %edx929; SSE-32-NEXT: orl $3072, %edx # imm = 0xC00930; SSE-32-NEXT: movw %dx, {{[0-9]+}}(%esp)931; SSE-32-NEXT: fldcw {{[0-9]+}}(%esp)932; SSE-32-NEXT: fistpll {{[0-9]+}}(%esp)933; SSE-32-NEXT: fldcw (%esp)934; SSE-32-NEXT: movzbl %al, %eax935; SSE-32-NEXT: shll $31, %eax936; SSE-32-NEXT: xorl {{[0-9]+}}(%esp), %eax937; SSE-32-NEXT: movd %eax, %xmm1938; SSE-32-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero939; SSE-32-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]940; SSE-32-NEXT: movzbl %cl, %eax941; SSE-32-NEXT: shll $31, %eax942; SSE-32-NEXT: xorl {{[0-9]+}}(%esp), %eax943; SSE-32-NEXT: movd %eax, %xmm1944; SSE-32-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero945; SSE-32-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]946; SSE-32-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]947; SSE-32-NEXT: movl %ebp, %esp948; SSE-32-NEXT: popl %ebp949; SSE-32-NEXT: .cfi_def_cfa %esp, 4950; SSE-32-NEXT: retl951;952; SSE-64-LABEL: strict_vector_fptoui_v2f32_to_v2i64:953; SSE-64: # %bb.0:954; SSE-64-NEXT: movss {{.*#+}} xmm3 = [9.22337203E+18,0.0E+0,0.0E+0,0.0E+0]955; SSE-64-NEXT: comiss %xmm3, %xmm0956; SSE-64-NEXT: xorps %xmm2, %xmm2957; SSE-64-NEXT: xorps %xmm1, %xmm1958; SSE-64-NEXT: jb .LBB4_2959; SSE-64-NEXT: # %bb.1:960; SSE-64-NEXT: movaps %xmm3, %xmm1961; SSE-64-NEXT: .LBB4_2:962; SSE-64-NEXT: movaps %xmm0, %xmm4963; SSE-64-NEXT: subss %xmm1, %xmm4964; SSE-64-NEXT: cvttss2si %xmm4, %rax965; SSE-64-NEXT: setae %cl966; SSE-64-NEXT: movzbl %cl, %ecx967; SSE-64-NEXT: shlq $63, %rcx968; SSE-64-NEXT: xorq %rax, %rcx969; SSE-64-NEXT: movq %rcx, %xmm1970; SSE-64-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]971; SSE-64-NEXT: comiss %xmm3, %xmm0972; SSE-64-NEXT: jb .LBB4_4973; SSE-64-NEXT: # %bb.3:974; SSE-64-NEXT: movaps %xmm3, %xmm2975; SSE-64-NEXT: .LBB4_4:976; SSE-64-NEXT: subss %xmm2, %xmm0977; SSE-64-NEXT: cvttss2si %xmm0, %rax978; SSE-64-NEXT: setae %cl979; SSE-64-NEXT: movzbl %cl, %ecx980; SSE-64-NEXT: shlq $63, %rcx981; SSE-64-NEXT: xorq %rax, %rcx982; SSE-64-NEXT: movq %rcx, %xmm0983; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]984; SSE-64-NEXT: movdqa %xmm1, %xmm0985; SSE-64-NEXT: retq986;987; AVX-32-LABEL: strict_vector_fptoui_v2f32_to_v2i64:988; AVX-32: # %bb.0:989; AVX-32-NEXT: pushl %ebp990; AVX-32-NEXT: .cfi_def_cfa_offset 8991; AVX-32-NEXT: .cfi_offset %ebp, -8992; AVX-32-NEXT: movl %esp, %ebp993; AVX-32-NEXT: .cfi_def_cfa_register %ebp994; AVX-32-NEXT: andl $-8, %esp995; AVX-32-NEXT: subl $16, %esp996; AVX-32-NEXT: vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]997; AVX-32-NEXT: vmovss {{.*#+}} xmm1 = [9.22337203E+18,0.0E+0,0.0E+0,0.0E+0]998; AVX-32-NEXT: vcomiss %xmm1, %xmm2999; AVX-32-NEXT: vmovaps %xmm1, %xmm31000; AVX-32-NEXT: jae .LBB4_21001; AVX-32-NEXT: # %bb.1:1002; AVX-32-NEXT: vxorps %xmm3, %xmm3, %xmm31003; AVX-32-NEXT: .LBB4_2:1004; AVX-32-NEXT: vsubss %xmm3, %xmm2, %xmm21005; AVX-32-NEXT: vmovss %xmm2, {{[0-9]+}}(%esp)1006; AVX-32-NEXT: flds {{[0-9]+}}(%esp)1007; AVX-32-NEXT: fisttpll {{[0-9]+}}(%esp)1008; AVX-32-NEXT: wait1009; AVX-32-NEXT: setae %al1010; AVX-32-NEXT: movzbl %al, %eax1011; AVX-32-NEXT: shll $31, %eax1012; AVX-32-NEXT: xorl {{[0-9]+}}(%esp), %eax1013; AVX-32-NEXT: vcomiss %xmm1, %xmm01014; AVX-32-NEXT: jae .LBB4_41015; AVX-32-NEXT: # %bb.3:1016; AVX-32-NEXT: vxorps %xmm1, %xmm1, %xmm11017; AVX-32-NEXT: .LBB4_4:1018; AVX-32-NEXT: vsubss %xmm1, %xmm0, %xmm01019; AVX-32-NEXT: vmovss %xmm0, (%esp)1020; AVX-32-NEXT: flds (%esp)1021; AVX-32-NEXT: fisttpll (%esp)1022; AVX-32-NEXT: wait1023; AVX-32-NEXT: setae %cl1024; AVX-32-NEXT: movzbl %cl, %ecx1025; AVX-32-NEXT: shll $31, %ecx1026; AVX-32-NEXT: xorl {{[0-9]+}}(%esp), %ecx1027; AVX-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero1028; AVX-32-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm01029; AVX-32-NEXT: vpinsrd $2, {{[0-9]+}}(%esp), %xmm0, %xmm01030; AVX-32-NEXT: vpinsrd $3, %eax, %xmm0, %xmm01031; AVX-32-NEXT: movl %ebp, %esp1032; AVX-32-NEXT: popl %ebp1033; AVX-32-NEXT: .cfi_def_cfa %esp, 41034; AVX-32-NEXT: retl1035;1036; AVX-64-LABEL: strict_vector_fptoui_v2f32_to_v2i64:1037; AVX-64: # %bb.0:1038; AVX-64-NEXT: vmovss {{.*#+}} xmm1 = [9.22337203E+18,0.0E+0,0.0E+0,0.0E+0]1039; AVX-64-NEXT: vcomiss %xmm1, %xmm01040; AVX-64-NEXT: vxorps %xmm2, %xmm2, %xmm21041; AVX-64-NEXT: vxorps %xmm3, %xmm3, %xmm31042; AVX-64-NEXT: jb .LBB4_21043; AVX-64-NEXT: # %bb.1:1044; AVX-64-NEXT: vmovaps %xmm1, %xmm31045; AVX-64-NEXT: .LBB4_2:1046; AVX-64-NEXT: vsubss %xmm3, %xmm0, %xmm31047; AVX-64-NEXT: vcvttss2si %xmm3, %rax1048; AVX-64-NEXT: setae %cl1049; AVX-64-NEXT: movzbl %cl, %ecx1050; AVX-64-NEXT: shlq $63, %rcx1051; AVX-64-NEXT: xorq %rax, %rcx1052; AVX-64-NEXT: vmovq %rcx, %xmm31053; AVX-64-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]1054; AVX-64-NEXT: vcomiss %xmm1, %xmm01055; AVX-64-NEXT: jb .LBB4_41056; AVX-64-NEXT: # %bb.3:1057; AVX-64-NEXT: vmovaps %xmm1, %xmm21058; AVX-64-NEXT: .LBB4_4:1059; AVX-64-NEXT: vsubss %xmm2, %xmm0, %xmm01060; AVX-64-NEXT: vcvttss2si %xmm0, %rax1061; AVX-64-NEXT: setae %cl1062; AVX-64-NEXT: movzbl %cl, %ecx1063; AVX-64-NEXT: shlq $63, %rcx1064; AVX-64-NEXT: xorq %rax, %rcx1065; AVX-64-NEXT: vmovq %rcx, %xmm01066; AVX-64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm3[0],xmm0[0]1067; AVX-64-NEXT: retq1068;1069; AVX512F-32-LABEL: strict_vector_fptoui_v2f32_to_v2i64:1070; AVX512F-32: # %bb.0:1071; AVX512F-32-NEXT: pushl %ebp1072; AVX512F-32-NEXT: .cfi_def_cfa_offset 81073; AVX512F-32-NEXT: .cfi_offset %ebp, -81074; AVX512F-32-NEXT: movl %esp, %ebp1075; AVX512F-32-NEXT: .cfi_def_cfa_register %ebp1076; AVX512F-32-NEXT: andl $-8, %esp1077; AVX512F-32-NEXT: subl $16, %esp1078; AVX512F-32-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]1079; AVX512F-32-NEXT: vmovss {{.*#+}} xmm2 = [9.22337203E+18,0.0E+0,0.0E+0,0.0E+0]1080; AVX512F-32-NEXT: xorl %eax, %eax1081; AVX512F-32-NEXT: vcomiss %xmm2, %xmm11082; AVX512F-32-NEXT: setae %al1083; AVX512F-32-NEXT: kmovw %eax, %k11084; AVX512F-32-NEXT: vmovss %xmm2, %xmm2, %xmm3 {%k1} {z}1085; AVX512F-32-NEXT: vsubss %xmm3, %xmm1, %xmm11086; AVX512F-32-NEXT: vmovss %xmm1, {{[0-9]+}}(%esp)1087; AVX512F-32-NEXT: xorl %ecx, %ecx1088; AVX512F-32-NEXT: vcomiss %xmm2, %xmm01089; AVX512F-32-NEXT: setae %cl1090; AVX512F-32-NEXT: kmovw %ecx, %k11091; AVX512F-32-NEXT: vmovss %xmm2, %xmm2, %xmm1 {%k1} {z}1092; AVX512F-32-NEXT: vsubss %xmm1, %xmm0, %xmm01093; AVX512F-32-NEXT: vmovss %xmm0, (%esp)1094; AVX512F-32-NEXT: flds {{[0-9]+}}(%esp)1095; AVX512F-32-NEXT: fisttpll {{[0-9]+}}(%esp)1096; AVX512F-32-NEXT: flds (%esp)1097; AVX512F-32-NEXT: fisttpll (%esp)1098; AVX512F-32-NEXT: wait1099; AVX512F-32-NEXT: shll $31, %eax1100; AVX512F-32-NEXT: xorl {{[0-9]+}}(%esp), %eax1101; AVX512F-32-NEXT: shll $31, %ecx1102; AVX512F-32-NEXT: xorl {{[0-9]+}}(%esp), %ecx1103; AVX512F-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero1104; AVX512F-32-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm01105; AVX512F-32-NEXT: vpinsrd $2, {{[0-9]+}}(%esp), %xmm0, %xmm01106; AVX512F-32-NEXT: vpinsrd $3, %eax, %xmm0, %xmm01107; AVX512F-32-NEXT: movl %ebp, %esp1108; AVX512F-32-NEXT: popl %ebp1109; AVX512F-32-NEXT: .cfi_def_cfa %esp, 41110; AVX512F-32-NEXT: retl1111;1112; AVX512F-64-LABEL: strict_vector_fptoui_v2f32_to_v2i64:1113; AVX512F-64: # %bb.0:1114; AVX512F-64-NEXT: vcvttss2usi %xmm0, %rax1115; AVX512F-64-NEXT: vmovq %rax, %xmm11116; AVX512F-64-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]1117; AVX512F-64-NEXT: vcvttss2usi %xmm0, %rax1118; AVX512F-64-NEXT: vmovq %rax, %xmm01119; AVX512F-64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]1120; AVX512F-64-NEXT: retq1121;1122; AVX512VL-32-LABEL: strict_vector_fptoui_v2f32_to_v2i64:1123; AVX512VL-32: # %bb.0:1124; AVX512VL-32-NEXT: pushl %ebp1125; AVX512VL-32-NEXT: .cfi_def_cfa_offset 81126; AVX512VL-32-NEXT: .cfi_offset %ebp, -81127; AVX512VL-32-NEXT: movl %esp, %ebp1128; AVX512VL-32-NEXT: .cfi_def_cfa_register %ebp1129; AVX512VL-32-NEXT: andl $-8, %esp1130; AVX512VL-32-NEXT: subl $16, %esp1131; AVX512VL-32-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]1132; AVX512VL-32-NEXT: vmovss {{.*#+}} xmm2 = [9.22337203E+18,0.0E+0,0.0E+0,0.0E+0]1133; AVX512VL-32-NEXT: xorl %eax, %eax1134; AVX512VL-32-NEXT: vcomiss %xmm2, %xmm11135; AVX512VL-32-NEXT: setae %al1136; AVX512VL-32-NEXT: kmovw %eax, %k11137; AVX512VL-32-NEXT: vmovss %xmm2, %xmm2, %xmm3 {%k1} {z}1138; AVX512VL-32-NEXT: vsubss %xmm3, %xmm1, %xmm11139; AVX512VL-32-NEXT: vmovss %xmm1, {{[0-9]+}}(%esp)1140; AVX512VL-32-NEXT: xorl %ecx, %ecx1141; AVX512VL-32-NEXT: vcomiss %xmm2, %xmm01142; AVX512VL-32-NEXT: setae %cl1143; AVX512VL-32-NEXT: kmovw %ecx, %k11144; AVX512VL-32-NEXT: vmovss %xmm2, %xmm2, %xmm1 {%k1} {z}1145; AVX512VL-32-NEXT: vsubss %xmm1, %xmm0, %xmm01146; AVX512VL-32-NEXT: vmovss %xmm0, (%esp)1147; AVX512VL-32-NEXT: flds {{[0-9]+}}(%esp)1148; AVX512VL-32-NEXT: fisttpll {{[0-9]+}}(%esp)1149; AVX512VL-32-NEXT: flds (%esp)1150; AVX512VL-32-NEXT: fisttpll (%esp)1151; AVX512VL-32-NEXT: wait1152; AVX512VL-32-NEXT: shll $31, %eax1153; AVX512VL-32-NEXT: xorl {{[0-9]+}}(%esp), %eax1154; AVX512VL-32-NEXT: shll $31, %ecx1155; AVX512VL-32-NEXT: xorl {{[0-9]+}}(%esp), %ecx1156; AVX512VL-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero1157; AVX512VL-32-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm01158; AVX512VL-32-NEXT: vpinsrd $2, {{[0-9]+}}(%esp), %xmm0, %xmm01159; AVX512VL-32-NEXT: vpinsrd $3, %eax, %xmm0, %xmm01160; AVX512VL-32-NEXT: movl %ebp, %esp1161; AVX512VL-32-NEXT: popl %ebp1162; AVX512VL-32-NEXT: .cfi_def_cfa %esp, 41163; AVX512VL-32-NEXT: retl1164;1165; AVX512VL-64-LABEL: strict_vector_fptoui_v2f32_to_v2i64:1166; AVX512VL-64: # %bb.0:1167; AVX512VL-64-NEXT: vcvttss2usi %xmm0, %rax1168; AVX512VL-64-NEXT: vmovq %rax, %xmm11169; AVX512VL-64-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]1170; AVX512VL-64-NEXT: vcvttss2usi %xmm0, %rax1171; AVX512VL-64-NEXT: vmovq %rax, %xmm01172; AVX512VL-64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]1173; AVX512VL-64-NEXT: retq1174;1175; AVX512DQ-LABEL: strict_vector_fptoui_v2f32_to_v2i64:1176; AVX512DQ: # %bb.0:1177; AVX512DQ-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero1178; AVX512DQ-NEXT: vcvttps2uqq %ymm0, %zmm01179; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm01180; AVX512DQ-NEXT: vzeroupper1181; AVX512DQ-NEXT: ret{{[l|q]}}1182;1183; AVX512VLDQ-LABEL: strict_vector_fptoui_v2f32_to_v2i64:1184; AVX512VLDQ: # %bb.0:1185; AVX512VLDQ-NEXT: vcvttps2uqq %xmm0, %xmm01186; AVX512VLDQ-NEXT: ret{{[l|q]}}1187 %ret = call <2 x i64> @llvm.experimental.constrained.fptoui.v2i64.v2f32(<2 x float> %a,1188 metadata !"fpexcept.strict") #01189 ret <2 x i64> %ret1190}1191 1192define <2 x i64> @strict_vector_fptoui_v2f32_to_v2i64_load128(ptr %x) strictfp {1193; SSE-32-LABEL: strict_vector_fptoui_v2f32_to_v2i64_load128:1194; SSE-32: # %bb.0:1195; SSE-32-NEXT: pushl %ebp1196; SSE-32-NEXT: .cfi_def_cfa_offset 81197; SSE-32-NEXT: .cfi_offset %ebp, -81198; SSE-32-NEXT: movl %esp, %ebp1199; SSE-32-NEXT: .cfi_def_cfa_register %ebp1200; SSE-32-NEXT: andl $-8, %esp1201; SSE-32-NEXT: subl $24, %esp1202; SSE-32-NEXT: movl 8(%ebp), %eax1203; SSE-32-NEXT: movaps (%eax), %xmm01204; SSE-32-NEXT: movss {{.*#+}} xmm1 = [9.22337203E+18,0.0E+0,0.0E+0,0.0E+0]1205; SSE-32-NEXT: comiss %xmm1, %xmm01206; SSE-32-NEXT: movaps %xmm1, %xmm21207; SSE-32-NEXT: jae .LBB5_21208; SSE-32-NEXT: # %bb.1:1209; SSE-32-NEXT: xorps %xmm2, %xmm21210; SSE-32-NEXT: .LBB5_2:1211; SSE-32-NEXT: movaps %xmm0, %xmm31212; SSE-32-NEXT: subss %xmm2, %xmm31213; SSE-32-NEXT: movss %xmm3, {{[0-9]+}}(%esp)1214; SSE-32-NEXT: setae %al1215; SSE-32-NEXT: flds {{[0-9]+}}(%esp)1216; SSE-32-NEXT: wait1217; SSE-32-NEXT: fnstcw {{[0-9]+}}(%esp)1218; SSE-32-NEXT: movzwl {{[0-9]+}}(%esp), %ecx1219; SSE-32-NEXT: orl $3072, %ecx # imm = 0xC001220; SSE-32-NEXT: movw %cx, {{[0-9]+}}(%esp)1221; SSE-32-NEXT: fldcw {{[0-9]+}}(%esp)1222; SSE-32-NEXT: fistpll {{[0-9]+}}(%esp)1223; SSE-32-NEXT: fldcw {{[0-9]+}}(%esp)1224; SSE-32-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]1225; SSE-32-NEXT: comiss %xmm1, %xmm01226; SSE-32-NEXT: jae .LBB5_41227; SSE-32-NEXT: # %bb.3:1228; SSE-32-NEXT: xorps %xmm1, %xmm11229; SSE-32-NEXT: .LBB5_4:1230; SSE-32-NEXT: subss %xmm1, %xmm01231; SSE-32-NEXT: movss %xmm0, {{[0-9]+}}(%esp)1232; SSE-32-NEXT: setae %cl1233; SSE-32-NEXT: flds {{[0-9]+}}(%esp)1234; SSE-32-NEXT: wait1235; SSE-32-NEXT: fnstcw (%esp)1236; SSE-32-NEXT: movzwl (%esp), %edx1237; SSE-32-NEXT: orl $3072, %edx # imm = 0xC001238; SSE-32-NEXT: movw %dx, {{[0-9]+}}(%esp)1239; SSE-32-NEXT: fldcw {{[0-9]+}}(%esp)1240; SSE-32-NEXT: fistpll {{[0-9]+}}(%esp)1241; SSE-32-NEXT: fldcw (%esp)1242; SSE-32-NEXT: movzbl %al, %eax1243; SSE-32-NEXT: shll $31, %eax1244; SSE-32-NEXT: xorl {{[0-9]+}}(%esp), %eax1245; SSE-32-NEXT: movd %eax, %xmm11246; SSE-32-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero1247; SSE-32-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]1248; SSE-32-NEXT: movzbl %cl, %eax1249; SSE-32-NEXT: shll $31, %eax1250; SSE-32-NEXT: xorl {{[0-9]+}}(%esp), %eax1251; SSE-32-NEXT: movd %eax, %xmm11252; SSE-32-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero1253; SSE-32-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]1254; SSE-32-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]1255; SSE-32-NEXT: movl %ebp, %esp1256; SSE-32-NEXT: popl %ebp1257; SSE-32-NEXT: .cfi_def_cfa %esp, 41258; SSE-32-NEXT: retl1259;1260; SSE-64-LABEL: strict_vector_fptoui_v2f32_to_v2i64_load128:1261; SSE-64: # %bb.0:1262; SSE-64-NEXT: movaps (%rdi), %xmm11263; SSE-64-NEXT: movss {{.*#+}} xmm3 = [9.22337203E+18,0.0E+0,0.0E+0,0.0E+0]1264; SSE-64-NEXT: comiss %xmm3, %xmm11265; SSE-64-NEXT: xorps %xmm2, %xmm21266; SSE-64-NEXT: xorps %xmm0, %xmm01267; SSE-64-NEXT: jb .LBB5_21268; SSE-64-NEXT: # %bb.1:1269; SSE-64-NEXT: movaps %xmm3, %xmm01270; SSE-64-NEXT: .LBB5_2:1271; SSE-64-NEXT: movaps %xmm1, %xmm41272; SSE-64-NEXT: subss %xmm0, %xmm41273; SSE-64-NEXT: cvttss2si %xmm4, %rax1274; SSE-64-NEXT: setae %cl1275; SSE-64-NEXT: movzbl %cl, %ecx1276; SSE-64-NEXT: shlq $63, %rcx1277; SSE-64-NEXT: xorq %rax, %rcx1278; SSE-64-NEXT: movq %rcx, %xmm01279; SSE-64-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,1,1]1280; SSE-64-NEXT: comiss %xmm3, %xmm11281; SSE-64-NEXT: jb .LBB5_41282; SSE-64-NEXT: # %bb.3:1283; SSE-64-NEXT: movaps %xmm3, %xmm21284; SSE-64-NEXT: .LBB5_4:1285; SSE-64-NEXT: subss %xmm2, %xmm11286; SSE-64-NEXT: cvttss2si %xmm1, %rax1287; SSE-64-NEXT: setae %cl1288; SSE-64-NEXT: movzbl %cl, %ecx1289; SSE-64-NEXT: shlq $63, %rcx1290; SSE-64-NEXT: xorq %rax, %rcx1291; SSE-64-NEXT: movq %rcx, %xmm11292; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]1293; SSE-64-NEXT: retq1294;1295; AVX-32-LABEL: strict_vector_fptoui_v2f32_to_v2i64_load128:1296; AVX-32: # %bb.0:1297; AVX-32-NEXT: pushl %ebp1298; AVX-32-NEXT: .cfi_def_cfa_offset 81299; AVX-32-NEXT: .cfi_offset %ebp, -81300; AVX-32-NEXT: movl %esp, %ebp1301; AVX-32-NEXT: .cfi_def_cfa_register %ebp1302; AVX-32-NEXT: andl $-8, %esp1303; AVX-32-NEXT: subl $16, %esp1304; AVX-32-NEXT: movl 8(%ebp), %eax1305; AVX-32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero1306; AVX-32-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero1307; AVX-32-NEXT: vmovss {{.*#+}} xmm1 = [9.22337203E+18,0.0E+0,0.0E+0,0.0E+0]1308; AVX-32-NEXT: vcomiss %xmm1, %xmm21309; AVX-32-NEXT: vmovaps %xmm1, %xmm31310; AVX-32-NEXT: jae .LBB5_21311; AVX-32-NEXT: # %bb.1:1312; AVX-32-NEXT: vxorps %xmm3, %xmm3, %xmm31313; AVX-32-NEXT: .LBB5_2:1314; AVX-32-NEXT: vsubss %xmm3, %xmm2, %xmm21315; AVX-32-NEXT: vmovss %xmm2, {{[0-9]+}}(%esp)1316; AVX-32-NEXT: flds {{[0-9]+}}(%esp)1317; AVX-32-NEXT: fisttpll {{[0-9]+}}(%esp)1318; AVX-32-NEXT: wait1319; AVX-32-NEXT: setae %al1320; AVX-32-NEXT: movzbl %al, %eax1321; AVX-32-NEXT: shll $31, %eax1322; AVX-32-NEXT: xorl {{[0-9]+}}(%esp), %eax1323; AVX-32-NEXT: vcomiss %xmm1, %xmm01324; AVX-32-NEXT: jae .LBB5_41325; AVX-32-NEXT: # %bb.3:1326; AVX-32-NEXT: vxorps %xmm1, %xmm1, %xmm11327; AVX-32-NEXT: .LBB5_4:1328; AVX-32-NEXT: vsubss %xmm1, %xmm0, %xmm01329; AVX-32-NEXT: vmovss %xmm0, (%esp)1330; AVX-32-NEXT: flds (%esp)1331; AVX-32-NEXT: fisttpll (%esp)1332; AVX-32-NEXT: wait1333; AVX-32-NEXT: setae %cl1334; AVX-32-NEXT: movzbl %cl, %ecx1335; AVX-32-NEXT: shll $31, %ecx1336; AVX-32-NEXT: xorl {{[0-9]+}}(%esp), %ecx1337; AVX-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero1338; AVX-32-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm01339; AVX-32-NEXT: vpinsrd $2, {{[0-9]+}}(%esp), %xmm0, %xmm01340; AVX-32-NEXT: vpinsrd $3, %eax, %xmm0, %xmm01341; AVX-32-NEXT: movl %ebp, %esp1342; AVX-32-NEXT: popl %ebp1343; AVX-32-NEXT: .cfi_def_cfa %esp, 41344; AVX-32-NEXT: retl1345;1346; AVX-64-LABEL: strict_vector_fptoui_v2f32_to_v2i64_load128:1347; AVX-64: # %bb.0:1348; AVX-64-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero1349; AVX-64-NEXT: vmovss {{.*#+}} xmm3 = mem[0],zero,zero,zero1350; AVX-64-NEXT: vmovss {{.*#+}} xmm1 = [9.22337203E+18,0.0E+0,0.0E+0,0.0E+0]1351; AVX-64-NEXT: vcomiss %xmm1, %xmm31352; AVX-64-NEXT: vxorps %xmm2, %xmm2, %xmm21353; AVX-64-NEXT: vxorps %xmm4, %xmm4, %xmm41354; AVX-64-NEXT: jb .LBB5_21355; AVX-64-NEXT: # %bb.1:1356; AVX-64-NEXT: vmovaps %xmm1, %xmm41357; AVX-64-NEXT: .LBB5_2:1358; AVX-64-NEXT: vsubss %xmm4, %xmm3, %xmm31359; AVX-64-NEXT: vcvttss2si %xmm3, %rax1360; AVX-64-NEXT: setae %cl1361; AVX-64-NEXT: movzbl %cl, %ecx1362; AVX-64-NEXT: shlq $63, %rcx1363; AVX-64-NEXT: xorq %rax, %rcx1364; AVX-64-NEXT: vmovq %rcx, %xmm31365; AVX-64-NEXT: vcomiss %xmm1, %xmm01366; AVX-64-NEXT: jb .LBB5_41367; AVX-64-NEXT: # %bb.3:1368; AVX-64-NEXT: vmovaps %xmm1, %xmm21369; AVX-64-NEXT: .LBB5_4:1370; AVX-64-NEXT: vsubss %xmm2, %xmm0, %xmm01371; AVX-64-NEXT: vcvttss2si %xmm0, %rax1372; AVX-64-NEXT: setae %cl1373; AVX-64-NEXT: movzbl %cl, %ecx1374; AVX-64-NEXT: shlq $63, %rcx1375; AVX-64-NEXT: xorq %rax, %rcx1376; AVX-64-NEXT: vmovq %rcx, %xmm01377; AVX-64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm3[0]1378; AVX-64-NEXT: retq1379;1380; AVX512F-32-LABEL: strict_vector_fptoui_v2f32_to_v2i64_load128:1381; AVX512F-32: # %bb.0:1382; AVX512F-32-NEXT: pushl %ebp1383; AVX512F-32-NEXT: .cfi_def_cfa_offset 81384; AVX512F-32-NEXT: .cfi_offset %ebp, -81385; AVX512F-32-NEXT: movl %esp, %ebp1386; AVX512F-32-NEXT: .cfi_def_cfa_register %ebp1387; AVX512F-32-NEXT: andl $-8, %esp1388; AVX512F-32-NEXT: subl $16, %esp1389; AVX512F-32-NEXT: movl 8(%ebp), %eax1390; AVX512F-32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero1391; AVX512F-32-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero1392; AVX512F-32-NEXT: vmovss {{.*#+}} xmm2 = [9.22337203E+18,0.0E+0,0.0E+0,0.0E+0]1393; AVX512F-32-NEXT: xorl %eax, %eax1394; AVX512F-32-NEXT: vcomiss %xmm2, %xmm11395; AVX512F-32-NEXT: setae %al1396; AVX512F-32-NEXT: kmovw %eax, %k11397; AVX512F-32-NEXT: vmovss %xmm2, %xmm2, %xmm3 {%k1} {z}1398; AVX512F-32-NEXT: vsubss %xmm3, %xmm1, %xmm11399; AVX512F-32-NEXT: vmovss %xmm1, {{[0-9]+}}(%esp)1400; AVX512F-32-NEXT: xorl %ecx, %ecx1401; AVX512F-32-NEXT: vcomiss %xmm2, %xmm01402; AVX512F-32-NEXT: setae %cl1403; AVX512F-32-NEXT: kmovw %ecx, %k11404; AVX512F-32-NEXT: vmovss %xmm2, %xmm2, %xmm1 {%k1} {z}1405; AVX512F-32-NEXT: vsubss %xmm1, %xmm0, %xmm01406; AVX512F-32-NEXT: vmovss %xmm0, (%esp)1407; AVX512F-32-NEXT: flds {{[0-9]+}}(%esp)1408; AVX512F-32-NEXT: fisttpll {{[0-9]+}}(%esp)1409; AVX512F-32-NEXT: flds (%esp)1410; AVX512F-32-NEXT: fisttpll (%esp)1411; AVX512F-32-NEXT: wait1412; AVX512F-32-NEXT: shll $31, %eax1413; AVX512F-32-NEXT: xorl {{[0-9]+}}(%esp), %eax1414; AVX512F-32-NEXT: shll $31, %ecx1415; AVX512F-32-NEXT: xorl {{[0-9]+}}(%esp), %ecx1416; AVX512F-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero1417; AVX512F-32-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm01418; AVX512F-32-NEXT: vpinsrd $2, {{[0-9]+}}(%esp), %xmm0, %xmm01419; AVX512F-32-NEXT: vpinsrd $3, %eax, %xmm0, %xmm01420; AVX512F-32-NEXT: movl %ebp, %esp1421; AVX512F-32-NEXT: popl %ebp1422; AVX512F-32-NEXT: .cfi_def_cfa %esp, 41423; AVX512F-32-NEXT: retl1424;1425; AVX512F-64-LABEL: strict_vector_fptoui_v2f32_to_v2i64_load128:1426; AVX512F-64: # %bb.0:1427; AVX512F-64-NEXT: vcvttss2usi 4(%rdi), %rax1428; AVX512F-64-NEXT: vmovq %rax, %xmm01429; AVX512F-64-NEXT: vcvttss2usi (%rdi), %rax1430; AVX512F-64-NEXT: vmovq %rax, %xmm11431; AVX512F-64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]1432; AVX512F-64-NEXT: retq1433;1434; AVX512VL-32-LABEL: strict_vector_fptoui_v2f32_to_v2i64_load128:1435; AVX512VL-32: # %bb.0:1436; AVX512VL-32-NEXT: pushl %ebp1437; AVX512VL-32-NEXT: .cfi_def_cfa_offset 81438; AVX512VL-32-NEXT: .cfi_offset %ebp, -81439; AVX512VL-32-NEXT: movl %esp, %ebp1440; AVX512VL-32-NEXT: .cfi_def_cfa_register %ebp1441; AVX512VL-32-NEXT: andl $-8, %esp1442; AVX512VL-32-NEXT: subl $16, %esp1443; AVX512VL-32-NEXT: movl 8(%ebp), %eax1444; AVX512VL-32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero1445; AVX512VL-32-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero1446; AVX512VL-32-NEXT: vmovss {{.*#+}} xmm2 = [9.22337203E+18,0.0E+0,0.0E+0,0.0E+0]1447; AVX512VL-32-NEXT: xorl %eax, %eax1448; AVX512VL-32-NEXT: vcomiss %xmm2, %xmm11449; AVX512VL-32-NEXT: setae %al1450; AVX512VL-32-NEXT: kmovw %eax, %k11451; AVX512VL-32-NEXT: vmovss %xmm2, %xmm2, %xmm3 {%k1} {z}1452; AVX512VL-32-NEXT: vsubss %xmm3, %xmm1, %xmm11453; AVX512VL-32-NEXT: vmovss %xmm1, {{[0-9]+}}(%esp)1454; AVX512VL-32-NEXT: xorl %ecx, %ecx1455; AVX512VL-32-NEXT: vcomiss %xmm2, %xmm01456; AVX512VL-32-NEXT: setae %cl1457; AVX512VL-32-NEXT: kmovw %ecx, %k11458; AVX512VL-32-NEXT: vmovss %xmm2, %xmm2, %xmm1 {%k1} {z}1459; AVX512VL-32-NEXT: vsubss %xmm1, %xmm0, %xmm01460; AVX512VL-32-NEXT: vmovss %xmm0, (%esp)1461; AVX512VL-32-NEXT: flds {{[0-9]+}}(%esp)1462; AVX512VL-32-NEXT: fisttpll {{[0-9]+}}(%esp)1463; AVX512VL-32-NEXT: flds (%esp)1464; AVX512VL-32-NEXT: fisttpll (%esp)1465; AVX512VL-32-NEXT: wait1466; AVX512VL-32-NEXT: shll $31, %eax1467; AVX512VL-32-NEXT: xorl {{[0-9]+}}(%esp), %eax1468; AVX512VL-32-NEXT: shll $31, %ecx1469; AVX512VL-32-NEXT: xorl {{[0-9]+}}(%esp), %ecx1470; AVX512VL-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero1471; AVX512VL-32-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm01472; AVX512VL-32-NEXT: vpinsrd $2, {{[0-9]+}}(%esp), %xmm0, %xmm01473; AVX512VL-32-NEXT: vpinsrd $3, %eax, %xmm0, %xmm01474; AVX512VL-32-NEXT: movl %ebp, %esp1475; AVX512VL-32-NEXT: popl %ebp1476; AVX512VL-32-NEXT: .cfi_def_cfa %esp, 41477; AVX512VL-32-NEXT: retl1478;1479; AVX512VL-64-LABEL: strict_vector_fptoui_v2f32_to_v2i64_load128:1480; AVX512VL-64: # %bb.0:1481; AVX512VL-64-NEXT: vcvttss2usi 4(%rdi), %rax1482; AVX512VL-64-NEXT: vmovq %rax, %xmm01483; AVX512VL-64-NEXT: vcvttss2usi (%rdi), %rax1484; AVX512VL-64-NEXT: vmovq %rax, %xmm11485; AVX512VL-64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]1486; AVX512VL-64-NEXT: retq1487;1488; AVX512DQ-32-LABEL: strict_vector_fptoui_v2f32_to_v2i64_load128:1489; AVX512DQ-32: # %bb.0:1490; AVX512DQ-32-NEXT: movl {{[0-9]+}}(%esp), %eax1491; AVX512DQ-32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero1492; AVX512DQ-32-NEXT: vcvttps2uqq %ymm0, %zmm01493; AVX512DQ-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm01494; AVX512DQ-32-NEXT: vzeroupper1495; AVX512DQ-32-NEXT: retl1496;1497; AVX512DQ-64-LABEL: strict_vector_fptoui_v2f32_to_v2i64_load128:1498; AVX512DQ-64: # %bb.0:1499; AVX512DQ-64-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero1500; AVX512DQ-64-NEXT: vcvttps2uqq %ymm0, %zmm01501; AVX512DQ-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm01502; AVX512DQ-64-NEXT: vzeroupper1503; AVX512DQ-64-NEXT: retq1504;1505; AVX512VLDQ-32-LABEL: strict_vector_fptoui_v2f32_to_v2i64_load128:1506; AVX512VLDQ-32: # %bb.0:1507; AVX512VLDQ-32-NEXT: movl {{[0-9]+}}(%esp), %eax1508; AVX512VLDQ-32-NEXT: vcvttps2uqq (%eax), %xmm01509; AVX512VLDQ-32-NEXT: retl1510;1511; AVX512VLDQ-64-LABEL: strict_vector_fptoui_v2f32_to_v2i64_load128:1512; AVX512VLDQ-64: # %bb.0:1513; AVX512VLDQ-64-NEXT: vcvttps2uqq (%rdi), %xmm01514; AVX512VLDQ-64-NEXT: retq1515 %a = load <4 x float>, ptr %x1516 %b = shufflevector <4 x float> %a, <4 x float> undef, <2 x i32> <i32 0, i32 1>1517 %c = call <2 x i64> @llvm.experimental.constrained.fptoui.v2i64.v2f32(<2 x float> %b, metadata !"fpexcept.strict") #01518 ret <2 x i64> %c1519}1520 1521define <2 x i32> @strict_vector_fptosi_v2f64_to_v2i32(<2 x double> %a) #0 {1522; SSE-32-LABEL: strict_vector_fptosi_v2f64_to_v2i32:1523; SSE-32: # %bb.0:1524; SSE-32-NEXT: cvttpd2dq %xmm0, %xmm01525; SSE-32-NEXT: retl1526;1527; SSE-64-LABEL: strict_vector_fptosi_v2f64_to_v2i32:1528; SSE-64: # %bb.0:1529; SSE-64-NEXT: cvttpd2dq %xmm0, %xmm01530; SSE-64-NEXT: retq1531;1532; AVX-LABEL: strict_vector_fptosi_v2f64_to_v2i32:1533; AVX: # %bb.0:1534; AVX-NEXT: vcvttpd2dq %xmm0, %xmm01535; AVX-NEXT: ret{{[l|q]}}1536;1537; AVX512F-LABEL: strict_vector_fptosi_v2f64_to_v2i32:1538; AVX512F: # %bb.0:1539; AVX512F-NEXT: vcvttpd2dq %xmm0, %xmm01540; AVX512F-NEXT: ret{{[l|q]}}1541;1542; AVX512VL-LABEL: strict_vector_fptosi_v2f64_to_v2i32:1543; AVX512VL: # %bb.0:1544; AVX512VL-NEXT: vcvttpd2dq %xmm0, %xmm01545; AVX512VL-NEXT: ret{{[l|q]}}1546;1547; AVX512DQ-LABEL: strict_vector_fptosi_v2f64_to_v2i32:1548; AVX512DQ: # %bb.0:1549; AVX512DQ-NEXT: vcvttpd2dq %xmm0, %xmm01550; AVX512DQ-NEXT: ret{{[l|q]}}1551;1552; AVX512VLDQ-LABEL: strict_vector_fptosi_v2f64_to_v2i32:1553; AVX512VLDQ: # %bb.0:1554; AVX512VLDQ-NEXT: vcvttpd2dq %xmm0, %xmm01555; AVX512VLDQ-NEXT: ret{{[l|q]}}1556 %ret = call <2 x i32> @llvm.experimental.constrained.fptosi.v2i32.v2f64(<2 x double> %a,1557 metadata !"fpexcept.strict") #01558 ret <2 x i32> %ret1559}1560 1561define <2 x i32> @strict_vector_fptoui_v2f64_to_v2i32(<2 x double> %a) #0 {1562; SSE-32-LABEL: strict_vector_fptoui_v2f64_to_v2i32:1563; SSE-32: # %bb.0:1564; SSE-32-NEXT: movsd {{.*#+}} xmm3 = [2.147483648E+9,0.0E+0]1565; SSE-32-NEXT: comisd %xmm3, %xmm01566; SSE-32-NEXT: xorpd %xmm2, %xmm21567; SSE-32-NEXT: xorpd %xmm1, %xmm11568; SSE-32-NEXT: jb .LBB7_21569; SSE-32-NEXT: # %bb.1:1570; SSE-32-NEXT: movapd %xmm3, %xmm11571; SSE-32-NEXT: .LBB7_2:1572; SSE-32-NEXT: setae %al1573; SSE-32-NEXT: movzbl %al, %eax1574; SSE-32-NEXT: shll $31, %eax1575; SSE-32-NEXT: movapd %xmm0, %xmm41576; SSE-32-NEXT: subsd %xmm1, %xmm41577; SSE-32-NEXT: cvttsd2si %xmm4, %ecx1578; SSE-32-NEXT: xorl %eax, %ecx1579; SSE-32-NEXT: movd %ecx, %xmm11580; SSE-32-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]1581; SSE-32-NEXT: comisd %xmm3, %xmm01582; SSE-32-NEXT: jb .LBB7_41583; SSE-32-NEXT: # %bb.3:1584; SSE-32-NEXT: movapd %xmm3, %xmm21585; SSE-32-NEXT: .LBB7_4:1586; SSE-32-NEXT: setae %al1587; SSE-32-NEXT: movzbl %al, %eax1588; SSE-32-NEXT: shll $31, %eax1589; SSE-32-NEXT: subsd %xmm2, %xmm01590; SSE-32-NEXT: cvttsd2si %xmm0, %ecx1591; SSE-32-NEXT: xorl %eax, %ecx1592; SSE-32-NEXT: movd %ecx, %xmm01593; SSE-32-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]1594; SSE-32-NEXT: movdqa %xmm1, %xmm01595; SSE-32-NEXT: retl1596;1597; SSE-64-LABEL: strict_vector_fptoui_v2f64_to_v2i32:1598; SSE-64: # %bb.0:1599; SSE-64-NEXT: cvttsd2si %xmm0, %rax1600; SSE-64-NEXT: movd %eax, %xmm11601; SSE-64-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]1602; SSE-64-NEXT: cvttsd2si %xmm0, %rax1603; SSE-64-NEXT: movd %eax, %xmm01604; SSE-64-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]1605; SSE-64-NEXT: movdqa %xmm1, %xmm01606; SSE-64-NEXT: retq1607;1608; AVX-32-LABEL: strict_vector_fptoui_v2f64_to_v2i32:1609; AVX-32: # %bb.0:1610; AVX-32-NEXT: pushl %ebp1611; AVX-32-NEXT: .cfi_def_cfa_offset 81612; AVX-32-NEXT: .cfi_offset %ebp, -81613; AVX-32-NEXT: movl %esp, %ebp1614; AVX-32-NEXT: .cfi_def_cfa_register %ebp1615; AVX-32-NEXT: andl $-8, %esp1616; AVX-32-NEXT: subl $16, %esp1617; AVX-32-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)1618; AVX-32-NEXT: vmovhps %xmm0, (%esp)1619; AVX-32-NEXT: fldl {{[0-9]+}}(%esp)1620; AVX-32-NEXT: fisttpll {{[0-9]+}}(%esp)1621; AVX-32-NEXT: fldl (%esp)1622; AVX-32-NEXT: fisttpll (%esp)1623; AVX-32-NEXT: wait1624; AVX-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero1625; AVX-32-NEXT: vpinsrd $1, (%esp), %xmm0, %xmm01626; AVX-32-NEXT: movl %ebp, %esp1627; AVX-32-NEXT: popl %ebp1628; AVX-32-NEXT: .cfi_def_cfa %esp, 41629; AVX-32-NEXT: retl1630;1631; AVX-64-LABEL: strict_vector_fptoui_v2f64_to_v2i32:1632; AVX-64: # %bb.0:1633; AVX-64-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]1634; AVX-64-NEXT: vcvttsd2si %xmm1, %rax1635; AVX-64-NEXT: vcvttsd2si %xmm0, %rcx1636; AVX-64-NEXT: vmovd %ecx, %xmm01637; AVX-64-NEXT: vpinsrd $1, %eax, %xmm0, %xmm01638; AVX-64-NEXT: retq1639;1640; AVX512F-LABEL: strict_vector_fptoui_v2f64_to_v2i32:1641; AVX512F: # %bb.0:1642; AVX512F-NEXT: vmovaps %xmm0, %xmm01643; AVX512F-NEXT: vcvttpd2udq %zmm0, %ymm01644; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm01645; AVX512F-NEXT: vzeroupper1646; AVX512F-NEXT: ret{{[l|q]}}1647;1648; AVX512VL-LABEL: strict_vector_fptoui_v2f64_to_v2i32:1649; AVX512VL: # %bb.0:1650; AVX512VL-NEXT: vcvttpd2udq %xmm0, %xmm01651; AVX512VL-NEXT: ret{{[l|q]}}1652;1653; AVX512DQ-LABEL: strict_vector_fptoui_v2f64_to_v2i32:1654; AVX512DQ: # %bb.0:1655; AVX512DQ-NEXT: vmovaps %xmm0, %xmm01656; AVX512DQ-NEXT: vcvttpd2udq %zmm0, %ymm01657; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm01658; AVX512DQ-NEXT: vzeroupper1659; AVX512DQ-NEXT: ret{{[l|q]}}1660;1661; AVX512VLDQ-LABEL: strict_vector_fptoui_v2f64_to_v2i32:1662; AVX512VLDQ: # %bb.0:1663; AVX512VLDQ-NEXT: vcvttpd2udq %xmm0, %xmm01664; AVX512VLDQ-NEXT: ret{{[l|q]}}1665 %ret = call <2 x i32> @llvm.experimental.constrained.fptoui.v2i32.v2f64(<2 x double> %a,1666 metadata !"fpexcept.strict") #01667 ret <2 x i32> %ret1668}1669 1670define <2 x i32> @strict_vector_fptosi_v2f32_to_v2i32(<2 x float> %a) #0 {1671; SSE-32-LABEL: strict_vector_fptosi_v2f32_to_v2i32:1672; SSE-32: # %bb.0:1673; SSE-32-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero1674; SSE-32-NEXT: cvttps2dq %xmm0, %xmm01675; SSE-32-NEXT: retl1676;1677; SSE-64-LABEL: strict_vector_fptosi_v2f32_to_v2i32:1678; SSE-64: # %bb.0:1679; SSE-64-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero1680; SSE-64-NEXT: cvttps2dq %xmm0, %xmm01681; SSE-64-NEXT: retq1682;1683; AVX-LABEL: strict_vector_fptosi_v2f32_to_v2i32:1684; AVX: # %bb.0:1685; AVX-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero1686; AVX-NEXT: vcvttps2dq %xmm0, %xmm01687; AVX-NEXT: ret{{[l|q]}}1688;1689; AVX512F-LABEL: strict_vector_fptosi_v2f32_to_v2i32:1690; AVX512F: # %bb.0:1691; AVX512F-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero1692; AVX512F-NEXT: vcvttps2dq %xmm0, %xmm01693; AVX512F-NEXT: ret{{[l|q]}}1694;1695; AVX512VL-LABEL: strict_vector_fptosi_v2f32_to_v2i32:1696; AVX512VL: # %bb.0:1697; AVX512VL-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero1698; AVX512VL-NEXT: vcvttps2dq %xmm0, %xmm01699; AVX512VL-NEXT: ret{{[l|q]}}1700;1701; AVX512DQ-LABEL: strict_vector_fptosi_v2f32_to_v2i32:1702; AVX512DQ: # %bb.0:1703; AVX512DQ-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero1704; AVX512DQ-NEXT: vcvttps2dq %xmm0, %xmm01705; AVX512DQ-NEXT: ret{{[l|q]}}1706;1707; AVX512VLDQ-LABEL: strict_vector_fptosi_v2f32_to_v2i32:1708; AVX512VLDQ: # %bb.0:1709; AVX512VLDQ-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero1710; AVX512VLDQ-NEXT: vcvttps2dq %xmm0, %xmm01711; AVX512VLDQ-NEXT: ret{{[l|q]}}1712 %ret = call <2 x i32> @llvm.experimental.constrained.fptosi.v2i32.v2f32(<2 x float> %a,1713 metadata !"fpexcept.strict") #01714 ret <2 x i32> %ret1715}1716 1717define <2 x i32> @strict_vector_fptoui_v2f32_to_v2i32(<2 x float> %a) #0 {1718; SSE-32-LABEL: strict_vector_fptoui_v2f32_to_v2i32:1719; SSE-32: # %bb.0:1720; SSE-32-NEXT: movss {{.*#+}} xmm3 = [2.14748365E+9,0.0E+0,0.0E+0,0.0E+0]1721; SSE-32-NEXT: comiss %xmm3, %xmm01722; SSE-32-NEXT: xorps %xmm2, %xmm21723; SSE-32-NEXT: xorps %xmm1, %xmm11724; SSE-32-NEXT: jb .LBB9_21725; SSE-32-NEXT: # %bb.1:1726; SSE-32-NEXT: movaps %xmm3, %xmm11727; SSE-32-NEXT: .LBB9_2:1728; SSE-32-NEXT: setae %al1729; SSE-32-NEXT: movzbl %al, %eax1730; SSE-32-NEXT: shll $31, %eax1731; SSE-32-NEXT: movaps %xmm0, %xmm41732; SSE-32-NEXT: subss %xmm1, %xmm41733; SSE-32-NEXT: cvttss2si %xmm4, %ecx1734; SSE-32-NEXT: xorl %eax, %ecx1735; SSE-32-NEXT: movd %ecx, %xmm11736; SSE-32-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]1737; SSE-32-NEXT: comiss %xmm3, %xmm01738; SSE-32-NEXT: jb .LBB9_41739; SSE-32-NEXT: # %bb.3:1740; SSE-32-NEXT: movaps %xmm3, %xmm21741; SSE-32-NEXT: .LBB9_4:1742; SSE-32-NEXT: setae %al1743; SSE-32-NEXT: movzbl %al, %eax1744; SSE-32-NEXT: shll $31, %eax1745; SSE-32-NEXT: subss %xmm2, %xmm01746; SSE-32-NEXT: cvttss2si %xmm0, %ecx1747; SSE-32-NEXT: xorl %eax, %ecx1748; SSE-32-NEXT: movd %ecx, %xmm01749; SSE-32-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]1750; SSE-32-NEXT: movdqa %xmm1, %xmm01751; SSE-32-NEXT: retl1752;1753; SSE-64-LABEL: strict_vector_fptoui_v2f32_to_v2i32:1754; SSE-64: # %bb.0:1755; SSE-64-NEXT: cvttss2si %xmm0, %rax1756; SSE-64-NEXT: movd %eax, %xmm11757; SSE-64-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]1758; SSE-64-NEXT: cvttss2si %xmm0, %rax1759; SSE-64-NEXT: movd %eax, %xmm01760; SSE-64-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]1761; SSE-64-NEXT: movdqa %xmm1, %xmm01762; SSE-64-NEXT: retq1763;1764; AVX-32-LABEL: strict_vector_fptoui_v2f32_to_v2i32:1765; AVX-32: # %bb.0:1766; AVX-32-NEXT: pushl %ebp1767; AVX-32-NEXT: .cfi_def_cfa_offset 81768; AVX-32-NEXT: .cfi_offset %ebp, -81769; AVX-32-NEXT: movl %esp, %ebp1770; AVX-32-NEXT: .cfi_def_cfa_register %ebp1771; AVX-32-NEXT: andl $-8, %esp1772; AVX-32-NEXT: subl $16, %esp1773; AVX-32-NEXT: vmovss %xmm0, (%esp)1774; AVX-32-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp)1775; AVX-32-NEXT: flds (%esp)1776; AVX-32-NEXT: fisttpll (%esp)1777; AVX-32-NEXT: flds {{[0-9]+}}(%esp)1778; AVX-32-NEXT: fisttpll {{[0-9]+}}(%esp)1779; AVX-32-NEXT: wait1780; AVX-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero1781; AVX-32-NEXT: vpinsrd $1, {{[0-9]+}}(%esp), %xmm0, %xmm01782; AVX-32-NEXT: movl %ebp, %esp1783; AVX-32-NEXT: popl %ebp1784; AVX-32-NEXT: .cfi_def_cfa %esp, 41785; AVX-32-NEXT: retl1786;1787; AVX-64-LABEL: strict_vector_fptoui_v2f32_to_v2i32:1788; AVX-64: # %bb.0:1789; AVX-64-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]1790; AVX-64-NEXT: vcvttss2si %xmm1, %rax1791; AVX-64-NEXT: vcvttss2si %xmm0, %rcx1792; AVX-64-NEXT: vmovd %ecx, %xmm01793; AVX-64-NEXT: vpinsrd $1, %eax, %xmm0, %xmm01794; AVX-64-NEXT: retq1795;1796; AVX512F-LABEL: strict_vector_fptoui_v2f32_to_v2i32:1797; AVX512F: # %bb.0:1798; AVX512F-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero1799; AVX512F-NEXT: vcvttps2udq %zmm0, %zmm01800; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm01801; AVX512F-NEXT: vzeroupper1802; AVX512F-NEXT: ret{{[l|q]}}1803;1804; AVX512VL-LABEL: strict_vector_fptoui_v2f32_to_v2i32:1805; AVX512VL: # %bb.0:1806; AVX512VL-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero1807; AVX512VL-NEXT: vcvttps2udq %xmm0, %xmm01808; AVX512VL-NEXT: ret{{[l|q]}}1809;1810; AVX512DQ-LABEL: strict_vector_fptoui_v2f32_to_v2i32:1811; AVX512DQ: # %bb.0:1812; AVX512DQ-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero1813; AVX512DQ-NEXT: vcvttps2udq %zmm0, %zmm01814; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm01815; AVX512DQ-NEXT: vzeroupper1816; AVX512DQ-NEXT: ret{{[l|q]}}1817;1818; AVX512VLDQ-LABEL: strict_vector_fptoui_v2f32_to_v2i32:1819; AVX512VLDQ: # %bb.0:1820; AVX512VLDQ-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero1821; AVX512VLDQ-NEXT: vcvttps2udq %xmm0, %xmm01822; AVX512VLDQ-NEXT: ret{{[l|q]}}1823 %ret = call <2 x i32> @llvm.experimental.constrained.fptoui.v2i32.v2f32(<2 x float> %a,1824 metadata !"fpexcept.strict") #01825 ret <2 x i32> %ret1826}1827 1828define <2 x i16> @strict_vector_fptosi_v2f64_to_v2i16(<2 x double> %a) #0 {1829; SSE-32-LABEL: strict_vector_fptosi_v2f64_to_v2i16:1830; SSE-32: # %bb.0:1831; SSE-32-NEXT: cvttpd2dq %xmm0, %xmm01832; SSE-32-NEXT: packssdw %xmm0, %xmm01833; SSE-32-NEXT: retl1834;1835; SSE-64-LABEL: strict_vector_fptosi_v2f64_to_v2i16:1836; SSE-64: # %bb.0:1837; SSE-64-NEXT: cvttpd2dq %xmm0, %xmm01838; SSE-64-NEXT: packssdw %xmm0, %xmm01839; SSE-64-NEXT: retq1840;1841; AVX-LABEL: strict_vector_fptosi_v2f64_to_v2i16:1842; AVX: # %bb.0:1843; AVX-NEXT: vcvttpd2dq %xmm0, %xmm01844; AVX-NEXT: vpackssdw %xmm0, %xmm0, %xmm01845; AVX-NEXT: ret{{[l|q]}}1846;1847; AVX512F-LABEL: strict_vector_fptosi_v2f64_to_v2i16:1848; AVX512F: # %bb.0:1849; AVX512F-NEXT: vcvttpd2dq %xmm0, %xmm01850; AVX512F-NEXT: vpackssdw %xmm0, %xmm0, %xmm01851; AVX512F-NEXT: ret{{[l|q]}}1852;1853; AVX512VL-LABEL: strict_vector_fptosi_v2f64_to_v2i16:1854; AVX512VL: # %bb.0:1855; AVX512VL-NEXT: vcvttpd2dq %xmm0, %xmm01856; AVX512VL-NEXT: vpackssdw %xmm0, %xmm0, %xmm01857; AVX512VL-NEXT: ret{{[l|q]}}1858;1859; AVX512DQ-LABEL: strict_vector_fptosi_v2f64_to_v2i16:1860; AVX512DQ: # %bb.0:1861; AVX512DQ-NEXT: vcvttpd2dq %xmm0, %xmm01862; AVX512DQ-NEXT: vpackssdw %xmm0, %xmm0, %xmm01863; AVX512DQ-NEXT: ret{{[l|q]}}1864;1865; AVX512VLDQ-LABEL: strict_vector_fptosi_v2f64_to_v2i16:1866; AVX512VLDQ: # %bb.0:1867; AVX512VLDQ-NEXT: vcvttpd2dq %xmm0, %xmm01868; AVX512VLDQ-NEXT: vpackssdw %xmm0, %xmm0, %xmm01869; AVX512VLDQ-NEXT: ret{{[l|q]}}1870 %ret = call <2 x i16> @llvm.experimental.constrained.fptosi.v2i16.v2f64(<2 x double> %a,1871 metadata !"fpexcept.strict") #01872 ret <2 x i16> %ret1873}1874 1875define <2 x i16> @strict_vector_fptoui_v2f64_to_v2i16(<2 x double> %a) #0 {1876; SSE-32-LABEL: strict_vector_fptoui_v2f64_to_v2i16:1877; SSE-32: # %bb.0:1878; SSE-32-NEXT: cvttpd2dq %xmm0, %xmm01879; SSE-32-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]1880; SSE-32-NEXT: retl1881;1882; SSE-64-LABEL: strict_vector_fptoui_v2f64_to_v2i16:1883; SSE-64: # %bb.0:1884; SSE-64-NEXT: cvttpd2dq %xmm0, %xmm01885; SSE-64-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]1886; SSE-64-NEXT: retq1887;1888; AVX-LABEL: strict_vector_fptoui_v2f64_to_v2i16:1889; AVX: # %bb.0:1890; AVX-NEXT: vcvttpd2dq %xmm0, %xmm01891; AVX-NEXT: vpackusdw %xmm0, %xmm0, %xmm01892; AVX-NEXT: ret{{[l|q]}}1893;1894; AVX512F-LABEL: strict_vector_fptoui_v2f64_to_v2i16:1895; AVX512F: # %bb.0:1896; AVX512F-NEXT: vcvttpd2dq %xmm0, %xmm01897; AVX512F-NEXT: vpackusdw %xmm0, %xmm0, %xmm01898; AVX512F-NEXT: ret{{[l|q]}}1899;1900; AVX512VL-LABEL: strict_vector_fptoui_v2f64_to_v2i16:1901; AVX512VL: # %bb.0:1902; AVX512VL-NEXT: vcvttpd2dq %xmm0, %xmm01903; AVX512VL-NEXT: vpackusdw %xmm0, %xmm0, %xmm01904; AVX512VL-NEXT: ret{{[l|q]}}1905;1906; AVX512DQ-LABEL: strict_vector_fptoui_v2f64_to_v2i16:1907; AVX512DQ: # %bb.0:1908; AVX512DQ-NEXT: vcvttpd2dq %xmm0, %xmm01909; AVX512DQ-NEXT: vpackusdw %xmm0, %xmm0, %xmm01910; AVX512DQ-NEXT: ret{{[l|q]}}1911;1912; AVX512VLDQ-LABEL: strict_vector_fptoui_v2f64_to_v2i16:1913; AVX512VLDQ: # %bb.0:1914; AVX512VLDQ-NEXT: vcvttpd2dq %xmm0, %xmm01915; AVX512VLDQ-NEXT: vpackusdw %xmm0, %xmm0, %xmm01916; AVX512VLDQ-NEXT: ret{{[l|q]}}1917 %ret = call <2 x i16> @llvm.experimental.constrained.fptoui.v2i16.v2f64(<2 x double> %a,1918 metadata !"fpexcept.strict") #01919 ret <2 x i16> %ret1920}1921 1922define <2 x i16> @strict_vector_fptosi_v2f32_to_v2i16(<2 x float> %a) #0 {1923; SSE-32-LABEL: strict_vector_fptosi_v2f32_to_v2i16:1924; SSE-32: # %bb.0:1925; SSE-32-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero1926; SSE-32-NEXT: cvttps2dq %xmm0, %xmm01927; SSE-32-NEXT: packssdw %xmm0, %xmm01928; SSE-32-NEXT: retl1929;1930; SSE-64-LABEL: strict_vector_fptosi_v2f32_to_v2i16:1931; SSE-64: # %bb.0:1932; SSE-64-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero1933; SSE-64-NEXT: cvttps2dq %xmm0, %xmm01934; SSE-64-NEXT: packssdw %xmm0, %xmm01935; SSE-64-NEXT: retq1936;1937; AVX-LABEL: strict_vector_fptosi_v2f32_to_v2i16:1938; AVX: # %bb.0:1939; AVX-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero1940; AVX-NEXT: vcvttps2dq %xmm0, %xmm01941; AVX-NEXT: vpackssdw %xmm0, %xmm0, %xmm01942; AVX-NEXT: ret{{[l|q]}}1943;1944; AVX512F-LABEL: strict_vector_fptosi_v2f32_to_v2i16:1945; AVX512F: # %bb.0:1946; AVX512F-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero1947; AVX512F-NEXT: vcvttps2dq %xmm0, %xmm01948; AVX512F-NEXT: vpackssdw %xmm0, %xmm0, %xmm01949; AVX512F-NEXT: ret{{[l|q]}}1950;1951; AVX512VL-LABEL: strict_vector_fptosi_v2f32_to_v2i16:1952; AVX512VL: # %bb.0:1953; AVX512VL-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero1954; AVX512VL-NEXT: vcvttps2dq %xmm0, %xmm01955; AVX512VL-NEXT: vpackssdw %xmm0, %xmm0, %xmm01956; AVX512VL-NEXT: ret{{[l|q]}}1957;1958; AVX512DQ-LABEL: strict_vector_fptosi_v2f32_to_v2i16:1959; AVX512DQ: # %bb.0:1960; AVX512DQ-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero1961; AVX512DQ-NEXT: vcvttps2dq %xmm0, %xmm01962; AVX512DQ-NEXT: vpackssdw %xmm0, %xmm0, %xmm01963; AVX512DQ-NEXT: ret{{[l|q]}}1964;1965; AVX512VLDQ-LABEL: strict_vector_fptosi_v2f32_to_v2i16:1966; AVX512VLDQ: # %bb.0:1967; AVX512VLDQ-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero1968; AVX512VLDQ-NEXT: vcvttps2dq %xmm0, %xmm01969; AVX512VLDQ-NEXT: vpackssdw %xmm0, %xmm0, %xmm01970; AVX512VLDQ-NEXT: ret{{[l|q]}}1971 %ret = call <2 x i16> @llvm.experimental.constrained.fptosi.v2i16.v2f32(<2 x float> %a,1972 metadata !"fpexcept.strict") #01973 ret <2 x i16> %ret1974}1975 1976define <2 x i16> @strict_vector_fptoui_v2f32_to_v2i16(<2 x float> %a) #0 {1977; SSE-32-LABEL: strict_vector_fptoui_v2f32_to_v2i16:1978; SSE-32: # %bb.0:1979; SSE-32-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero1980; SSE-32-NEXT: cvttps2dq %xmm0, %xmm01981; SSE-32-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]1982; SSE-32-NEXT: retl1983;1984; SSE-64-LABEL: strict_vector_fptoui_v2f32_to_v2i16:1985; SSE-64: # %bb.0:1986; SSE-64-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero1987; SSE-64-NEXT: cvttps2dq %xmm0, %xmm01988; SSE-64-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]1989; SSE-64-NEXT: retq1990;1991; AVX-LABEL: strict_vector_fptoui_v2f32_to_v2i16:1992; AVX: # %bb.0:1993; AVX-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero1994; AVX-NEXT: vcvttps2dq %xmm0, %xmm01995; AVX-NEXT: vpackusdw %xmm0, %xmm0, %xmm01996; AVX-NEXT: ret{{[l|q]}}1997;1998; AVX512F-LABEL: strict_vector_fptoui_v2f32_to_v2i16:1999; AVX512F: # %bb.0:2000; AVX512F-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero2001; AVX512F-NEXT: vcvttps2dq %xmm0, %xmm02002; AVX512F-NEXT: vpackusdw %xmm0, %xmm0, %xmm02003; AVX512F-NEXT: ret{{[l|q]}}2004;2005; AVX512VL-LABEL: strict_vector_fptoui_v2f32_to_v2i16:2006; AVX512VL: # %bb.0:2007; AVX512VL-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero2008; AVX512VL-NEXT: vcvttps2dq %xmm0, %xmm02009; AVX512VL-NEXT: vpackusdw %xmm0, %xmm0, %xmm02010; AVX512VL-NEXT: ret{{[l|q]}}2011;2012; AVX512DQ-LABEL: strict_vector_fptoui_v2f32_to_v2i16:2013; AVX512DQ: # %bb.0:2014; AVX512DQ-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero2015; AVX512DQ-NEXT: vcvttps2dq %xmm0, %xmm02016; AVX512DQ-NEXT: vpackusdw %xmm0, %xmm0, %xmm02017; AVX512DQ-NEXT: ret{{[l|q]}}2018;2019; AVX512VLDQ-LABEL: strict_vector_fptoui_v2f32_to_v2i16:2020; AVX512VLDQ: # %bb.0:2021; AVX512VLDQ-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero2022; AVX512VLDQ-NEXT: vcvttps2dq %xmm0, %xmm02023; AVX512VLDQ-NEXT: vpackusdw %xmm0, %xmm0, %xmm02024; AVX512VLDQ-NEXT: ret{{[l|q]}}2025 %ret = call <2 x i16> @llvm.experimental.constrained.fptoui.v2i16.v2f32(<2 x float> %a,2026 metadata !"fpexcept.strict") #02027 ret <2 x i16> %ret2028}2029 2030define <2 x i8> @strict_vector_fptosi_v2f64_to_v2i8(<2 x double> %a) #0 {2031; SSE-32-LABEL: strict_vector_fptosi_v2f64_to_v2i8:2032; SSE-32: # %bb.0:2033; SSE-32-NEXT: cvttpd2dq %xmm0, %xmm02034; SSE-32-NEXT: packssdw %xmm0, %xmm02035; SSE-32-NEXT: packsswb %xmm0, %xmm02036; SSE-32-NEXT: retl2037;2038; SSE-64-LABEL: strict_vector_fptosi_v2f64_to_v2i8:2039; SSE-64: # %bb.0:2040; SSE-64-NEXT: cvttpd2dq %xmm0, %xmm02041; SSE-64-NEXT: packssdw %xmm0, %xmm02042; SSE-64-NEXT: packsswb %xmm0, %xmm02043; SSE-64-NEXT: retq2044;2045; AVX-LABEL: strict_vector_fptosi_v2f64_to_v2i8:2046; AVX: # %bb.0:2047; AVX-NEXT: vcvttpd2dq %xmm0, %xmm02048; AVX-NEXT: vpackssdw %xmm0, %xmm0, %xmm02049; AVX-NEXT: vpacksswb %xmm0, %xmm0, %xmm02050; AVX-NEXT: ret{{[l|q]}}2051;2052; AVX512F-LABEL: strict_vector_fptosi_v2f64_to_v2i8:2053; AVX512F: # %bb.0:2054; AVX512F-NEXT: vcvttpd2dq %xmm0, %xmm02055; AVX512F-NEXT: vpackssdw %xmm0, %xmm0, %xmm02056; AVX512F-NEXT: vpacksswb %xmm0, %xmm0, %xmm02057; AVX512F-NEXT: ret{{[l|q]}}2058;2059; AVX512VL-LABEL: strict_vector_fptosi_v2f64_to_v2i8:2060; AVX512VL: # %bb.0:2061; AVX512VL-NEXT: vcvttpd2dq %xmm0, %xmm02062; AVX512VL-NEXT: vpmovdb %xmm0, %xmm02063; AVX512VL-NEXT: ret{{[l|q]}}2064;2065; AVX512DQ-LABEL: strict_vector_fptosi_v2f64_to_v2i8:2066; AVX512DQ: # %bb.0:2067; AVX512DQ-NEXT: vcvttpd2dq %xmm0, %xmm02068; AVX512DQ-NEXT: vpackssdw %xmm0, %xmm0, %xmm02069; AVX512DQ-NEXT: vpacksswb %xmm0, %xmm0, %xmm02070; AVX512DQ-NEXT: ret{{[l|q]}}2071;2072; AVX512VLDQ-LABEL: strict_vector_fptosi_v2f64_to_v2i8:2073; AVX512VLDQ: # %bb.0:2074; AVX512VLDQ-NEXT: vcvttpd2dq %xmm0, %xmm02075; AVX512VLDQ-NEXT: vpmovdb %xmm0, %xmm02076; AVX512VLDQ-NEXT: ret{{[l|q]}}2077 %ret = call <2 x i8> @llvm.experimental.constrained.fptosi.v2i8.v2f64(<2 x double> %a,2078 metadata !"fpexcept.strict") #02079 ret <2 x i8> %ret2080}2081 2082define <2 x i8> @strict_vector_fptoui_v2f64_to_v2i8(<2 x double> %a) #0 {2083; SSE-32-LABEL: strict_vector_fptoui_v2f64_to_v2i8:2084; SSE-32: # %bb.0:2085; SSE-32-NEXT: cvttpd2dq %xmm0, %xmm02086; SSE-32-NEXT: packuswb %xmm0, %xmm02087; SSE-32-NEXT: packuswb %xmm0, %xmm02088; SSE-32-NEXT: retl2089;2090; SSE-64-LABEL: strict_vector_fptoui_v2f64_to_v2i8:2091; SSE-64: # %bb.0:2092; SSE-64-NEXT: cvttpd2dq %xmm0, %xmm02093; SSE-64-NEXT: packuswb %xmm0, %xmm02094; SSE-64-NEXT: packuswb %xmm0, %xmm02095; SSE-64-NEXT: retq2096;2097; AVX-LABEL: strict_vector_fptoui_v2f64_to_v2i8:2098; AVX: # %bb.0:2099; AVX-NEXT: vcvttpd2dq %xmm0, %xmm02100; AVX-NEXT: vpackusdw %xmm0, %xmm0, %xmm02101; AVX-NEXT: vpackuswb %xmm0, %xmm0, %xmm02102; AVX-NEXT: ret{{[l|q]}}2103;2104; AVX512F-LABEL: strict_vector_fptoui_v2f64_to_v2i8:2105; AVX512F: # %bb.0:2106; AVX512F-NEXT: vcvttpd2dq %xmm0, %xmm02107; AVX512F-NEXT: vpackusdw %xmm0, %xmm0, %xmm02108; AVX512F-NEXT: vpackuswb %xmm0, %xmm0, %xmm02109; AVX512F-NEXT: ret{{[l|q]}}2110;2111; AVX512VL-LABEL: strict_vector_fptoui_v2f64_to_v2i8:2112; AVX512VL: # %bb.0:2113; AVX512VL-NEXT: vcvttpd2dq %xmm0, %xmm02114; AVX512VL-NEXT: vpmovdb %xmm0, %xmm02115; AVX512VL-NEXT: ret{{[l|q]}}2116;2117; AVX512DQ-LABEL: strict_vector_fptoui_v2f64_to_v2i8:2118; AVX512DQ: # %bb.0:2119; AVX512DQ-NEXT: vcvttpd2dq %xmm0, %xmm02120; AVX512DQ-NEXT: vpackusdw %xmm0, %xmm0, %xmm02121; AVX512DQ-NEXT: vpackuswb %xmm0, %xmm0, %xmm02122; AVX512DQ-NEXT: ret{{[l|q]}}2123;2124; AVX512VLDQ-LABEL: strict_vector_fptoui_v2f64_to_v2i8:2125; AVX512VLDQ: # %bb.0:2126; AVX512VLDQ-NEXT: vcvttpd2dq %xmm0, %xmm02127; AVX512VLDQ-NEXT: vpmovdb %xmm0, %xmm02128; AVX512VLDQ-NEXT: ret{{[l|q]}}2129 %ret = call <2 x i8> @llvm.experimental.constrained.fptoui.v2i8.v2f64(<2 x double> %a,2130 metadata !"fpexcept.strict") #02131 ret <2 x i8> %ret2132}2133 2134define <2 x i8> @strict_vector_fptosi_v2f32_to_v2i8(<2 x float> %a) #0 {2135; SSE-32-LABEL: strict_vector_fptosi_v2f32_to_v2i8:2136; SSE-32: # %bb.0:2137; SSE-32-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero2138; SSE-32-NEXT: cvttps2dq %xmm0, %xmm02139; SSE-32-NEXT: packssdw %xmm0, %xmm02140; SSE-32-NEXT: packsswb %xmm0, %xmm02141; SSE-32-NEXT: retl2142;2143; SSE-64-LABEL: strict_vector_fptosi_v2f32_to_v2i8:2144; SSE-64: # %bb.0:2145; SSE-64-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero2146; SSE-64-NEXT: cvttps2dq %xmm0, %xmm02147; SSE-64-NEXT: packssdw %xmm0, %xmm02148; SSE-64-NEXT: packsswb %xmm0, %xmm02149; SSE-64-NEXT: retq2150;2151; AVX-LABEL: strict_vector_fptosi_v2f32_to_v2i8:2152; AVX: # %bb.0:2153; AVX-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero2154; AVX-NEXT: vcvttps2dq %xmm0, %xmm02155; AVX-NEXT: vpackssdw %xmm0, %xmm0, %xmm02156; AVX-NEXT: vpacksswb %xmm0, %xmm0, %xmm02157; AVX-NEXT: ret{{[l|q]}}2158;2159; AVX512F-LABEL: strict_vector_fptosi_v2f32_to_v2i8:2160; AVX512F: # %bb.0:2161; AVX512F-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero2162; AVX512F-NEXT: vcvttps2dq %xmm0, %xmm02163; AVX512F-NEXT: vpackssdw %xmm0, %xmm0, %xmm02164; AVX512F-NEXT: vpacksswb %xmm0, %xmm0, %xmm02165; AVX512F-NEXT: ret{{[l|q]}}2166;2167; AVX512VL-LABEL: strict_vector_fptosi_v2f32_to_v2i8:2168; AVX512VL: # %bb.0:2169; AVX512VL-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero2170; AVX512VL-NEXT: vcvttps2dq %xmm0, %xmm02171; AVX512VL-NEXT: vpmovdb %xmm0, %xmm02172; AVX512VL-NEXT: ret{{[l|q]}}2173;2174; AVX512DQ-LABEL: strict_vector_fptosi_v2f32_to_v2i8:2175; AVX512DQ: # %bb.0:2176; AVX512DQ-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero2177; AVX512DQ-NEXT: vcvttps2dq %xmm0, %xmm02178; AVX512DQ-NEXT: vpackssdw %xmm0, %xmm0, %xmm02179; AVX512DQ-NEXT: vpacksswb %xmm0, %xmm0, %xmm02180; AVX512DQ-NEXT: ret{{[l|q]}}2181;2182; AVX512VLDQ-LABEL: strict_vector_fptosi_v2f32_to_v2i8:2183; AVX512VLDQ: # %bb.0:2184; AVX512VLDQ-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero2185; AVX512VLDQ-NEXT: vcvttps2dq %xmm0, %xmm02186; AVX512VLDQ-NEXT: vpmovdb %xmm0, %xmm02187; AVX512VLDQ-NEXT: ret{{[l|q]}}2188 %ret = call <2 x i8> @llvm.experimental.constrained.fptosi.v2i8.v2f32(<2 x float> %a,2189 metadata !"fpexcept.strict") #02190 ret <2 x i8> %ret2191}2192 2193define <2 x i8> @strict_vector_fptoui_v2f32_to_v2i8(<2 x float> %a) #0 {2194; SSE-32-LABEL: strict_vector_fptoui_v2f32_to_v2i8:2195; SSE-32: # %bb.0:2196; SSE-32-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero2197; SSE-32-NEXT: cvttps2dq %xmm0, %xmm02198; SSE-32-NEXT: packuswb %xmm0, %xmm02199; SSE-32-NEXT: packuswb %xmm0, %xmm02200; SSE-32-NEXT: retl2201;2202; SSE-64-LABEL: strict_vector_fptoui_v2f32_to_v2i8:2203; SSE-64: # %bb.0:2204; SSE-64-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero2205; SSE-64-NEXT: cvttps2dq %xmm0, %xmm02206; SSE-64-NEXT: packuswb %xmm0, %xmm02207; SSE-64-NEXT: packuswb %xmm0, %xmm02208; SSE-64-NEXT: retq2209;2210; AVX-LABEL: strict_vector_fptoui_v2f32_to_v2i8:2211; AVX: # %bb.0:2212; AVX-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero2213; AVX-NEXT: vcvttps2dq %xmm0, %xmm02214; AVX-NEXT: vpackusdw %xmm0, %xmm0, %xmm02215; AVX-NEXT: vpackuswb %xmm0, %xmm0, %xmm02216; AVX-NEXT: ret{{[l|q]}}2217;2218; AVX512F-LABEL: strict_vector_fptoui_v2f32_to_v2i8:2219; AVX512F: # %bb.0:2220; AVX512F-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero2221; AVX512F-NEXT: vcvttps2dq %xmm0, %xmm02222; AVX512F-NEXT: vpackusdw %xmm0, %xmm0, %xmm02223; AVX512F-NEXT: vpackuswb %xmm0, %xmm0, %xmm02224; AVX512F-NEXT: ret{{[l|q]}}2225;2226; AVX512VL-LABEL: strict_vector_fptoui_v2f32_to_v2i8:2227; AVX512VL: # %bb.0:2228; AVX512VL-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero2229; AVX512VL-NEXT: vcvttps2dq %xmm0, %xmm02230; AVX512VL-NEXT: vpmovdb %xmm0, %xmm02231; AVX512VL-NEXT: ret{{[l|q]}}2232;2233; AVX512DQ-LABEL: strict_vector_fptoui_v2f32_to_v2i8:2234; AVX512DQ: # %bb.0:2235; AVX512DQ-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero2236; AVX512DQ-NEXT: vcvttps2dq %xmm0, %xmm02237; AVX512DQ-NEXT: vpackusdw %xmm0, %xmm0, %xmm02238; AVX512DQ-NEXT: vpackuswb %xmm0, %xmm0, %xmm02239; AVX512DQ-NEXT: ret{{[l|q]}}2240;2241; AVX512VLDQ-LABEL: strict_vector_fptoui_v2f32_to_v2i8:2242; AVX512VLDQ: # %bb.0:2243; AVX512VLDQ-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero2244; AVX512VLDQ-NEXT: vcvttps2dq %xmm0, %xmm02245; AVX512VLDQ-NEXT: vpmovdb %xmm0, %xmm02246; AVX512VLDQ-NEXT: ret{{[l|q]}}2247 %ret = call <2 x i8> @llvm.experimental.constrained.fptoui.v2i8.v2f32(<2 x float> %a,2248 metadata !"fpexcept.strict") #02249 ret <2 x i8> %ret2250}2251 2252define <2 x i1> @strict_vector_fptosi_v2f64_to_v2i1(<2 x double> %a) #0 {2253; SSE-32-LABEL: strict_vector_fptosi_v2f64_to_v2i1:2254; SSE-32: # %bb.0:2255; SSE-32-NEXT: pushl %ebp2256; SSE-32-NEXT: .cfi_def_cfa_offset 82257; SSE-32-NEXT: .cfi_offset %ebp, -82258; SSE-32-NEXT: movl %esp, %ebp2259; SSE-32-NEXT: .cfi_def_cfa_register %ebp2260; SSE-32-NEXT: andl $-8, %esp2261; SSE-32-NEXT: subl $24, %esp2262; SSE-32-NEXT: movhps %xmm0, {{[0-9]+}}(%esp)2263; SSE-32-NEXT: movlps %xmm0, {{[0-9]+}}(%esp)2264; SSE-32-NEXT: fldl {{[0-9]+}}(%esp)2265; SSE-32-NEXT: wait2266; SSE-32-NEXT: fnstcw {{[0-9]+}}(%esp)2267; SSE-32-NEXT: movzwl {{[0-9]+}}(%esp), %eax2268; SSE-32-NEXT: orl $3072, %eax # imm = 0xC002269; SSE-32-NEXT: movw %ax, {{[0-9]+}}(%esp)2270; SSE-32-NEXT: fldcw {{[0-9]+}}(%esp)2271; SSE-32-NEXT: fistpll {{[0-9]+}}(%esp)2272; SSE-32-NEXT: fldcw {{[0-9]+}}(%esp)2273; SSE-32-NEXT: fldl {{[0-9]+}}(%esp)2274; SSE-32-NEXT: wait2275; SSE-32-NEXT: fnstcw (%esp)2276; SSE-32-NEXT: movzwl (%esp), %eax2277; SSE-32-NEXT: orl $3072, %eax # imm = 0xC002278; SSE-32-NEXT: movw %ax, {{[0-9]+}}(%esp)2279; SSE-32-NEXT: fldcw {{[0-9]+}}(%esp)2280; SSE-32-NEXT: fistpll {{[0-9]+}}(%esp)2281; SSE-32-NEXT: fldcw (%esp)2282; SSE-32-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero2283; SSE-32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero2284; SSE-32-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]2285; SSE-32-NEXT: movl %ebp, %esp2286; SSE-32-NEXT: popl %ebp2287; SSE-32-NEXT: .cfi_def_cfa %esp, 42288; SSE-32-NEXT: retl2289;2290; SSE-64-LABEL: strict_vector_fptosi_v2f64_to_v2i1:2291; SSE-64: # %bb.0:2292; SSE-64-NEXT: cvttsd2si %xmm0, %rax2293; SSE-64-NEXT: movq %rax, %xmm12294; SSE-64-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]2295; SSE-64-NEXT: cvttsd2si %xmm0, %rax2296; SSE-64-NEXT: movq %rax, %xmm02297; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]2298; SSE-64-NEXT: movdqa %xmm1, %xmm02299; SSE-64-NEXT: retq2300;2301; AVX-32-LABEL: strict_vector_fptosi_v2f64_to_v2i1:2302; AVX-32: # %bb.0:2303; AVX-32-NEXT: pushl %ebp2304; AVX-32-NEXT: .cfi_def_cfa_offset 82305; AVX-32-NEXT: .cfi_offset %ebp, -82306; AVX-32-NEXT: movl %esp, %ebp2307; AVX-32-NEXT: .cfi_def_cfa_register %ebp2308; AVX-32-NEXT: andl $-8, %esp2309; AVX-32-NEXT: subl $16, %esp2310; AVX-32-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)2311; AVX-32-NEXT: vmovhps %xmm0, (%esp)2312; AVX-32-NEXT: fldl {{[0-9]+}}(%esp)2313; AVX-32-NEXT: fisttpll {{[0-9]+}}(%esp)2314; AVX-32-NEXT: fldl (%esp)2315; AVX-32-NEXT: fisttpll (%esp)2316; AVX-32-NEXT: wait2317; AVX-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero2318; AVX-32-NEXT: vpinsrd $1, {{[0-9]+}}(%esp), %xmm0, %xmm02319; AVX-32-NEXT: vpinsrd $2, (%esp), %xmm0, %xmm02320; AVX-32-NEXT: vpinsrd $3, {{[0-9]+}}(%esp), %xmm0, %xmm02321; AVX-32-NEXT: movl %ebp, %esp2322; AVX-32-NEXT: popl %ebp2323; AVX-32-NEXT: .cfi_def_cfa %esp, 42324; AVX-32-NEXT: retl2325;2326; AVX-64-LABEL: strict_vector_fptosi_v2f64_to_v2i1:2327; AVX-64: # %bb.0:2328; AVX-64-NEXT: vcvttsd2si %xmm0, %rax2329; AVX-64-NEXT: vmovq %rax, %xmm12330; AVX-64-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]2331; AVX-64-NEXT: vcvttsd2si %xmm0, %rax2332; AVX-64-NEXT: vmovq %rax, %xmm02333; AVX-64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]2334; AVX-64-NEXT: retq2335;2336; AVX512F-LABEL: strict_vector_fptosi_v2f64_to_v2i1:2337; AVX512F: # %bb.0:2338; AVX512F-NEXT: vcvttpd2dq %xmm0, %xmm02339; AVX512F-NEXT: vpslld $31, %xmm0, %xmm02340; AVX512F-NEXT: vptestmd %zmm0, %zmm0, %k12341; AVX512F-NEXT: vpternlogq {{.*#+}} zmm0 {%k1} {z} = -12342; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm02343; AVX512F-NEXT: vzeroupper2344; AVX512F-NEXT: ret{{[l|q]}}2345;2346; AVX512VL-LABEL: strict_vector_fptosi_v2f64_to_v2i1:2347; AVX512VL: # %bb.0:2348; AVX512VL-NEXT: vcvttpd2dq %xmm0, %xmm02349; AVX512VL-NEXT: vpslld $31, %xmm0, %xmm02350; AVX512VL-NEXT: vptestmd %xmm0, %xmm0, %k12351; AVX512VL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm02352; AVX512VL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}2353; AVX512VL-NEXT: ret{{[l|q]}}2354;2355; AVX512DQ-LABEL: strict_vector_fptosi_v2f64_to_v2i1:2356; AVX512DQ: # %bb.0:2357; AVX512DQ-NEXT: vcvttpd2dq %xmm0, %xmm02358; AVX512DQ-NEXT: vpslld $31, %xmm0, %xmm02359; AVX512DQ-NEXT: vpmovd2m %zmm0, %k02360; AVX512DQ-NEXT: vpmovm2q %k0, %zmm02361; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm02362; AVX512DQ-NEXT: vzeroupper2363; AVX512DQ-NEXT: ret{{[l|q]}}2364;2365; AVX512VLDQ-LABEL: strict_vector_fptosi_v2f64_to_v2i1:2366; AVX512VLDQ: # %bb.0:2367; AVX512VLDQ-NEXT: vcvttpd2dq %xmm0, %xmm02368; AVX512VLDQ-NEXT: vpslld $31, %xmm0, %xmm02369; AVX512VLDQ-NEXT: vpmovd2m %xmm0, %k02370; AVX512VLDQ-NEXT: vpmovm2q %k0, %xmm02371; AVX512VLDQ-NEXT: ret{{[l|q]}}2372 %ret = call <2 x i1> @llvm.experimental.constrained.fptosi.v2i1.v2f64(<2 x double> %a,2373 metadata !"fpexcept.strict") #02374 ret <2 x i1> %ret2375}2376 2377define <2 x i1> @strict_vector_fptoui_v2f64_to_v2i1(<2 x double> %a) #0 {2378; SSE-32-LABEL: strict_vector_fptoui_v2f64_to_v2i1:2379; SSE-32: # %bb.0:2380; SSE-32-NEXT: pushl %ebp2381; SSE-32-NEXT: .cfi_def_cfa_offset 82382; SSE-32-NEXT: .cfi_offset %ebp, -82383; SSE-32-NEXT: movl %esp, %ebp2384; SSE-32-NEXT: .cfi_def_cfa_register %ebp2385; SSE-32-NEXT: andl $-8, %esp2386; SSE-32-NEXT: subl $24, %esp2387; SSE-32-NEXT: movsd {{.*#+}} xmm1 = [9.2233720368547758E+18,0.0E+0]2388; SSE-32-NEXT: comisd %xmm1, %xmm02389; SSE-32-NEXT: movapd %xmm1, %xmm22390; SSE-32-NEXT: jae .LBB19_22391; SSE-32-NEXT: # %bb.1:2392; SSE-32-NEXT: xorpd %xmm2, %xmm22393; SSE-32-NEXT: .LBB19_2:2394; SSE-32-NEXT: movapd %xmm0, %xmm32395; SSE-32-NEXT: subsd %xmm2, %xmm32396; SSE-32-NEXT: movsd %xmm3, {{[0-9]+}}(%esp)2397; SSE-32-NEXT: setae %al2398; SSE-32-NEXT: fldl {{[0-9]+}}(%esp)2399; SSE-32-NEXT: wait2400; SSE-32-NEXT: fnstcw {{[0-9]+}}(%esp)2401; SSE-32-NEXT: movzwl {{[0-9]+}}(%esp), %ecx2402; SSE-32-NEXT: orl $3072, %ecx # imm = 0xC002403; SSE-32-NEXT: movw %cx, {{[0-9]+}}(%esp)2404; SSE-32-NEXT: fldcw {{[0-9]+}}(%esp)2405; SSE-32-NEXT: fistpll {{[0-9]+}}(%esp)2406; SSE-32-NEXT: fldcw {{[0-9]+}}(%esp)2407; SSE-32-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]2408; SSE-32-NEXT: comisd %xmm1, %xmm02409; SSE-32-NEXT: jae .LBB19_42410; SSE-32-NEXT: # %bb.3:2411; SSE-32-NEXT: xorpd %xmm1, %xmm12412; SSE-32-NEXT: .LBB19_4:2413; SSE-32-NEXT: subsd %xmm1, %xmm02414; SSE-32-NEXT: movsd %xmm0, {{[0-9]+}}(%esp)2415; SSE-32-NEXT: setae %cl2416; SSE-32-NEXT: fldl {{[0-9]+}}(%esp)2417; SSE-32-NEXT: wait2418; SSE-32-NEXT: fnstcw (%esp)2419; SSE-32-NEXT: movzwl (%esp), %edx2420; SSE-32-NEXT: orl $3072, %edx # imm = 0xC002421; SSE-32-NEXT: movw %dx, {{[0-9]+}}(%esp)2422; SSE-32-NEXT: fldcw {{[0-9]+}}(%esp)2423; SSE-32-NEXT: fistpll {{[0-9]+}}(%esp)2424; SSE-32-NEXT: fldcw (%esp)2425; SSE-32-NEXT: movzbl %al, %eax2426; SSE-32-NEXT: shll $31, %eax2427; SSE-32-NEXT: xorl {{[0-9]+}}(%esp), %eax2428; SSE-32-NEXT: movd %eax, %xmm12429; SSE-32-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero2430; SSE-32-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]2431; SSE-32-NEXT: movzbl %cl, %eax2432; SSE-32-NEXT: shll $31, %eax2433; SSE-32-NEXT: xorl {{[0-9]+}}(%esp), %eax2434; SSE-32-NEXT: movd %eax, %xmm12435; SSE-32-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero2436; SSE-32-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]2437; SSE-32-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]2438; SSE-32-NEXT: movl %ebp, %esp2439; SSE-32-NEXT: popl %ebp2440; SSE-32-NEXT: .cfi_def_cfa %esp, 42441; SSE-32-NEXT: retl2442;2443; SSE-64-LABEL: strict_vector_fptoui_v2f64_to_v2i1:2444; SSE-64: # %bb.0:2445; SSE-64-NEXT: movsd {{.*#+}} xmm3 = [9.2233720368547758E+18,0.0E+0]2446; SSE-64-NEXT: comisd %xmm3, %xmm02447; SSE-64-NEXT: xorpd %xmm2, %xmm22448; SSE-64-NEXT: xorpd %xmm1, %xmm12449; SSE-64-NEXT: jb .LBB19_22450; SSE-64-NEXT: # %bb.1:2451; SSE-64-NEXT: movapd %xmm3, %xmm12452; SSE-64-NEXT: .LBB19_2:2453; SSE-64-NEXT: movapd %xmm0, %xmm42454; SSE-64-NEXT: subsd %xmm1, %xmm42455; SSE-64-NEXT: cvttsd2si %xmm4, %rax2456; SSE-64-NEXT: setae %cl2457; SSE-64-NEXT: movzbl %cl, %ecx2458; SSE-64-NEXT: shlq $63, %rcx2459; SSE-64-NEXT: xorq %rax, %rcx2460; SSE-64-NEXT: movq %rcx, %xmm12461; SSE-64-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]2462; SSE-64-NEXT: comisd %xmm3, %xmm02463; SSE-64-NEXT: jb .LBB19_42464; SSE-64-NEXT: # %bb.3:2465; SSE-64-NEXT: movapd %xmm3, %xmm22466; SSE-64-NEXT: .LBB19_4:2467; SSE-64-NEXT: subsd %xmm2, %xmm02468; SSE-64-NEXT: cvttsd2si %xmm0, %rax2469; SSE-64-NEXT: setae %cl2470; SSE-64-NEXT: movzbl %cl, %ecx2471; SSE-64-NEXT: shlq $63, %rcx2472; SSE-64-NEXT: xorq %rax, %rcx2473; SSE-64-NEXT: movq %rcx, %xmm02474; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]2475; SSE-64-NEXT: movdqa %xmm1, %xmm02476; SSE-64-NEXT: retq2477;2478; AVX-32-LABEL: strict_vector_fptoui_v2f64_to_v2i1:2479; AVX-32: # %bb.0:2480; AVX-32-NEXT: pushl %ebp2481; AVX-32-NEXT: .cfi_def_cfa_offset 82482; AVX-32-NEXT: .cfi_offset %ebp, -82483; AVX-32-NEXT: movl %esp, %ebp2484; AVX-32-NEXT: .cfi_def_cfa_register %ebp2485; AVX-32-NEXT: andl $-8, %esp2486; AVX-32-NEXT: subl $16, %esp2487; AVX-32-NEXT: vshufpd {{.*#+}} xmm2 = xmm0[1,0]2488; AVX-32-NEXT: vmovsd {{.*#+}} xmm1 = [9.2233720368547758E+18,0.0E+0]2489; AVX-32-NEXT: vcomisd %xmm1, %xmm22490; AVX-32-NEXT: vmovapd %xmm1, %xmm32491; AVX-32-NEXT: jae .LBB19_22492; AVX-32-NEXT: # %bb.1:2493; AVX-32-NEXT: vxorpd %xmm3, %xmm3, %xmm32494; AVX-32-NEXT: .LBB19_2:2495; AVX-32-NEXT: vsubsd %xmm3, %xmm2, %xmm22496; AVX-32-NEXT: vmovsd %xmm2, (%esp)2497; AVX-32-NEXT: fldl (%esp)2498; AVX-32-NEXT: fisttpll (%esp)2499; AVX-32-NEXT: wait2500; AVX-32-NEXT: setae %al2501; AVX-32-NEXT: movzbl %al, %eax2502; AVX-32-NEXT: shll $31, %eax2503; AVX-32-NEXT: xorl {{[0-9]+}}(%esp), %eax2504; AVX-32-NEXT: vcomisd %xmm1, %xmm02505; AVX-32-NEXT: jae .LBB19_42506; AVX-32-NEXT: # %bb.3:2507; AVX-32-NEXT: vxorpd %xmm1, %xmm1, %xmm12508; AVX-32-NEXT: .LBB19_4:2509; AVX-32-NEXT: vsubsd %xmm1, %xmm0, %xmm02510; AVX-32-NEXT: vmovsd %xmm0, {{[0-9]+}}(%esp)2511; AVX-32-NEXT: fldl {{[0-9]+}}(%esp)2512; AVX-32-NEXT: fisttpll {{[0-9]+}}(%esp)2513; AVX-32-NEXT: wait2514; AVX-32-NEXT: setae %cl2515; AVX-32-NEXT: movzbl %cl, %ecx2516; AVX-32-NEXT: shll $31, %ecx2517; AVX-32-NEXT: xorl {{[0-9]+}}(%esp), %ecx2518; AVX-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero2519; AVX-32-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm02520; AVX-32-NEXT: vpinsrd $2, (%esp), %xmm0, %xmm02521; AVX-32-NEXT: vpinsrd $3, %eax, %xmm0, %xmm02522; AVX-32-NEXT: movl %ebp, %esp2523; AVX-32-NEXT: popl %ebp2524; AVX-32-NEXT: .cfi_def_cfa %esp, 42525; AVX-32-NEXT: retl2526;2527; AVX-64-LABEL: strict_vector_fptoui_v2f64_to_v2i1:2528; AVX-64: # %bb.0:2529; AVX-64-NEXT: vmovsd {{.*#+}} xmm1 = [9.2233720368547758E+18,0.0E+0]2530; AVX-64-NEXT: vcomisd %xmm1, %xmm02531; AVX-64-NEXT: vxorpd %xmm2, %xmm2, %xmm22532; AVX-64-NEXT: vxorpd %xmm3, %xmm3, %xmm32533; AVX-64-NEXT: jb .LBB19_22534; AVX-64-NEXT: # %bb.1:2535; AVX-64-NEXT: vmovapd %xmm1, %xmm32536; AVX-64-NEXT: .LBB19_2:2537; AVX-64-NEXT: vsubsd %xmm3, %xmm0, %xmm32538; AVX-64-NEXT: vcvttsd2si %xmm3, %rax2539; AVX-64-NEXT: setae %cl2540; AVX-64-NEXT: movzbl %cl, %ecx2541; AVX-64-NEXT: shlq $63, %rcx2542; AVX-64-NEXT: xorq %rax, %rcx2543; AVX-64-NEXT: vmovq %rcx, %xmm32544; AVX-64-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]2545; AVX-64-NEXT: vcomisd %xmm1, %xmm02546; AVX-64-NEXT: jb .LBB19_42547; AVX-64-NEXT: # %bb.3:2548; AVX-64-NEXT: vmovapd %xmm1, %xmm22549; AVX-64-NEXT: .LBB19_4:2550; AVX-64-NEXT: vsubsd %xmm2, %xmm0, %xmm02551; AVX-64-NEXT: vcvttsd2si %xmm0, %rax2552; AVX-64-NEXT: setae %cl2553; AVX-64-NEXT: movzbl %cl, %ecx2554; AVX-64-NEXT: shlq $63, %rcx2555; AVX-64-NEXT: xorq %rax, %rcx2556; AVX-64-NEXT: vmovq %rcx, %xmm02557; AVX-64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm3[0],xmm0[0]2558; AVX-64-NEXT: retq2559;2560; AVX512F-LABEL: strict_vector_fptoui_v2f64_to_v2i1:2561; AVX512F: # %bb.0:2562; AVX512F-NEXT: vmovaps %xmm0, %xmm02563; AVX512F-NEXT: vcvttpd2udq %zmm0, %ymm02564; AVX512F-NEXT: vpslld $31, %ymm0, %ymm02565; AVX512F-NEXT: vptestmd %zmm0, %zmm0, %k12566; AVX512F-NEXT: vpternlogq {{.*#+}} zmm0 {%k1} {z} = -12567; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm02568; AVX512F-NEXT: vzeroupper2569; AVX512F-NEXT: ret{{[l|q]}}2570;2571; AVX512VL-LABEL: strict_vector_fptoui_v2f64_to_v2i1:2572; AVX512VL: # %bb.0:2573; AVX512VL-NEXT: vcvttpd2udq %xmm0, %xmm02574; AVX512VL-NEXT: vpslld $31, %xmm0, %xmm02575; AVX512VL-NEXT: vptestmd %xmm0, %xmm0, %k12576; AVX512VL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm02577; AVX512VL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}2578; AVX512VL-NEXT: ret{{[l|q]}}2579;2580; AVX512DQ-LABEL: strict_vector_fptoui_v2f64_to_v2i1:2581; AVX512DQ: # %bb.0:2582; AVX512DQ-NEXT: vmovaps %xmm0, %xmm02583; AVX512DQ-NEXT: vcvttpd2udq %zmm0, %ymm02584; AVX512DQ-NEXT: vpslld $31, %ymm0, %ymm02585; AVX512DQ-NEXT: vpmovd2m %zmm0, %k02586; AVX512DQ-NEXT: vpmovm2q %k0, %zmm02587; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm02588; AVX512DQ-NEXT: vzeroupper2589; AVX512DQ-NEXT: ret{{[l|q]}}2590;2591; AVX512VLDQ-LABEL: strict_vector_fptoui_v2f64_to_v2i1:2592; AVX512VLDQ: # %bb.0:2593; AVX512VLDQ-NEXT: vcvttpd2udq %xmm0, %xmm02594; AVX512VLDQ-NEXT: vpslld $31, %xmm0, %xmm02595; AVX512VLDQ-NEXT: vpmovd2m %xmm0, %k02596; AVX512VLDQ-NEXT: vpmovm2q %k0, %xmm02597; AVX512VLDQ-NEXT: ret{{[l|q]}}2598 %ret = call <2 x i1> @llvm.experimental.constrained.fptoui.v2i1.v2f64(<2 x double> %a,2599 metadata !"fpexcept.strict") #02600 ret <2 x i1> %ret2601}2602 2603define <2 x i1> @strict_vector_fptosi_v2f32_to_v2i1(<2 x float> %a) #0 {2604; SSE-32-LABEL: strict_vector_fptosi_v2f32_to_v2i1:2605; SSE-32: # %bb.0:2606; SSE-32-NEXT: pushl %ebp2607; SSE-32-NEXT: .cfi_def_cfa_offset 82608; SSE-32-NEXT: .cfi_offset %ebp, -82609; SSE-32-NEXT: movl %esp, %ebp2610; SSE-32-NEXT: .cfi_def_cfa_register %ebp2611; SSE-32-NEXT: andl $-8, %esp2612; SSE-32-NEXT: subl $24, %esp2613; SSE-32-NEXT: movss %xmm0, {{[0-9]+}}(%esp)2614; SSE-32-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]2615; SSE-32-NEXT: movss %xmm0, {{[0-9]+}}(%esp)2616; SSE-32-NEXT: flds {{[0-9]+}}(%esp)2617; SSE-32-NEXT: wait2618; SSE-32-NEXT: fnstcw {{[0-9]+}}(%esp)2619; SSE-32-NEXT: movzwl {{[0-9]+}}(%esp), %eax2620; SSE-32-NEXT: orl $3072, %eax # imm = 0xC002621; SSE-32-NEXT: movw %ax, {{[0-9]+}}(%esp)2622; SSE-32-NEXT: fldcw {{[0-9]+}}(%esp)2623; SSE-32-NEXT: fistpll {{[0-9]+}}(%esp)2624; SSE-32-NEXT: fldcw {{[0-9]+}}(%esp)2625; SSE-32-NEXT: flds {{[0-9]+}}(%esp)2626; SSE-32-NEXT: wait2627; SSE-32-NEXT: fnstcw (%esp)2628; SSE-32-NEXT: movzwl (%esp), %eax2629; SSE-32-NEXT: orl $3072, %eax # imm = 0xC002630; SSE-32-NEXT: movw %ax, {{[0-9]+}}(%esp)2631; SSE-32-NEXT: fldcw {{[0-9]+}}(%esp)2632; SSE-32-NEXT: fistpll {{[0-9]+}}(%esp)2633; SSE-32-NEXT: fldcw (%esp)2634; SSE-32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero2635; SSE-32-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero2636; SSE-32-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]2637; SSE-32-NEXT: movl %ebp, %esp2638; SSE-32-NEXT: popl %ebp2639; SSE-32-NEXT: .cfi_def_cfa %esp, 42640; SSE-32-NEXT: retl2641;2642; SSE-64-LABEL: strict_vector_fptosi_v2f32_to_v2i1:2643; SSE-64: # %bb.0:2644; SSE-64-NEXT: cvttss2si %xmm0, %rax2645; SSE-64-NEXT: movq %rax, %xmm12646; SSE-64-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]2647; SSE-64-NEXT: cvttss2si %xmm0, %rax2648; SSE-64-NEXT: movq %rax, %xmm02649; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]2650; SSE-64-NEXT: movdqa %xmm1, %xmm02651; SSE-64-NEXT: retq2652;2653; AVX-32-LABEL: strict_vector_fptosi_v2f32_to_v2i1:2654; AVX-32: # %bb.0:2655; AVX-32-NEXT: pushl %ebp2656; AVX-32-NEXT: .cfi_def_cfa_offset 82657; AVX-32-NEXT: .cfi_offset %ebp, -82658; AVX-32-NEXT: movl %esp, %ebp2659; AVX-32-NEXT: .cfi_def_cfa_register %ebp2660; AVX-32-NEXT: andl $-8, %esp2661; AVX-32-NEXT: subl $16, %esp2662; AVX-32-NEXT: vmovss %xmm0, (%esp)2663; AVX-32-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp)2664; AVX-32-NEXT: flds (%esp)2665; AVX-32-NEXT: fisttpll (%esp)2666; AVX-32-NEXT: flds {{[0-9]+}}(%esp)2667; AVX-32-NEXT: fisttpll {{[0-9]+}}(%esp)2668; AVX-32-NEXT: wait2669; AVX-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero2670; AVX-32-NEXT: vpinsrd $1, {{[0-9]+}}(%esp), %xmm0, %xmm02671; AVX-32-NEXT: vpinsrd $2, {{[0-9]+}}(%esp), %xmm0, %xmm02672; AVX-32-NEXT: vpinsrd $3, {{[0-9]+}}(%esp), %xmm0, %xmm02673; AVX-32-NEXT: movl %ebp, %esp2674; AVX-32-NEXT: popl %ebp2675; AVX-32-NEXT: .cfi_def_cfa %esp, 42676; AVX-32-NEXT: retl2677;2678; AVX-64-LABEL: strict_vector_fptosi_v2f32_to_v2i1:2679; AVX-64: # %bb.0:2680; AVX-64-NEXT: vcvttss2si %xmm0, %rax2681; AVX-64-NEXT: vmovq %rax, %xmm12682; AVX-64-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]2683; AVX-64-NEXT: vcvttss2si %xmm0, %rax2684; AVX-64-NEXT: vmovq %rax, %xmm02685; AVX-64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]2686; AVX-64-NEXT: retq2687;2688; AVX512F-LABEL: strict_vector_fptosi_v2f32_to_v2i1:2689; AVX512F: # %bb.0:2690; AVX512F-NEXT: vcvttss2si %xmm0, %eax2691; AVX512F-NEXT: andl $1, %eax2692; AVX512F-NEXT: kmovw %eax, %k02693; AVX512F-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]2694; AVX512F-NEXT: vcvttss2si %xmm0, %eax2695; AVX512F-NEXT: kmovw %eax, %k12696; AVX512F-NEXT: kshiftlw $1, %k1, %k12697; AVX512F-NEXT: korw %k1, %k0, %k12698; AVX512F-NEXT: vpternlogq {{.*#+}} zmm0 {%k1} {z} = -12699; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm02700; AVX512F-NEXT: vzeroupper2701; AVX512F-NEXT: ret{{[l|q]}}2702;2703; AVX512VL-LABEL: strict_vector_fptosi_v2f32_to_v2i1:2704; AVX512VL: # %bb.0:2705; AVX512VL-NEXT: vcvttss2si %xmm0, %eax2706; AVX512VL-NEXT: andl $1, %eax2707; AVX512VL-NEXT: kmovw %eax, %k02708; AVX512VL-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]2709; AVX512VL-NEXT: vcvttss2si %xmm0, %eax2710; AVX512VL-NEXT: kmovw %eax, %k12711; AVX512VL-NEXT: kshiftlw $1, %k1, %k12712; AVX512VL-NEXT: korw %k1, %k0, %k12713; AVX512VL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm02714; AVX512VL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}2715; AVX512VL-NEXT: ret{{[l|q]}}2716;2717; AVX512DQ-LABEL: strict_vector_fptosi_v2f32_to_v2i1:2718; AVX512DQ: # %bb.0:2719; AVX512DQ-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]2720; AVX512DQ-NEXT: vcvttss2si %xmm1, %eax2721; AVX512DQ-NEXT: kmovw %eax, %k02722; AVX512DQ-NEXT: kshiftlb $1, %k0, %k02723; AVX512DQ-NEXT: vcvttss2si %xmm0, %eax2724; AVX512DQ-NEXT: kmovw %eax, %k12725; AVX512DQ-NEXT: kshiftlb $7, %k1, %k12726; AVX512DQ-NEXT: kshiftrb $7, %k1, %k12727; AVX512DQ-NEXT: korw %k0, %k1, %k02728; AVX512DQ-NEXT: vpmovm2q %k0, %zmm02729; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm02730; AVX512DQ-NEXT: vzeroupper2731; AVX512DQ-NEXT: ret{{[l|q]}}2732;2733; AVX512VLDQ-LABEL: strict_vector_fptosi_v2f32_to_v2i1:2734; AVX512VLDQ: # %bb.0:2735; AVX512VLDQ-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]2736; AVX512VLDQ-NEXT: vcvttss2si %xmm1, %eax2737; AVX512VLDQ-NEXT: kmovw %eax, %k02738; AVX512VLDQ-NEXT: kshiftlb $1, %k0, %k02739; AVX512VLDQ-NEXT: vcvttss2si %xmm0, %eax2740; AVX512VLDQ-NEXT: kmovw %eax, %k12741; AVX512VLDQ-NEXT: kshiftlb $7, %k1, %k12742; AVX512VLDQ-NEXT: kshiftrb $7, %k1, %k12743; AVX512VLDQ-NEXT: korw %k0, %k1, %k02744; AVX512VLDQ-NEXT: vpmovm2q %k0, %xmm02745; AVX512VLDQ-NEXT: ret{{[l|q]}}2746 %ret = call <2 x i1> @llvm.experimental.constrained.fptosi.v2i1.v2f32(<2 x float> %a,2747 metadata !"fpexcept.strict") #02748 ret <2 x i1> %ret2749}2750 2751define <2 x i1> @strict_vector_fptoui_v2f32_to_v2i1(<2 x float> %a) #0 {2752; SSE-32-LABEL: strict_vector_fptoui_v2f32_to_v2i1:2753; SSE-32: # %bb.0:2754; SSE-32-NEXT: pushl %ebp2755; SSE-32-NEXT: .cfi_def_cfa_offset 82756; SSE-32-NEXT: .cfi_offset %ebp, -82757; SSE-32-NEXT: movl %esp, %ebp2758; SSE-32-NEXT: .cfi_def_cfa_register %ebp2759; SSE-32-NEXT: andl $-8, %esp2760; SSE-32-NEXT: subl $24, %esp2761; SSE-32-NEXT: movss {{.*#+}} xmm1 = [9.22337203E+18,0.0E+0,0.0E+0,0.0E+0]2762; SSE-32-NEXT: comiss %xmm1, %xmm02763; SSE-32-NEXT: movaps %xmm1, %xmm22764; SSE-32-NEXT: jae .LBB21_22765; SSE-32-NEXT: # %bb.1:2766; SSE-32-NEXT: xorps %xmm2, %xmm22767; SSE-32-NEXT: .LBB21_2:2768; SSE-32-NEXT: movaps %xmm0, %xmm32769; SSE-32-NEXT: subss %xmm2, %xmm32770; SSE-32-NEXT: movss %xmm3, {{[0-9]+}}(%esp)2771; SSE-32-NEXT: setae %al2772; SSE-32-NEXT: flds {{[0-9]+}}(%esp)2773; SSE-32-NEXT: wait2774; SSE-32-NEXT: fnstcw {{[0-9]+}}(%esp)2775; SSE-32-NEXT: movzwl {{[0-9]+}}(%esp), %ecx2776; SSE-32-NEXT: orl $3072, %ecx # imm = 0xC002777; SSE-32-NEXT: movw %cx, {{[0-9]+}}(%esp)2778; SSE-32-NEXT: fldcw {{[0-9]+}}(%esp)2779; SSE-32-NEXT: fistpll {{[0-9]+}}(%esp)2780; SSE-32-NEXT: fldcw {{[0-9]+}}(%esp)2781; SSE-32-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]2782; SSE-32-NEXT: comiss %xmm1, %xmm02783; SSE-32-NEXT: jae .LBB21_42784; SSE-32-NEXT: # %bb.3:2785; SSE-32-NEXT: xorps %xmm1, %xmm12786; SSE-32-NEXT: .LBB21_4:2787; SSE-32-NEXT: subss %xmm1, %xmm02788; SSE-32-NEXT: movss %xmm0, {{[0-9]+}}(%esp)2789; SSE-32-NEXT: setae %cl2790; SSE-32-NEXT: flds {{[0-9]+}}(%esp)2791; SSE-32-NEXT: wait2792; SSE-32-NEXT: fnstcw (%esp)2793; SSE-32-NEXT: movzwl (%esp), %edx2794; SSE-32-NEXT: orl $3072, %edx # imm = 0xC002795; SSE-32-NEXT: movw %dx, {{[0-9]+}}(%esp)2796; SSE-32-NEXT: fldcw {{[0-9]+}}(%esp)2797; SSE-32-NEXT: fistpll {{[0-9]+}}(%esp)2798; SSE-32-NEXT: fldcw (%esp)2799; SSE-32-NEXT: movzbl %al, %eax2800; SSE-32-NEXT: shll $31, %eax2801; SSE-32-NEXT: xorl {{[0-9]+}}(%esp), %eax2802; SSE-32-NEXT: movd %eax, %xmm12803; SSE-32-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero2804; SSE-32-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]2805; SSE-32-NEXT: movzbl %cl, %eax2806; SSE-32-NEXT: shll $31, %eax2807; SSE-32-NEXT: xorl {{[0-9]+}}(%esp), %eax2808; SSE-32-NEXT: movd %eax, %xmm12809; SSE-32-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero2810; SSE-32-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]2811; SSE-32-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]2812; SSE-32-NEXT: movl %ebp, %esp2813; SSE-32-NEXT: popl %ebp2814; SSE-32-NEXT: .cfi_def_cfa %esp, 42815; SSE-32-NEXT: retl2816;2817; SSE-64-LABEL: strict_vector_fptoui_v2f32_to_v2i1:2818; SSE-64: # %bb.0:2819; SSE-64-NEXT: movss {{.*#+}} xmm3 = [9.22337203E+18,0.0E+0,0.0E+0,0.0E+0]2820; SSE-64-NEXT: comiss %xmm3, %xmm02821; SSE-64-NEXT: xorps %xmm2, %xmm22822; SSE-64-NEXT: xorps %xmm1, %xmm12823; SSE-64-NEXT: jb .LBB21_22824; SSE-64-NEXT: # %bb.1:2825; SSE-64-NEXT: movaps %xmm3, %xmm12826; SSE-64-NEXT: .LBB21_2:2827; SSE-64-NEXT: movaps %xmm0, %xmm42828; SSE-64-NEXT: subss %xmm1, %xmm42829; SSE-64-NEXT: cvttss2si %xmm4, %rax2830; SSE-64-NEXT: setae %cl2831; SSE-64-NEXT: movzbl %cl, %ecx2832; SSE-64-NEXT: shlq $63, %rcx2833; SSE-64-NEXT: xorq %rax, %rcx2834; SSE-64-NEXT: movq %rcx, %xmm12835; SSE-64-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]2836; SSE-64-NEXT: comiss %xmm3, %xmm02837; SSE-64-NEXT: jb .LBB21_42838; SSE-64-NEXT: # %bb.3:2839; SSE-64-NEXT: movaps %xmm3, %xmm22840; SSE-64-NEXT: .LBB21_4:2841; SSE-64-NEXT: subss %xmm2, %xmm02842; SSE-64-NEXT: cvttss2si %xmm0, %rax2843; SSE-64-NEXT: setae %cl2844; SSE-64-NEXT: movzbl %cl, %ecx2845; SSE-64-NEXT: shlq $63, %rcx2846; SSE-64-NEXT: xorq %rax, %rcx2847; SSE-64-NEXT: movq %rcx, %xmm02848; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]2849; SSE-64-NEXT: movdqa %xmm1, %xmm02850; SSE-64-NEXT: retq2851;2852; AVX-32-LABEL: strict_vector_fptoui_v2f32_to_v2i1:2853; AVX-32: # %bb.0:2854; AVX-32-NEXT: pushl %ebp2855; AVX-32-NEXT: .cfi_def_cfa_offset 82856; AVX-32-NEXT: .cfi_offset %ebp, -82857; AVX-32-NEXT: movl %esp, %ebp2858; AVX-32-NEXT: .cfi_def_cfa_register %ebp2859; AVX-32-NEXT: andl $-8, %esp2860; AVX-32-NEXT: subl $16, %esp2861; AVX-32-NEXT: vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]2862; AVX-32-NEXT: vmovss {{.*#+}} xmm1 = [9.22337203E+18,0.0E+0,0.0E+0,0.0E+0]2863; AVX-32-NEXT: vcomiss %xmm1, %xmm22864; AVX-32-NEXT: vmovaps %xmm1, %xmm32865; AVX-32-NEXT: jae .LBB21_22866; AVX-32-NEXT: # %bb.1:2867; AVX-32-NEXT: vxorps %xmm3, %xmm3, %xmm32868; AVX-32-NEXT: .LBB21_2:2869; AVX-32-NEXT: vsubss %xmm3, %xmm2, %xmm22870; AVX-32-NEXT: vmovss %xmm2, {{[0-9]+}}(%esp)2871; AVX-32-NEXT: flds {{[0-9]+}}(%esp)2872; AVX-32-NEXT: fisttpll {{[0-9]+}}(%esp)2873; AVX-32-NEXT: wait2874; AVX-32-NEXT: setae %al2875; AVX-32-NEXT: movzbl %al, %eax2876; AVX-32-NEXT: shll $31, %eax2877; AVX-32-NEXT: xorl {{[0-9]+}}(%esp), %eax2878; AVX-32-NEXT: vcomiss %xmm1, %xmm02879; AVX-32-NEXT: jae .LBB21_42880; AVX-32-NEXT: # %bb.3:2881; AVX-32-NEXT: vxorps %xmm1, %xmm1, %xmm12882; AVX-32-NEXT: .LBB21_4:2883; AVX-32-NEXT: vsubss %xmm1, %xmm0, %xmm02884; AVX-32-NEXT: vmovss %xmm0, (%esp)2885; AVX-32-NEXT: flds (%esp)2886; AVX-32-NEXT: fisttpll (%esp)2887; AVX-32-NEXT: wait2888; AVX-32-NEXT: setae %cl2889; AVX-32-NEXT: movzbl %cl, %ecx2890; AVX-32-NEXT: shll $31, %ecx2891; AVX-32-NEXT: xorl {{[0-9]+}}(%esp), %ecx2892; AVX-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero2893; AVX-32-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm02894; AVX-32-NEXT: vpinsrd $2, {{[0-9]+}}(%esp), %xmm0, %xmm02895; AVX-32-NEXT: vpinsrd $3, %eax, %xmm0, %xmm02896; AVX-32-NEXT: movl %ebp, %esp2897; AVX-32-NEXT: popl %ebp2898; AVX-32-NEXT: .cfi_def_cfa %esp, 42899; AVX-32-NEXT: retl2900;2901; AVX-64-LABEL: strict_vector_fptoui_v2f32_to_v2i1:2902; AVX-64: # %bb.0:2903; AVX-64-NEXT: vmovss {{.*#+}} xmm1 = [9.22337203E+18,0.0E+0,0.0E+0,0.0E+0]2904; AVX-64-NEXT: vcomiss %xmm1, %xmm02905; AVX-64-NEXT: vxorps %xmm2, %xmm2, %xmm22906; AVX-64-NEXT: vxorps %xmm3, %xmm3, %xmm32907; AVX-64-NEXT: jb .LBB21_22908; AVX-64-NEXT: # %bb.1:2909; AVX-64-NEXT: vmovaps %xmm1, %xmm32910; AVX-64-NEXT: .LBB21_2:2911; AVX-64-NEXT: vsubss %xmm3, %xmm0, %xmm32912; AVX-64-NEXT: vcvttss2si %xmm3, %rax2913; AVX-64-NEXT: setae %cl2914; AVX-64-NEXT: movzbl %cl, %ecx2915; AVX-64-NEXT: shlq $63, %rcx2916; AVX-64-NEXT: xorq %rax, %rcx2917; AVX-64-NEXT: vmovq %rcx, %xmm32918; AVX-64-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]2919; AVX-64-NEXT: vcomiss %xmm1, %xmm02920; AVX-64-NEXT: jb .LBB21_42921; AVX-64-NEXT: # %bb.3:2922; AVX-64-NEXT: vmovaps %xmm1, %xmm22923; AVX-64-NEXT: .LBB21_4:2924; AVX-64-NEXT: vsubss %xmm2, %xmm0, %xmm02925; AVX-64-NEXT: vcvttss2si %xmm0, %rax2926; AVX-64-NEXT: setae %cl2927; AVX-64-NEXT: movzbl %cl, %ecx2928; AVX-64-NEXT: shlq $63, %rcx2929; AVX-64-NEXT: xorq %rax, %rcx2930; AVX-64-NEXT: vmovq %rcx, %xmm02931; AVX-64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm3[0],xmm0[0]2932; AVX-64-NEXT: retq2933;2934; AVX512F-LABEL: strict_vector_fptoui_v2f32_to_v2i1:2935; AVX512F: # %bb.0:2936; AVX512F-NEXT: vcvttss2si %xmm0, %eax2937; AVX512F-NEXT: andl $1, %eax2938; AVX512F-NEXT: kmovw %eax, %k02939; AVX512F-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]2940; AVX512F-NEXT: vcvttss2si %xmm0, %eax2941; AVX512F-NEXT: kmovw %eax, %k12942; AVX512F-NEXT: kshiftlw $1, %k1, %k12943; AVX512F-NEXT: korw %k1, %k0, %k12944; AVX512F-NEXT: vpternlogq {{.*#+}} zmm0 {%k1} {z} = -12945; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm02946; AVX512F-NEXT: vzeroupper2947; AVX512F-NEXT: ret{{[l|q]}}2948;2949; AVX512VL-LABEL: strict_vector_fptoui_v2f32_to_v2i1:2950; AVX512VL: # %bb.0:2951; AVX512VL-NEXT: vcvttss2si %xmm0, %eax2952; AVX512VL-NEXT: andl $1, %eax2953; AVX512VL-NEXT: kmovw %eax, %k02954; AVX512VL-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]2955; AVX512VL-NEXT: vcvttss2si %xmm0, %eax2956; AVX512VL-NEXT: kmovw %eax, %k12957; AVX512VL-NEXT: kshiftlw $1, %k1, %k12958; AVX512VL-NEXT: korw %k1, %k0, %k12959; AVX512VL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm02960; AVX512VL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}2961; AVX512VL-NEXT: ret{{[l|q]}}2962;2963; AVX512DQ-LABEL: strict_vector_fptoui_v2f32_to_v2i1:2964; AVX512DQ: # %bb.0:2965; AVX512DQ-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]2966; AVX512DQ-NEXT: vcvttss2si %xmm1, %eax2967; AVX512DQ-NEXT: kmovw %eax, %k02968; AVX512DQ-NEXT: kshiftlb $1, %k0, %k02969; AVX512DQ-NEXT: vcvttss2si %xmm0, %eax2970; AVX512DQ-NEXT: kmovw %eax, %k12971; AVX512DQ-NEXT: kshiftlb $7, %k1, %k12972; AVX512DQ-NEXT: kshiftrb $7, %k1, %k12973; AVX512DQ-NEXT: korw %k0, %k1, %k02974; AVX512DQ-NEXT: vpmovm2q %k0, %zmm02975; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm02976; AVX512DQ-NEXT: vzeroupper2977; AVX512DQ-NEXT: ret{{[l|q]}}2978;2979; AVX512VLDQ-LABEL: strict_vector_fptoui_v2f32_to_v2i1:2980; AVX512VLDQ: # %bb.0:2981; AVX512VLDQ-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]2982; AVX512VLDQ-NEXT: vcvttss2si %xmm1, %eax2983; AVX512VLDQ-NEXT: kmovw %eax, %k02984; AVX512VLDQ-NEXT: kshiftlb $1, %k0, %k02985; AVX512VLDQ-NEXT: vcvttss2si %xmm0, %eax2986; AVX512VLDQ-NEXT: kmovw %eax, %k12987; AVX512VLDQ-NEXT: kshiftlb $7, %k1, %k12988; AVX512VLDQ-NEXT: kshiftrb $7, %k1, %k12989; AVX512VLDQ-NEXT: korw %k0, %k1, %k02990; AVX512VLDQ-NEXT: vpmovm2q %k0, %xmm02991; AVX512VLDQ-NEXT: ret{{[l|q]}}2992 %ret = call <2 x i1> @llvm.experimental.constrained.fptoui.v2i1.v2f32(<2 x float> %a,2993 metadata !"fpexcept.strict") #02994 ret <2 x i1> %ret2995}2996 2997define <4 x i32> @strict_vector_fptosi_v4f32_to_v4i32(<4 x float> %a) #0 {2998; SSE-32-LABEL: strict_vector_fptosi_v4f32_to_v4i32:2999; SSE-32: # %bb.0:3000; SSE-32-NEXT: cvttps2dq %xmm0, %xmm03001; SSE-32-NEXT: retl3002;3003; SSE-64-LABEL: strict_vector_fptosi_v4f32_to_v4i32:3004; SSE-64: # %bb.0:3005; SSE-64-NEXT: cvttps2dq %xmm0, %xmm03006; SSE-64-NEXT: retq3007;3008; AVX-LABEL: strict_vector_fptosi_v4f32_to_v4i32:3009; AVX: # %bb.0:3010; AVX-NEXT: vcvttps2dq %xmm0, %xmm03011; AVX-NEXT: ret{{[l|q]}}3012;3013; AVX512F-LABEL: strict_vector_fptosi_v4f32_to_v4i32:3014; AVX512F: # %bb.0:3015; AVX512F-NEXT: vcvttps2dq %xmm0, %xmm03016; AVX512F-NEXT: ret{{[l|q]}}3017;3018; AVX512VL-LABEL: strict_vector_fptosi_v4f32_to_v4i32:3019; AVX512VL: # %bb.0:3020; AVX512VL-NEXT: vcvttps2dq %xmm0, %xmm03021; AVX512VL-NEXT: ret{{[l|q]}}3022;3023; AVX512DQ-LABEL: strict_vector_fptosi_v4f32_to_v4i32:3024; AVX512DQ: # %bb.0:3025; AVX512DQ-NEXT: vcvttps2dq %xmm0, %xmm03026; AVX512DQ-NEXT: ret{{[l|q]}}3027;3028; AVX512VLDQ-LABEL: strict_vector_fptosi_v4f32_to_v4i32:3029; AVX512VLDQ: # %bb.0:3030; AVX512VLDQ-NEXT: vcvttps2dq %xmm0, %xmm03031; AVX512VLDQ-NEXT: ret{{[l|q]}}3032 %ret = call <4 x i32> @llvm.experimental.constrained.fptosi.v4i32.v4f32(<4 x float> %a,3033 metadata !"fpexcept.strict") #03034 ret <4 x i32> %ret3035}3036 3037define <4 x i32> @strict_vector_fptoui_v4f32_to_v4i32(<4 x float> %a) #0 {3038; SSE-32-LABEL: strict_vector_fptoui_v4f32_to_v4i32:3039; SSE-32: # %bb.0:3040; SSE-32-NEXT: movaps {{.*#+}} xmm1 = [2.14748365E+9,2.14748365E+9,2.14748365E+9,2.14748365E+9]3041; SSE-32-NEXT: movaps %xmm0, %xmm23042; SSE-32-NEXT: cmpltps %xmm1, %xmm23043; SSE-32-NEXT: movaps %xmm2, %xmm33044; SSE-32-NEXT: andnps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm33045; SSE-32-NEXT: andnps %xmm1, %xmm23046; SSE-32-NEXT: subps %xmm2, %xmm03047; SSE-32-NEXT: cvttps2dq %xmm0, %xmm03048; SSE-32-NEXT: xorps %xmm3, %xmm03049; SSE-32-NEXT: retl3050;3051; SSE-64-LABEL: strict_vector_fptoui_v4f32_to_v4i32:3052; SSE-64: # %bb.0:3053; SSE-64-NEXT: movaps {{.*#+}} xmm1 = [2.14748365E+9,2.14748365E+9,2.14748365E+9,2.14748365E+9]3054; SSE-64-NEXT: movaps %xmm0, %xmm23055; SSE-64-NEXT: cmpltps %xmm1, %xmm23056; SSE-64-NEXT: movaps %xmm2, %xmm33057; SSE-64-NEXT: andnps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm33058; SSE-64-NEXT: andnps %xmm1, %xmm23059; SSE-64-NEXT: subps %xmm2, %xmm03060; SSE-64-NEXT: cvttps2dq %xmm0, %xmm03061; SSE-64-NEXT: xorps %xmm3, %xmm03062; SSE-64-NEXT: retq3063;3064; AVX-LABEL: strict_vector_fptoui_v4f32_to_v4i32:3065; AVX: # %bb.0:3066; AVX-NEXT: vbroadcastss {{.*#+}} xmm1 = [2.14748365E+9,2.14748365E+9,2.14748365E+9,2.14748365E+9]3067; AVX-NEXT: vcmpltps %xmm1, %xmm0, %xmm23068; AVX-NEXT: vxorps %xmm3, %xmm3, %xmm33069; AVX-NEXT: vbroadcastss {{.*#+}} xmm4 = [2147483648,2147483648,2147483648,2147483648]3070; AVX-NEXT: vblendvps %xmm2, %xmm3, %xmm4, %xmm43071; AVX-NEXT: vblendvps %xmm2, %xmm3, %xmm1, %xmm13072; AVX-NEXT: vsubps %xmm1, %xmm0, %xmm03073; AVX-NEXT: vcvttps2dq %xmm0, %xmm03074; AVX-NEXT: vxorps %xmm4, %xmm0, %xmm03075; AVX-NEXT: ret{{[l|q]}}3076;3077; AVX512F-LABEL: strict_vector_fptoui_v4f32_to_v4i32:3078; AVX512F: # %bb.0:3079; AVX512F-NEXT: vmovaps %xmm0, %xmm03080; AVX512F-NEXT: vcvttps2udq %zmm0, %zmm03081; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm03082; AVX512F-NEXT: vzeroupper3083; AVX512F-NEXT: ret{{[l|q]}}3084;3085; AVX512VL-LABEL: strict_vector_fptoui_v4f32_to_v4i32:3086; AVX512VL: # %bb.0:3087; AVX512VL-NEXT: vcvttps2udq %xmm0, %xmm03088; AVX512VL-NEXT: ret{{[l|q]}}3089;3090; AVX512DQ-LABEL: strict_vector_fptoui_v4f32_to_v4i32:3091; AVX512DQ: # %bb.0:3092; AVX512DQ-NEXT: vmovaps %xmm0, %xmm03093; AVX512DQ-NEXT: vcvttps2udq %zmm0, %zmm03094; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm03095; AVX512DQ-NEXT: vzeroupper3096; AVX512DQ-NEXT: ret{{[l|q]}}3097;3098; AVX512VLDQ-LABEL: strict_vector_fptoui_v4f32_to_v4i32:3099; AVX512VLDQ: # %bb.0:3100; AVX512VLDQ-NEXT: vcvttps2udq %xmm0, %xmm03101; AVX512VLDQ-NEXT: ret{{[l|q]}}3102 %ret = call <4 x i32> @llvm.experimental.constrained.fptoui.v4i32.v4f32(<4 x float> %a,3103 metadata !"fpexcept.strict") #03104 ret <4 x i32> %ret3105}3106 3107define <4 x i8> @strict_vector_fptosi_v4f32_to_v4i8(<4 x float> %a) #0 {3108; SSE-32-LABEL: strict_vector_fptosi_v4f32_to_v4i8:3109; SSE-32: # %bb.0:3110; SSE-32-NEXT: cvttps2dq %xmm0, %xmm03111; SSE-32-NEXT: packssdw %xmm0, %xmm03112; SSE-32-NEXT: packsswb %xmm0, %xmm03113; SSE-32-NEXT: retl3114;3115; SSE-64-LABEL: strict_vector_fptosi_v4f32_to_v4i8:3116; SSE-64: # %bb.0:3117; SSE-64-NEXT: cvttps2dq %xmm0, %xmm03118; SSE-64-NEXT: packssdw %xmm0, %xmm03119; SSE-64-NEXT: packsswb %xmm0, %xmm03120; SSE-64-NEXT: retq3121;3122; AVX-LABEL: strict_vector_fptosi_v4f32_to_v4i8:3123; AVX: # %bb.0:3124; AVX-NEXT: vcvttps2dq %xmm0, %xmm03125; AVX-NEXT: vpackssdw %xmm0, %xmm0, %xmm03126; AVX-NEXT: vpacksswb %xmm0, %xmm0, %xmm03127; AVX-NEXT: ret{{[l|q]}}3128;3129; AVX512F-LABEL: strict_vector_fptosi_v4f32_to_v4i8:3130; AVX512F: # %bb.0:3131; AVX512F-NEXT: vcvttps2dq %xmm0, %xmm03132; AVX512F-NEXT: vpackssdw %xmm0, %xmm0, %xmm03133; AVX512F-NEXT: vpacksswb %xmm0, %xmm0, %xmm03134; AVX512F-NEXT: ret{{[l|q]}}3135;3136; AVX512VL-LABEL: strict_vector_fptosi_v4f32_to_v4i8:3137; AVX512VL: # %bb.0:3138; AVX512VL-NEXT: vcvttps2dq %xmm0, %xmm03139; AVX512VL-NEXT: vpmovdb %xmm0, %xmm03140; AVX512VL-NEXT: ret{{[l|q]}}3141;3142; AVX512DQ-LABEL: strict_vector_fptosi_v4f32_to_v4i8:3143; AVX512DQ: # %bb.0:3144; AVX512DQ-NEXT: vcvttps2dq %xmm0, %xmm03145; AVX512DQ-NEXT: vpackssdw %xmm0, %xmm0, %xmm03146; AVX512DQ-NEXT: vpacksswb %xmm0, %xmm0, %xmm03147; AVX512DQ-NEXT: ret{{[l|q]}}3148;3149; AVX512VLDQ-LABEL: strict_vector_fptosi_v4f32_to_v4i8:3150; AVX512VLDQ: # %bb.0:3151; AVX512VLDQ-NEXT: vcvttps2dq %xmm0, %xmm03152; AVX512VLDQ-NEXT: vpmovdb %xmm0, %xmm03153; AVX512VLDQ-NEXT: ret{{[l|q]}}3154 %ret = call <4 x i8> @llvm.experimental.constrained.fptosi.v4i8.v4f32(<4 x float> %a,3155 metadata !"fpexcept.strict") #03156 ret <4 x i8> %ret3157}3158 3159define <4 x i8> @strict_vector_fptoui_v4f32_to_v4i8(<4 x float> %a) #0 {3160; SSE-32-LABEL: strict_vector_fptoui_v4f32_to_v4i8:3161; SSE-32: # %bb.0:3162; SSE-32-NEXT: cvttps2dq %xmm0, %xmm03163; SSE-32-NEXT: packuswb %xmm0, %xmm03164; SSE-32-NEXT: packuswb %xmm0, %xmm03165; SSE-32-NEXT: retl3166;3167; SSE-64-LABEL: strict_vector_fptoui_v4f32_to_v4i8:3168; SSE-64: # %bb.0:3169; SSE-64-NEXT: cvttps2dq %xmm0, %xmm03170; SSE-64-NEXT: packuswb %xmm0, %xmm03171; SSE-64-NEXT: packuswb %xmm0, %xmm03172; SSE-64-NEXT: retq3173;3174; AVX-LABEL: strict_vector_fptoui_v4f32_to_v4i8:3175; AVX: # %bb.0:3176; AVX-NEXT: vcvttps2dq %xmm0, %xmm03177; AVX-NEXT: vpackusdw %xmm0, %xmm0, %xmm03178; AVX-NEXT: vpackuswb %xmm0, %xmm0, %xmm03179; AVX-NEXT: ret{{[l|q]}}3180;3181; AVX512F-LABEL: strict_vector_fptoui_v4f32_to_v4i8:3182; AVX512F: # %bb.0:3183; AVX512F-NEXT: vcvttps2dq %xmm0, %xmm03184; AVX512F-NEXT: vpackusdw %xmm0, %xmm0, %xmm03185; AVX512F-NEXT: vpackuswb %xmm0, %xmm0, %xmm03186; AVX512F-NEXT: ret{{[l|q]}}3187;3188; AVX512VL-LABEL: strict_vector_fptoui_v4f32_to_v4i8:3189; AVX512VL: # %bb.0:3190; AVX512VL-NEXT: vcvttps2dq %xmm0, %xmm03191; AVX512VL-NEXT: vpmovdb %xmm0, %xmm03192; AVX512VL-NEXT: ret{{[l|q]}}3193;3194; AVX512DQ-LABEL: strict_vector_fptoui_v4f32_to_v4i8:3195; AVX512DQ: # %bb.0:3196; AVX512DQ-NEXT: vcvttps2dq %xmm0, %xmm03197; AVX512DQ-NEXT: vpackusdw %xmm0, %xmm0, %xmm03198; AVX512DQ-NEXT: vpackuswb %xmm0, %xmm0, %xmm03199; AVX512DQ-NEXT: ret{{[l|q]}}3200;3201; AVX512VLDQ-LABEL: strict_vector_fptoui_v4f32_to_v4i8:3202; AVX512VLDQ: # %bb.0:3203; AVX512VLDQ-NEXT: vcvttps2dq %xmm0, %xmm03204; AVX512VLDQ-NEXT: vpmovdb %xmm0, %xmm03205; AVX512VLDQ-NEXT: ret{{[l|q]}}3206 %ret = call <4 x i8> @llvm.experimental.constrained.fptoui.v4i8.v4f32(<4 x float> %a,3207 metadata !"fpexcept.strict") #03208 ret <4 x i8> %ret3209}3210 3211define <4 x i1> @strict_vector_fptosi_v4f32_to_v4i1(<4 x float> %a) #0 {3212; SSE-32-LABEL: strict_vector_fptosi_v4f32_to_v4i1:3213; SSE-32: # %bb.0:3214; SSE-32-NEXT: cvttps2dq %xmm0, %xmm03215; SSE-32-NEXT: retl3216;3217; SSE-64-LABEL: strict_vector_fptosi_v4f32_to_v4i1:3218; SSE-64: # %bb.0:3219; SSE-64-NEXT: cvttps2dq %xmm0, %xmm03220; SSE-64-NEXT: retq3221;3222; AVX-LABEL: strict_vector_fptosi_v4f32_to_v4i1:3223; AVX: # %bb.0:3224; AVX-NEXT: vcvttps2dq %xmm0, %xmm03225; AVX-NEXT: ret{{[l|q]}}3226;3227; AVX512F-LABEL: strict_vector_fptosi_v4f32_to_v4i1:3228; AVX512F: # %bb.0:3229; AVX512F-NEXT: vcvttps2dq %xmm0, %xmm03230; AVX512F-NEXT: vptestmd %zmm0, %zmm0, %k13231; AVX512F-NEXT: vpternlogd {{.*#+}} zmm0 {%k1} {z} = -13232; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm03233; AVX512F-NEXT: vzeroupper3234; AVX512F-NEXT: ret{{[l|q]}}3235;3236; AVX512VL-LABEL: strict_vector_fptosi_v4f32_to_v4i1:3237; AVX512VL: # %bb.0:3238; AVX512VL-NEXT: vcvttps2dq %xmm0, %xmm03239; AVX512VL-NEXT: vptestmd %xmm0, %xmm0, %k13240; AVX512VL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm03241; AVX512VL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}3242; AVX512VL-NEXT: ret{{[l|q]}}3243;3244; AVX512DQ-LABEL: strict_vector_fptosi_v4f32_to_v4i1:3245; AVX512DQ: # %bb.0:3246; AVX512DQ-NEXT: vcvttps2dq %xmm0, %xmm03247; AVX512DQ-NEXT: vpmovd2m %zmm0, %k03248; AVX512DQ-NEXT: vpmovm2d %k0, %zmm03249; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm03250; AVX512DQ-NEXT: vzeroupper3251; AVX512DQ-NEXT: ret{{[l|q]}}3252;3253; AVX512VLDQ-LABEL: strict_vector_fptosi_v4f32_to_v4i1:3254; AVX512VLDQ: # %bb.0:3255; AVX512VLDQ-NEXT: vcvttps2dq %xmm0, %xmm03256; AVX512VLDQ-NEXT: vpmovd2m %xmm0, %k03257; AVX512VLDQ-NEXT: vpmovm2d %k0, %xmm03258; AVX512VLDQ-NEXT: ret{{[l|q]}}3259 %ret = call <4 x i1> @llvm.experimental.constrained.fptosi.v4i1.v4f32(<4 x float> %a,3260 metadata !"fpexcept.strict") #03261 ret <4 x i1> %ret3262}3263 3264define <4 x i1> @strict_vector_fptoui_v4f32_to_v4i1(<4 x float> %a) #0 {3265; SSE-32-LABEL: strict_vector_fptoui_v4f32_to_v4i1:3266; SSE-32: # %bb.0:3267; SSE-32-NEXT: cvttps2dq %xmm0, %xmm03268; SSE-32-NEXT: retl3269;3270; SSE-64-LABEL: strict_vector_fptoui_v4f32_to_v4i1:3271; SSE-64: # %bb.0:3272; SSE-64-NEXT: cvttps2dq %xmm0, %xmm03273; SSE-64-NEXT: retq3274;3275; AVX-LABEL: strict_vector_fptoui_v4f32_to_v4i1:3276; AVX: # %bb.0:3277; AVX-NEXT: vcvttps2dq %xmm0, %xmm03278; AVX-NEXT: ret{{[l|q]}}3279;3280; AVX512F-LABEL: strict_vector_fptoui_v4f32_to_v4i1:3281; AVX512F: # %bb.0:3282; AVX512F-NEXT: vcvttps2dq %xmm0, %xmm03283; AVX512F-NEXT: vpslld $31, %xmm0, %xmm03284; AVX512F-NEXT: vptestmd %zmm0, %zmm0, %k13285; AVX512F-NEXT: vpternlogd {{.*#+}} zmm0 {%k1} {z} = -13286; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm03287; AVX512F-NEXT: vzeroupper3288; AVX512F-NEXT: ret{{[l|q]}}3289;3290; AVX512VL-LABEL: strict_vector_fptoui_v4f32_to_v4i1:3291; AVX512VL: # %bb.0:3292; AVX512VL-NEXT: vcvttps2dq %xmm0, %xmm03293; AVX512VL-NEXT: vpslld $31, %xmm0, %xmm03294; AVX512VL-NEXT: vptestmd %xmm0, %xmm0, %k13295; AVX512VL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm03296; AVX512VL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}3297; AVX512VL-NEXT: ret{{[l|q]}}3298;3299; AVX512DQ-LABEL: strict_vector_fptoui_v4f32_to_v4i1:3300; AVX512DQ: # %bb.0:3301; AVX512DQ-NEXT: vcvttps2dq %xmm0, %xmm03302; AVX512DQ-NEXT: vpslld $31, %xmm0, %xmm03303; AVX512DQ-NEXT: vpmovd2m %zmm0, %k03304; AVX512DQ-NEXT: vpmovm2d %k0, %zmm03305; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm03306; AVX512DQ-NEXT: vzeroupper3307; AVX512DQ-NEXT: ret{{[l|q]}}3308;3309; AVX512VLDQ-LABEL: strict_vector_fptoui_v4f32_to_v4i1:3310; AVX512VLDQ: # %bb.0:3311; AVX512VLDQ-NEXT: vcvttps2dq %xmm0, %xmm03312; AVX512VLDQ-NEXT: vpslld $31, %xmm0, %xmm03313; AVX512VLDQ-NEXT: vpmovd2m %xmm0, %k03314; AVX512VLDQ-NEXT: vpmovm2d %k0, %xmm03315; AVX512VLDQ-NEXT: ret{{[l|q]}}3316 %ret = call <4 x i1> @llvm.experimental.constrained.fptoui.v4i1.v4f32(<4 x float> %a,3317 metadata !"fpexcept.strict") #03318 ret <4 x i1> %ret3319}3320 3321attributes #0 = { strictfp }3322