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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512f,avx512vl -O3 | FileCheck %s --check-prefixes=CHECK,AVX512VL,AVX512VL-323; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,avx512vl -O3 | FileCheck %s --check-prefixes=CHECK,AVX512VL,AVX512VL-644; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=avx512f,avx512dq -O3 | FileCheck %s --check-prefixes=CHECK,AVX512DQ5; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f,avx512dq -O3 | FileCheck %s --check-prefixes=CHECK,AVX512DQ6 7declare <8 x i64> @llvm.experimental.constrained.fptosi.v8i64.v8f64(<8 x double>, metadata)8declare <8 x i64> @llvm.experimental.constrained.fptoui.v8i64.v8f64(<8 x double>, metadata)9declare <8 x i64> @llvm.experimental.constrained.fptosi.v8i64.v8f32(<8 x float>, metadata)10declare <8 x i64> @llvm.experimental.constrained.fptoui.v8i64.v8f32(<8 x float>, metadata)11declare <8 x i32> @llvm.experimental.constrained.fptosi.v8i32.v8f64(<8 x double>, metadata)12declare <8 x i32> @llvm.experimental.constrained.fptoui.v8i32.v8f64(<8 x double>, metadata)13declare <8 x i16> @llvm.experimental.constrained.fptosi.v8i16.v8f64(<8 x double>, metadata)14declare <8 x i16> @llvm.experimental.constrained.fptoui.v8i16.v8f64(<8 x double>, metadata)15declare <8 x i8> @llvm.experimental.constrained.fptosi.v8i8.v8f64(<8 x double>, metadata)16declare <8 x i8> @llvm.experimental.constrained.fptoui.v8i8.v8f64(<8 x double>, metadata)17declare <8 x i1> @llvm.experimental.constrained.fptosi.v8i1.v8f64(<8 x double>, metadata)18declare <8 x i1> @llvm.experimental.constrained.fptoui.v8i1.v8f64(<8 x double>, metadata)19declare <8 x i1> @llvm.experimental.constrained.fptosi.v8i1.v8f32(<8 x float>, metadata)20declare <8 x i1> @llvm.experimental.constrained.fptoui.v8i1.v8f32(<8 x float>, metadata)21 22declare <16 x i32> @llvm.experimental.constrained.fptosi.v16i32.v16f32(<16 x float>, metadata)23declare <16 x i32> @llvm.experimental.constrained.fptoui.v16i32.v16f32(<16 x float>, metadata)24declare <16 x i16> @llvm.experimental.constrained.fptosi.v16i16.v16f32(<16 x float>, metadata)25declare <16 x i16> @llvm.experimental.constrained.fptoui.v16i16.v16f32(<16 x float>, metadata)26declare <16 x i8> @llvm.experimental.constrained.fptosi.v16i8.v16f32(<16 x float>, metadata)27declare <16 x i8> @llvm.experimental.constrained.fptoui.v16i8.v16f32(<16 x float>, metadata)28declare <16 x i1> @llvm.experimental.constrained.fptosi.v16i1.v16f32(<16 x float>, metadata)29declare <16 x i1> @llvm.experimental.constrained.fptoui.v16i1.v16f32(<16 x float>, metadata)30 31define <8 x i64> @strict_vector_fptosi_v8f64_to_v8i64(<8 x double> %a) #0 {32; AVX512VL-32-LABEL: strict_vector_fptosi_v8f64_to_v8i64:33; AVX512VL-32: # %bb.0:34; AVX512VL-32-NEXT: pushl %ebp35; AVX512VL-32-NEXT: .cfi_def_cfa_offset 836; AVX512VL-32-NEXT: .cfi_offset %ebp, -837; AVX512VL-32-NEXT: movl %esp, %ebp38; AVX512VL-32-NEXT: .cfi_def_cfa_register %ebp39; AVX512VL-32-NEXT: andl $-8, %esp40; AVX512VL-32-NEXT: subl $64, %esp41; AVX512VL-32-NEXT: vextractf32x4 $2, %zmm0, %xmm142; AVX512VL-32-NEXT: vmovlps %xmm1, {{[0-9]+}}(%esp)43; AVX512VL-32-NEXT: vmovhps %xmm1, {{[0-9]+}}(%esp)44; AVX512VL-32-NEXT: vextractf32x4 $3, %zmm0, %xmm145; AVX512VL-32-NEXT: vmovlps %xmm1, {{[0-9]+}}(%esp)46; AVX512VL-32-NEXT: vmovhps %xmm1, (%esp)47; AVX512VL-32-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)48; AVX512VL-32-NEXT: vmovhps %xmm0, {{[0-9]+}}(%esp)49; AVX512VL-32-NEXT: vextractf128 $1, %ymm0, %xmm050; AVX512VL-32-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)51; AVX512VL-32-NEXT: vmovhps %xmm0, {{[0-9]+}}(%esp)52; AVX512VL-32-NEXT: fldl {{[0-9]+}}(%esp)53; AVX512VL-32-NEXT: fisttpll {{[0-9]+}}(%esp)54; AVX512VL-32-NEXT: fldl {{[0-9]+}}(%esp)55; AVX512VL-32-NEXT: fisttpll {{[0-9]+}}(%esp)56; AVX512VL-32-NEXT: fldl {{[0-9]+}}(%esp)57; AVX512VL-32-NEXT: fisttpll {{[0-9]+}}(%esp)58; AVX512VL-32-NEXT: fldl (%esp)59; AVX512VL-32-NEXT: fisttpll (%esp)60; AVX512VL-32-NEXT: fldl {{[0-9]+}}(%esp)61; AVX512VL-32-NEXT: fisttpll {{[0-9]+}}(%esp)62; AVX512VL-32-NEXT: fldl {{[0-9]+}}(%esp)63; AVX512VL-32-NEXT: fisttpll {{[0-9]+}}(%esp)64; AVX512VL-32-NEXT: fldl {{[0-9]+}}(%esp)65; AVX512VL-32-NEXT: fisttpll {{[0-9]+}}(%esp)66; AVX512VL-32-NEXT: fldl {{[0-9]+}}(%esp)67; AVX512VL-32-NEXT: fisttpll {{[0-9]+}}(%esp)68; AVX512VL-32-NEXT: wait69; AVX512VL-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero70; AVX512VL-32-NEXT: vpinsrd $1, {{[0-9]+}}(%esp), %xmm0, %xmm071; AVX512VL-32-NEXT: vpinsrd $2, {{[0-9]+}}(%esp), %xmm0, %xmm072; AVX512VL-32-NEXT: vpinsrd $3, {{[0-9]+}}(%esp), %xmm0, %xmm073; AVX512VL-32-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero74; AVX512VL-32-NEXT: vpinsrd $1, {{[0-9]+}}(%esp), %xmm1, %xmm175; AVX512VL-32-NEXT: vpinsrd $2, (%esp), %xmm1, %xmm176; AVX512VL-32-NEXT: vpinsrd $3, {{[0-9]+}}(%esp), %xmm1, %xmm177; AVX512VL-32-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm078; AVX512VL-32-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero79; AVX512VL-32-NEXT: vpinsrd $1, {{[0-9]+}}(%esp), %xmm1, %xmm180; AVX512VL-32-NEXT: vpinsrd $2, {{[0-9]+}}(%esp), %xmm1, %xmm181; AVX512VL-32-NEXT: vpinsrd $3, {{[0-9]+}}(%esp), %xmm1, %xmm182; AVX512VL-32-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero83; AVX512VL-32-NEXT: vpinsrd $1, {{[0-9]+}}(%esp), %xmm2, %xmm284; AVX512VL-32-NEXT: vpinsrd $2, {{[0-9]+}}(%esp), %xmm2, %xmm285; AVX512VL-32-NEXT: vpinsrd $3, {{[0-9]+}}(%esp), %xmm2, %xmm286; AVX512VL-32-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm187; AVX512VL-32-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm088; AVX512VL-32-NEXT: movl %ebp, %esp89; AVX512VL-32-NEXT: popl %ebp90; AVX512VL-32-NEXT: .cfi_def_cfa %esp, 491; AVX512VL-32-NEXT: retl92;93; AVX512VL-64-LABEL: strict_vector_fptosi_v8f64_to_v8i64:94; AVX512VL-64: # %bb.0:95; AVX512VL-64-NEXT: vextractf32x4 $3, %zmm0, %xmm196; AVX512VL-64-NEXT: vcvttsd2si %xmm1, %rax97; AVX512VL-64-NEXT: vmovq %rax, %xmm298; AVX512VL-64-NEXT: vshufpd {{.*#+}} xmm1 = xmm1[1,0]99; AVX512VL-64-NEXT: vcvttsd2si %xmm1, %rax100; AVX512VL-64-NEXT: vmovq %rax, %xmm1101; AVX512VL-64-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]102; AVX512VL-64-NEXT: vextractf32x4 $2, %zmm0, %xmm2103; AVX512VL-64-NEXT: vcvttsd2si %xmm2, %rax104; AVX512VL-64-NEXT: vmovq %rax, %xmm3105; AVX512VL-64-NEXT: vshufpd {{.*#+}} xmm2 = xmm2[1,0]106; AVX512VL-64-NEXT: vcvttsd2si %xmm2, %rax107; AVX512VL-64-NEXT: vmovq %rax, %xmm2108; AVX512VL-64-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]109; AVX512VL-64-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1110; AVX512VL-64-NEXT: vextractf128 $1, %ymm0, %xmm2111; AVX512VL-64-NEXT: vcvttsd2si %xmm2, %rax112; AVX512VL-64-NEXT: vmovq %rax, %xmm3113; AVX512VL-64-NEXT: vshufpd {{.*#+}} xmm2 = xmm2[1,0]114; AVX512VL-64-NEXT: vcvttsd2si %xmm2, %rax115; AVX512VL-64-NEXT: vmovq %rax, %xmm2116; AVX512VL-64-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]117; AVX512VL-64-NEXT: vcvttsd2si %xmm0, %rax118; AVX512VL-64-NEXT: vmovq %rax, %xmm3119; AVX512VL-64-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]120; AVX512VL-64-NEXT: vcvttsd2si %xmm0, %rax121; AVX512VL-64-NEXT: vmovq %rax, %xmm0122; AVX512VL-64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm3[0],xmm0[0]123; AVX512VL-64-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0124; AVX512VL-64-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0125; AVX512VL-64-NEXT: retq126;127; AVX512DQ-LABEL: strict_vector_fptosi_v8f64_to_v8i64:128; AVX512DQ: # %bb.0:129; AVX512DQ-NEXT: vcvttpd2qq %zmm0, %zmm0130; AVX512DQ-NEXT: ret{{[l|q]}}131 %ret = call <8 x i64> @llvm.experimental.constrained.fptosi.v8i64.v8f64(<8 x double> %a,132 metadata !"fpexcept.strict") #0133 ret <8 x i64> %ret134}135 136define <8 x i64> @strict_vector_fptoui_v8f64_to_v8i64(<8 x double> %a) #0 {137; AVX512VL-32-LABEL: strict_vector_fptoui_v8f64_to_v8i64:138; AVX512VL-32: # %bb.0:139; AVX512VL-32-NEXT: pushl %ebp140; AVX512VL-32-NEXT: .cfi_def_cfa_offset 8141; AVX512VL-32-NEXT: .cfi_offset %ebp, -8142; AVX512VL-32-NEXT: movl %esp, %ebp143; AVX512VL-32-NEXT: .cfi_def_cfa_register %ebp144; AVX512VL-32-NEXT: pushl %ebx145; AVX512VL-32-NEXT: pushl %edi146; AVX512VL-32-NEXT: pushl %esi147; AVX512VL-32-NEXT: andl $-8, %esp148; AVX512VL-32-NEXT: subl $80, %esp149; AVX512VL-32-NEXT: .cfi_offset %esi, -20150; AVX512VL-32-NEXT: .cfi_offset %edi, -16151; AVX512VL-32-NEXT: .cfi_offset %ebx, -12152; AVX512VL-32-NEXT: vextractf32x4 $3, %zmm0, %xmm2153; AVX512VL-32-NEXT: vshufpd {{.*#+}} xmm3 = xmm2[1,0]154; AVX512VL-32-NEXT: vmovsd {{.*#+}} xmm1 = [9.2233720368547758E+18,0.0E+0]155; AVX512VL-32-NEXT: xorl %eax, %eax156; AVX512VL-32-NEXT: vcomisd %xmm1, %xmm3157; AVX512VL-32-NEXT: setae %al158; AVX512VL-32-NEXT: kmovw %eax, %k1159; AVX512VL-32-NEXT: movl %eax, %esi160; AVX512VL-32-NEXT: vmovsd %xmm1, %xmm1, %xmm4 {%k1} {z}161; AVX512VL-32-NEXT: vsubsd %xmm4, %xmm3, %xmm3162; AVX512VL-32-NEXT: vmovsd %xmm3, (%esp)163; AVX512VL-32-NEXT: xorl %ebx, %ebx164; AVX512VL-32-NEXT: vcomisd %xmm1, %xmm2165; AVX512VL-32-NEXT: setae %bl166; AVX512VL-32-NEXT: kmovw %ebx, %k1167; AVX512VL-32-NEXT: vmovsd %xmm1, %xmm1, %xmm3 {%k1} {z}168; AVX512VL-32-NEXT: vsubsd %xmm3, %xmm2, %xmm2169; AVX512VL-32-NEXT: vmovsd %xmm2, {{[0-9]+}}(%esp)170; AVX512VL-32-NEXT: vextractf32x4 $2, %zmm0, %xmm2171; AVX512VL-32-NEXT: vshufpd {{.*#+}} xmm3 = xmm2[1,0]172; AVX512VL-32-NEXT: xorl %eax, %eax173; AVX512VL-32-NEXT: vcomisd %xmm1, %xmm3174; AVX512VL-32-NEXT: setae %al175; AVX512VL-32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill176; AVX512VL-32-NEXT: kmovw %eax, %k1177; AVX512VL-32-NEXT: vmovsd %xmm1, %xmm1, %xmm4 {%k1} {z}178; AVX512VL-32-NEXT: vsubsd %xmm4, %xmm3, %xmm3179; AVX512VL-32-NEXT: vmovsd %xmm3, {{[0-9]+}}(%esp)180; AVX512VL-32-NEXT: xorl %edx, %edx181; AVX512VL-32-NEXT: vcomisd %xmm1, %xmm2182; AVX512VL-32-NEXT: setae %dl183; AVX512VL-32-NEXT: kmovw %edx, %k1184; AVX512VL-32-NEXT: vmovsd %xmm1, %xmm1, %xmm3 {%k1} {z}185; AVX512VL-32-NEXT: vsubsd %xmm3, %xmm2, %xmm2186; AVX512VL-32-NEXT: vmovsd %xmm2, {{[0-9]+}}(%esp)187; AVX512VL-32-NEXT: vextractf128 $1, %ymm0, %xmm2188; AVX512VL-32-NEXT: vshufpd {{.*#+}} xmm3 = xmm2[1,0]189; AVX512VL-32-NEXT: xorl %eax, %eax190; AVX512VL-32-NEXT: vcomisd %xmm1, %xmm3191; AVX512VL-32-NEXT: setae %al192; AVX512VL-32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill193; AVX512VL-32-NEXT: kmovw %eax, %k1194; AVX512VL-32-NEXT: vmovsd %xmm1, %xmm1, %xmm4 {%k1} {z}195; AVX512VL-32-NEXT: vsubsd %xmm4, %xmm3, %xmm3196; AVX512VL-32-NEXT: vmovsd %xmm3, {{[0-9]+}}(%esp)197; AVX512VL-32-NEXT: xorl %ecx, %ecx198; AVX512VL-32-NEXT: vcomisd %xmm1, %xmm2199; AVX512VL-32-NEXT: setae %cl200; AVX512VL-32-NEXT: kmovw %ecx, %k1201; AVX512VL-32-NEXT: vmovsd %xmm1, %xmm1, %xmm3 {%k1} {z}202; AVX512VL-32-NEXT: vsubsd %xmm3, %xmm2, %xmm2203; AVX512VL-32-NEXT: vmovsd %xmm2, {{[0-9]+}}(%esp)204; AVX512VL-32-NEXT: vshufpd {{.*#+}} xmm2 = xmm0[1,0]205; AVX512VL-32-NEXT: xorl %eax, %eax206; AVX512VL-32-NEXT: vcomisd %xmm1, %xmm2207; AVX512VL-32-NEXT: setae %al208; AVX512VL-32-NEXT: kmovw %eax, %k1209; AVX512VL-32-NEXT: movl %eax, %edi210; AVX512VL-32-NEXT: vmovsd %xmm1, %xmm1, %xmm3 {%k1} {z}211; AVX512VL-32-NEXT: vsubsd %xmm3, %xmm2, %xmm2212; AVX512VL-32-NEXT: vmovsd %xmm2, {{[0-9]+}}(%esp)213; AVX512VL-32-NEXT: xorl %eax, %eax214; AVX512VL-32-NEXT: vcomisd %xmm1, %xmm0215; AVX512VL-32-NEXT: setae %al216; AVX512VL-32-NEXT: kmovw %eax, %k1217; AVX512VL-32-NEXT: vmovsd %xmm1, %xmm1, %xmm1 {%k1} {z}218; AVX512VL-32-NEXT: vsubsd %xmm1, %xmm0, %xmm0219; AVX512VL-32-NEXT: vmovsd %xmm0, {{[0-9]+}}(%esp)220; AVX512VL-32-NEXT: fldl (%esp)221; AVX512VL-32-NEXT: fisttpll (%esp)222; AVX512VL-32-NEXT: fldl {{[0-9]+}}(%esp)223; AVX512VL-32-NEXT: fisttpll {{[0-9]+}}(%esp)224; AVX512VL-32-NEXT: fldl {{[0-9]+}}(%esp)225; AVX512VL-32-NEXT: fisttpll {{[0-9]+}}(%esp)226; AVX512VL-32-NEXT: fldl {{[0-9]+}}(%esp)227; AVX512VL-32-NEXT: fisttpll {{[0-9]+}}(%esp)228; AVX512VL-32-NEXT: fldl {{[0-9]+}}(%esp)229; AVX512VL-32-NEXT: fisttpll {{[0-9]+}}(%esp)230; AVX512VL-32-NEXT: fldl {{[0-9]+}}(%esp)231; AVX512VL-32-NEXT: fisttpll {{[0-9]+}}(%esp)232; AVX512VL-32-NEXT: fldl {{[0-9]+}}(%esp)233; AVX512VL-32-NEXT: fisttpll {{[0-9]+}}(%esp)234; AVX512VL-32-NEXT: fldl {{[0-9]+}}(%esp)235; AVX512VL-32-NEXT: fisttpll {{[0-9]+}}(%esp)236; AVX512VL-32-NEXT: wait237; AVX512VL-32-NEXT: shll $31, %ebx238; AVX512VL-32-NEXT: xorl {{[0-9]+}}(%esp), %ebx239; AVX512VL-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero240; AVX512VL-32-NEXT: vpinsrd $1, %ebx, %xmm0, %xmm0241; AVX512VL-32-NEXT: shll $31, %esi242; AVX512VL-32-NEXT: xorl {{[0-9]+}}(%esp), %esi243; AVX512VL-32-NEXT: vpinsrd $2, (%esp), %xmm0, %xmm0244; AVX512VL-32-NEXT: vpinsrd $3, %esi, %xmm0, %xmm0245; AVX512VL-32-NEXT: shll $31, %edx246; AVX512VL-32-NEXT: xorl {{[0-9]+}}(%esp), %edx247; AVX512VL-32-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero248; AVX512VL-32-NEXT: vpinsrd $1, %edx, %xmm1, %xmm1249; AVX512VL-32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload250; AVX512VL-32-NEXT: shll $31, %edx251; AVX512VL-32-NEXT: xorl {{[0-9]+}}(%esp), %edx252; AVX512VL-32-NEXT: vpinsrd $2, {{[0-9]+}}(%esp), %xmm1, %xmm1253; AVX512VL-32-NEXT: vpinsrd $3, %edx, %xmm1, %xmm1254; AVX512VL-32-NEXT: shll $31, %ecx255; AVX512VL-32-NEXT: xorl {{[0-9]+}}(%esp), %ecx256; AVX512VL-32-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero257; AVX512VL-32-NEXT: vpinsrd $1, %ecx, %xmm2, %xmm2258; AVX512VL-32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload259; AVX512VL-32-NEXT: shll $31, %ecx260; AVX512VL-32-NEXT: xorl {{[0-9]+}}(%esp), %ecx261; AVX512VL-32-NEXT: vpinsrd $2, {{[0-9]+}}(%esp), %xmm2, %xmm2262; AVX512VL-32-NEXT: vpinsrd $3, %ecx, %xmm2, %xmm2263; AVX512VL-32-NEXT: shll $31, %eax264; AVX512VL-32-NEXT: xorl {{[0-9]+}}(%esp), %eax265; AVX512VL-32-NEXT: vmovd {{.*#+}} xmm3 = mem[0],zero,zero,zero266; AVX512VL-32-NEXT: vpinsrd $1, %eax, %xmm3, %xmm3267; AVX512VL-32-NEXT: shll $31, %edi268; AVX512VL-32-NEXT: xorl {{[0-9]+}}(%esp), %edi269; AVX512VL-32-NEXT: vpinsrd $2, {{[0-9]+}}(%esp), %xmm3, %xmm3270; AVX512VL-32-NEXT: vpinsrd $3, %edi, %xmm3, %xmm3271; AVX512VL-32-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0272; AVX512VL-32-NEXT: vinserti128 $1, %xmm2, %ymm3, %ymm1273; AVX512VL-32-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0274; AVX512VL-32-NEXT: leal -12(%ebp), %esp275; AVX512VL-32-NEXT: popl %esi276; AVX512VL-32-NEXT: popl %edi277; AVX512VL-32-NEXT: popl %ebx278; AVX512VL-32-NEXT: popl %ebp279; AVX512VL-32-NEXT: .cfi_def_cfa %esp, 4280; AVX512VL-32-NEXT: retl281;282; AVX512VL-64-LABEL: strict_vector_fptoui_v8f64_to_v8i64:283; AVX512VL-64: # %bb.0:284; AVX512VL-64-NEXT: vextractf32x4 $3, %zmm0, %xmm1285; AVX512VL-64-NEXT: vcvttsd2usi %xmm1, %rax286; AVX512VL-64-NEXT: vmovq %rax, %xmm2287; AVX512VL-64-NEXT: vshufpd {{.*#+}} xmm1 = xmm1[1,0]288; AVX512VL-64-NEXT: vcvttsd2usi %xmm1, %rax289; AVX512VL-64-NEXT: vmovq %rax, %xmm1290; AVX512VL-64-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]291; AVX512VL-64-NEXT: vextractf32x4 $2, %zmm0, %xmm2292; AVX512VL-64-NEXT: vcvttsd2usi %xmm2, %rax293; AVX512VL-64-NEXT: vmovq %rax, %xmm3294; AVX512VL-64-NEXT: vshufpd {{.*#+}} xmm2 = xmm2[1,0]295; AVX512VL-64-NEXT: vcvttsd2usi %xmm2, %rax296; AVX512VL-64-NEXT: vmovq %rax, %xmm2297; AVX512VL-64-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]298; AVX512VL-64-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1299; AVX512VL-64-NEXT: vextractf128 $1, %ymm0, %xmm2300; AVX512VL-64-NEXT: vcvttsd2usi %xmm2, %rax301; AVX512VL-64-NEXT: vmovq %rax, %xmm3302; AVX512VL-64-NEXT: vshufpd {{.*#+}} xmm2 = xmm2[1,0]303; AVX512VL-64-NEXT: vcvttsd2usi %xmm2, %rax304; AVX512VL-64-NEXT: vmovq %rax, %xmm2305; AVX512VL-64-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]306; AVX512VL-64-NEXT: vcvttsd2usi %xmm0, %rax307; AVX512VL-64-NEXT: vmovq %rax, %xmm3308; AVX512VL-64-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]309; AVX512VL-64-NEXT: vcvttsd2usi %xmm0, %rax310; AVX512VL-64-NEXT: vmovq %rax, %xmm0311; AVX512VL-64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm3[0],xmm0[0]312; AVX512VL-64-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0313; AVX512VL-64-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0314; AVX512VL-64-NEXT: retq315;316; AVX512DQ-LABEL: strict_vector_fptoui_v8f64_to_v8i64:317; AVX512DQ: # %bb.0:318; AVX512DQ-NEXT: vcvttpd2uqq %zmm0, %zmm0319; AVX512DQ-NEXT: ret{{[l|q]}}320 %ret = call <8 x i64> @llvm.experimental.constrained.fptoui.v8i64.v8f64(<8 x double> %a,321 metadata !"fpexcept.strict") #0322 ret <8 x i64> %ret323}324 325define <8 x i64> @strict_vector_fptosi_v8f32_to_v8i64(<8 x float> %a) #0 {326; AVX512VL-32-LABEL: strict_vector_fptosi_v8f32_to_v8i64:327; AVX512VL-32: # %bb.0:328; AVX512VL-32-NEXT: pushl %ebp329; AVX512VL-32-NEXT: .cfi_def_cfa_offset 8330; AVX512VL-32-NEXT: .cfi_offset %ebp, -8331; AVX512VL-32-NEXT: movl %esp, %ebp332; AVX512VL-32-NEXT: .cfi_def_cfa_register %ebp333; AVX512VL-32-NEXT: andl $-8, %esp334; AVX512VL-32-NEXT: subl $64, %esp335; AVX512VL-32-NEXT: vextracti128 $1, %ymm0, %xmm1336; AVX512VL-32-NEXT: vmovd %xmm1, {{[0-9]+}}(%esp)337; AVX512VL-32-NEXT: vextractps $1, %xmm1, {{[0-9]+}}(%esp)338; AVX512VL-32-NEXT: vextractps $2, %xmm1, {{[0-9]+}}(%esp)339; AVX512VL-32-NEXT: vextractps $3, %xmm1, (%esp)340; AVX512VL-32-NEXT: vmovd %xmm0, {{[0-9]+}}(%esp)341; AVX512VL-32-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp)342; AVX512VL-32-NEXT: vextractps $2, %xmm0, {{[0-9]+}}(%esp)343; AVX512VL-32-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp)344; AVX512VL-32-NEXT: flds {{[0-9]+}}(%esp)345; AVX512VL-32-NEXT: fisttpll {{[0-9]+}}(%esp)346; AVX512VL-32-NEXT: flds {{[0-9]+}}(%esp)347; AVX512VL-32-NEXT: fisttpll {{[0-9]+}}(%esp)348; AVX512VL-32-NEXT: flds {{[0-9]+}}(%esp)349; AVX512VL-32-NEXT: fisttpll {{[0-9]+}}(%esp)350; AVX512VL-32-NEXT: flds (%esp)351; AVX512VL-32-NEXT: fisttpll (%esp)352; AVX512VL-32-NEXT: flds {{[0-9]+}}(%esp)353; AVX512VL-32-NEXT: fisttpll {{[0-9]+}}(%esp)354; AVX512VL-32-NEXT: flds {{[0-9]+}}(%esp)355; AVX512VL-32-NEXT: fisttpll {{[0-9]+}}(%esp)356; AVX512VL-32-NEXT: flds {{[0-9]+}}(%esp)357; AVX512VL-32-NEXT: fisttpll {{[0-9]+}}(%esp)358; AVX512VL-32-NEXT: flds {{[0-9]+}}(%esp)359; AVX512VL-32-NEXT: fisttpll {{[0-9]+}}(%esp)360; AVX512VL-32-NEXT: wait361; AVX512VL-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero362; AVX512VL-32-NEXT: vpinsrd $1, {{[0-9]+}}(%esp), %xmm0, %xmm0363; AVX512VL-32-NEXT: vpinsrd $2, {{[0-9]+}}(%esp), %xmm0, %xmm0364; AVX512VL-32-NEXT: vpinsrd $3, {{[0-9]+}}(%esp), %xmm0, %xmm0365; AVX512VL-32-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero366; AVX512VL-32-NEXT: vpinsrd $1, {{[0-9]+}}(%esp), %xmm1, %xmm1367; AVX512VL-32-NEXT: vpinsrd $2, (%esp), %xmm1, %xmm1368; AVX512VL-32-NEXT: vpinsrd $3, {{[0-9]+}}(%esp), %xmm1, %xmm1369; AVX512VL-32-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0370; AVX512VL-32-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero371; AVX512VL-32-NEXT: vpinsrd $1, {{[0-9]+}}(%esp), %xmm1, %xmm1372; AVX512VL-32-NEXT: vpinsrd $2, {{[0-9]+}}(%esp), %xmm1, %xmm1373; AVX512VL-32-NEXT: vpinsrd $3, {{[0-9]+}}(%esp), %xmm1, %xmm1374; AVX512VL-32-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero375; AVX512VL-32-NEXT: vpinsrd $1, {{[0-9]+}}(%esp), %xmm2, %xmm2376; AVX512VL-32-NEXT: vpinsrd $2, {{[0-9]+}}(%esp), %xmm2, %xmm2377; AVX512VL-32-NEXT: vpinsrd $3, {{[0-9]+}}(%esp), %xmm2, %xmm2378; AVX512VL-32-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1379; AVX512VL-32-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0380; AVX512VL-32-NEXT: movl %ebp, %esp381; AVX512VL-32-NEXT: popl %ebp382; AVX512VL-32-NEXT: .cfi_def_cfa %esp, 4383; AVX512VL-32-NEXT: retl384;385; AVX512VL-64-LABEL: strict_vector_fptosi_v8f32_to_v8i64:386; AVX512VL-64: # %bb.0:387; AVX512VL-64-NEXT: vextractf128 $1, %ymm0, %xmm1388; AVX512VL-64-NEXT: vshufps {{.*#+}} xmm2 = xmm1[3,3,3,3]389; AVX512VL-64-NEXT: vcvttss2si %xmm2, %rax390; AVX512VL-64-NEXT: vmovq %rax, %xmm2391; AVX512VL-64-NEXT: vshufpd {{.*#+}} xmm3 = xmm1[1,0]392; AVX512VL-64-NEXT: vcvttss2si %xmm3, %rax393; AVX512VL-64-NEXT: vmovq %rax, %xmm3394; AVX512VL-64-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]395; AVX512VL-64-NEXT: vcvttss2si %xmm1, %rax396; AVX512VL-64-NEXT: vmovq %rax, %xmm3397; AVX512VL-64-NEXT: vmovshdup {{.*#+}} xmm1 = xmm1[1,1,3,3]398; AVX512VL-64-NEXT: vcvttss2si %xmm1, %rax399; AVX512VL-64-NEXT: vmovq %rax, %xmm1400; AVX512VL-64-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm3[0],xmm1[0]401; AVX512VL-64-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1402; AVX512VL-64-NEXT: vshufps {{.*#+}} xmm2 = xmm0[3,3,3,3]403; AVX512VL-64-NEXT: vcvttss2si %xmm2, %rax404; AVX512VL-64-NEXT: vmovq %rax, %xmm2405; AVX512VL-64-NEXT: vshufpd {{.*#+}} xmm3 = xmm0[1,0]406; AVX512VL-64-NEXT: vcvttss2si %xmm3, %rax407; AVX512VL-64-NEXT: vmovq %rax, %xmm3408; AVX512VL-64-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]409; AVX512VL-64-NEXT: vcvttss2si %xmm0, %rax410; AVX512VL-64-NEXT: vmovq %rax, %xmm3411; AVX512VL-64-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]412; AVX512VL-64-NEXT: vcvttss2si %xmm0, %rax413; AVX512VL-64-NEXT: vmovq %rax, %xmm0414; AVX512VL-64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm3[0],xmm0[0]415; AVX512VL-64-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0416; AVX512VL-64-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0417; AVX512VL-64-NEXT: retq418;419; AVX512DQ-LABEL: strict_vector_fptosi_v8f32_to_v8i64:420; AVX512DQ: # %bb.0:421; AVX512DQ-NEXT: vcvttps2qq %ymm0, %zmm0422; AVX512DQ-NEXT: ret{{[l|q]}}423 %ret = call <8 x i64> @llvm.experimental.constrained.fptosi.v8i64.v8f32(<8 x float> %a,424 metadata !"fpexcept.strict") #0425 ret <8 x i64> %ret426}427 428define <8 x i64> @strict_vector_fptoui_v8f32_to_v8i64(<8 x float> %a) #0 {429; AVX512VL-32-LABEL: strict_vector_fptoui_v8f32_to_v8i64:430; AVX512VL-32: # %bb.0:431; AVX512VL-32-NEXT: pushl %ebp432; AVX512VL-32-NEXT: .cfi_def_cfa_offset 8433; AVX512VL-32-NEXT: .cfi_offset %ebp, -8434; AVX512VL-32-NEXT: movl %esp, %ebp435; AVX512VL-32-NEXT: .cfi_def_cfa_register %ebp436; AVX512VL-32-NEXT: pushl %ebx437; AVX512VL-32-NEXT: pushl %edi438; AVX512VL-32-NEXT: pushl %esi439; AVX512VL-32-NEXT: andl $-8, %esp440; AVX512VL-32-NEXT: subl $80, %esp441; AVX512VL-32-NEXT: .cfi_offset %esi, -20442; AVX512VL-32-NEXT: .cfi_offset %edi, -16443; AVX512VL-32-NEXT: .cfi_offset %ebx, -12444; AVX512VL-32-NEXT: vextractf128 $1, %ymm0, %xmm2445; AVX512VL-32-NEXT: vshufps {{.*#+}} xmm3 = xmm2[3,3,3,3]446; AVX512VL-32-NEXT: vmovss {{.*#+}} xmm1 = [9.22337203E+18,0.0E+0,0.0E+0,0.0E+0]447; AVX512VL-32-NEXT: xorl %eax, %eax448; AVX512VL-32-NEXT: vcomiss %xmm1, %xmm3449; AVX512VL-32-NEXT: setae %al450; AVX512VL-32-NEXT: kmovw %eax, %k1451; AVX512VL-32-NEXT: movl %eax, %esi452; AVX512VL-32-NEXT: vmovss %xmm1, %xmm1, %xmm4 {%k1} {z}453; AVX512VL-32-NEXT: vsubss %xmm4, %xmm3, %xmm3454; AVX512VL-32-NEXT: vmovss %xmm3, (%esp)455; AVX512VL-32-NEXT: vshufpd {{.*#+}} xmm3 = xmm2[1,0]456; AVX512VL-32-NEXT: xorl %ebx, %ebx457; AVX512VL-32-NEXT: vcomiss %xmm1, %xmm3458; AVX512VL-32-NEXT: setae %bl459; AVX512VL-32-NEXT: kmovw %ebx, %k1460; AVX512VL-32-NEXT: vmovss %xmm1, %xmm1, %xmm4 {%k1} {z}461; AVX512VL-32-NEXT: vsubss %xmm4, %xmm3, %xmm3462; AVX512VL-32-NEXT: vmovss %xmm3, {{[0-9]+}}(%esp)463; AVX512VL-32-NEXT: vmovshdup {{.*#+}} xmm3 = xmm2[1,1,3,3]464; AVX512VL-32-NEXT: xorl %eax, %eax465; AVX512VL-32-NEXT: vcomiss %xmm1, %xmm3466; AVX512VL-32-NEXT: setae %al467; AVX512VL-32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill468; AVX512VL-32-NEXT: kmovw %eax, %k1469; AVX512VL-32-NEXT: vmovss %xmm1, %xmm1, %xmm4 {%k1} {z}470; AVX512VL-32-NEXT: vsubss %xmm4, %xmm3, %xmm3471; AVX512VL-32-NEXT: vmovss %xmm3, {{[0-9]+}}(%esp)472; AVX512VL-32-NEXT: xorl %edx, %edx473; AVX512VL-32-NEXT: vcomiss %xmm1, %xmm2474; AVX512VL-32-NEXT: setae %dl475; AVX512VL-32-NEXT: kmovw %edx, %k1476; AVX512VL-32-NEXT: vmovss %xmm1, %xmm1, %xmm3 {%k1} {z}477; AVX512VL-32-NEXT: vsubss %xmm3, %xmm2, %xmm2478; AVX512VL-32-NEXT: vmovss %xmm2, {{[0-9]+}}(%esp)479; AVX512VL-32-NEXT: vshufps {{.*#+}} xmm2 = xmm0[3,3,3,3]480; AVX512VL-32-NEXT: xorl %eax, %eax481; AVX512VL-32-NEXT: vcomiss %xmm1, %xmm2482; AVX512VL-32-NEXT: setae %al483; AVX512VL-32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill484; AVX512VL-32-NEXT: kmovw %eax, %k1485; AVX512VL-32-NEXT: vmovss %xmm1, %xmm1, %xmm3 {%k1} {z}486; AVX512VL-32-NEXT: vsubss %xmm3, %xmm2, %xmm2487; AVX512VL-32-NEXT: vmovss %xmm2, {{[0-9]+}}(%esp)488; AVX512VL-32-NEXT: vshufpd {{.*#+}} xmm2 = xmm0[1,0]489; AVX512VL-32-NEXT: xorl %ecx, %ecx490; AVX512VL-32-NEXT: vcomiss %xmm1, %xmm2491; AVX512VL-32-NEXT: setae %cl492; AVX512VL-32-NEXT: kmovw %ecx, %k1493; AVX512VL-32-NEXT: vmovss %xmm1, %xmm1, %xmm3 {%k1} {z}494; AVX512VL-32-NEXT: vsubss %xmm3, %xmm2, %xmm2495; AVX512VL-32-NEXT: vmovss %xmm2, {{[0-9]+}}(%esp)496; AVX512VL-32-NEXT: vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]497; AVX512VL-32-NEXT: xorl %eax, %eax498; AVX512VL-32-NEXT: vcomiss %xmm1, %xmm2499; AVX512VL-32-NEXT: setae %al500; AVX512VL-32-NEXT: kmovw %eax, %k1501; AVX512VL-32-NEXT: movl %eax, %edi502; AVX512VL-32-NEXT: vmovss %xmm1, %xmm1, %xmm3 {%k1} {z}503; AVX512VL-32-NEXT: vsubss %xmm3, %xmm2, %xmm2504; AVX512VL-32-NEXT: vmovss %xmm2, {{[0-9]+}}(%esp)505; AVX512VL-32-NEXT: xorl %eax, %eax506; AVX512VL-32-NEXT: vcomiss %xmm1, %xmm0507; AVX512VL-32-NEXT: setae %al508; AVX512VL-32-NEXT: kmovw %eax, %k1509; AVX512VL-32-NEXT: vmovss %xmm1, %xmm1, %xmm1 {%k1} {z}510; AVX512VL-32-NEXT: vsubss %xmm1, %xmm0, %xmm0511; AVX512VL-32-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp)512; AVX512VL-32-NEXT: flds (%esp)513; AVX512VL-32-NEXT: fisttpll (%esp)514; AVX512VL-32-NEXT: flds {{[0-9]+}}(%esp)515; AVX512VL-32-NEXT: fisttpll {{[0-9]+}}(%esp)516; AVX512VL-32-NEXT: flds {{[0-9]+}}(%esp)517; AVX512VL-32-NEXT: fisttpll {{[0-9]+}}(%esp)518; AVX512VL-32-NEXT: flds {{[0-9]+}}(%esp)519; AVX512VL-32-NEXT: fisttpll {{[0-9]+}}(%esp)520; AVX512VL-32-NEXT: flds {{[0-9]+}}(%esp)521; AVX512VL-32-NEXT: fisttpll {{[0-9]+}}(%esp)522; AVX512VL-32-NEXT: flds {{[0-9]+}}(%esp)523; AVX512VL-32-NEXT: fisttpll {{[0-9]+}}(%esp)524; AVX512VL-32-NEXT: flds {{[0-9]+}}(%esp)525; AVX512VL-32-NEXT: fisttpll {{[0-9]+}}(%esp)526; AVX512VL-32-NEXT: flds {{[0-9]+}}(%esp)527; AVX512VL-32-NEXT: fisttpll {{[0-9]+}}(%esp)528; AVX512VL-32-NEXT: wait529; AVX512VL-32-NEXT: shll $31, %ebx530; AVX512VL-32-NEXT: xorl {{[0-9]+}}(%esp), %ebx531; AVX512VL-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero532; AVX512VL-32-NEXT: vpinsrd $1, %ebx, %xmm0, %xmm0533; AVX512VL-32-NEXT: shll $31, %esi534; AVX512VL-32-NEXT: xorl {{[0-9]+}}(%esp), %esi535; AVX512VL-32-NEXT: vpinsrd $2, (%esp), %xmm0, %xmm0536; AVX512VL-32-NEXT: vpinsrd $3, %esi, %xmm0, %xmm0537; AVX512VL-32-NEXT: shll $31, %edx538; AVX512VL-32-NEXT: xorl {{[0-9]+}}(%esp), %edx539; AVX512VL-32-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero540; AVX512VL-32-NEXT: vpinsrd $1, %edx, %xmm1, %xmm1541; AVX512VL-32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload542; AVX512VL-32-NEXT: shll $31, %edx543; AVX512VL-32-NEXT: xorl {{[0-9]+}}(%esp), %edx544; AVX512VL-32-NEXT: vpinsrd $2, {{[0-9]+}}(%esp), %xmm1, %xmm1545; AVX512VL-32-NEXT: vpinsrd $3, %edx, %xmm1, %xmm1546; AVX512VL-32-NEXT: shll $31, %ecx547; AVX512VL-32-NEXT: xorl {{[0-9]+}}(%esp), %ecx548; AVX512VL-32-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero549; AVX512VL-32-NEXT: vpinsrd $1, %ecx, %xmm2, %xmm2550; AVX512VL-32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload551; AVX512VL-32-NEXT: shll $31, %ecx552; AVX512VL-32-NEXT: xorl {{[0-9]+}}(%esp), %ecx553; AVX512VL-32-NEXT: vpinsrd $2, {{[0-9]+}}(%esp), %xmm2, %xmm2554; AVX512VL-32-NEXT: vpinsrd $3, %ecx, %xmm2, %xmm2555; AVX512VL-32-NEXT: shll $31, %eax556; AVX512VL-32-NEXT: xorl {{[0-9]+}}(%esp), %eax557; AVX512VL-32-NEXT: vmovd {{.*#+}} xmm3 = mem[0],zero,zero,zero558; AVX512VL-32-NEXT: vpinsrd $1, %eax, %xmm3, %xmm3559; AVX512VL-32-NEXT: shll $31, %edi560; AVX512VL-32-NEXT: xorl {{[0-9]+}}(%esp), %edi561; AVX512VL-32-NEXT: vpinsrd $2, {{[0-9]+}}(%esp), %xmm3, %xmm3562; AVX512VL-32-NEXT: vpinsrd $3, %edi, %xmm3, %xmm3563; AVX512VL-32-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0564; AVX512VL-32-NEXT: vinserti128 $1, %xmm2, %ymm3, %ymm1565; AVX512VL-32-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0566; AVX512VL-32-NEXT: leal -12(%ebp), %esp567; AVX512VL-32-NEXT: popl %esi568; AVX512VL-32-NEXT: popl %edi569; AVX512VL-32-NEXT: popl %ebx570; AVX512VL-32-NEXT: popl %ebp571; AVX512VL-32-NEXT: .cfi_def_cfa %esp, 4572; AVX512VL-32-NEXT: retl573;574; AVX512VL-64-LABEL: strict_vector_fptoui_v8f32_to_v8i64:575; AVX512VL-64: # %bb.0:576; AVX512VL-64-NEXT: vextractf128 $1, %ymm0, %xmm1577; AVX512VL-64-NEXT: vshufps {{.*#+}} xmm2 = xmm1[3,3,3,3]578; AVX512VL-64-NEXT: vcvttss2usi %xmm2, %rax579; AVX512VL-64-NEXT: vmovq %rax, %xmm2580; AVX512VL-64-NEXT: vshufpd {{.*#+}} xmm3 = xmm1[1,0]581; AVX512VL-64-NEXT: vcvttss2usi %xmm3, %rax582; AVX512VL-64-NEXT: vmovq %rax, %xmm3583; AVX512VL-64-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]584; AVX512VL-64-NEXT: vcvttss2usi %xmm1, %rax585; AVX512VL-64-NEXT: vmovq %rax, %xmm3586; AVX512VL-64-NEXT: vmovshdup {{.*#+}} xmm1 = xmm1[1,1,3,3]587; AVX512VL-64-NEXT: vcvttss2usi %xmm1, %rax588; AVX512VL-64-NEXT: vmovq %rax, %xmm1589; AVX512VL-64-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm3[0],xmm1[0]590; AVX512VL-64-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1591; AVX512VL-64-NEXT: vshufps {{.*#+}} xmm2 = xmm0[3,3,3,3]592; AVX512VL-64-NEXT: vcvttss2usi %xmm2, %rax593; AVX512VL-64-NEXT: vmovq %rax, %xmm2594; AVX512VL-64-NEXT: vshufpd {{.*#+}} xmm3 = xmm0[1,0]595; AVX512VL-64-NEXT: vcvttss2usi %xmm3, %rax596; AVX512VL-64-NEXT: vmovq %rax, %xmm3597; AVX512VL-64-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]598; AVX512VL-64-NEXT: vcvttss2usi %xmm0, %rax599; AVX512VL-64-NEXT: vmovq %rax, %xmm3600; AVX512VL-64-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]601; AVX512VL-64-NEXT: vcvttss2usi %xmm0, %rax602; AVX512VL-64-NEXT: vmovq %rax, %xmm0603; AVX512VL-64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm3[0],xmm0[0]604; AVX512VL-64-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0605; AVX512VL-64-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0606; AVX512VL-64-NEXT: retq607;608; AVX512DQ-LABEL: strict_vector_fptoui_v8f32_to_v8i64:609; AVX512DQ: # %bb.0:610; AVX512DQ-NEXT: vcvttps2uqq %ymm0, %zmm0611; AVX512DQ-NEXT: ret{{[l|q]}}612 %ret = call <8 x i64> @llvm.experimental.constrained.fptoui.v8i64.v8f32(<8 x float> %a,613 metadata !"fpexcept.strict") #0614 ret <8 x i64> %ret615}616 617define <8 x i32> @strict_vector_fptosi_v8f64_to_v8i32(<8 x double> %a) #0 {618; CHECK-LABEL: strict_vector_fptosi_v8f64_to_v8i32:619; CHECK: # %bb.0:620; CHECK-NEXT: vcvttpd2dq %zmm0, %ymm0621; CHECK-NEXT: ret{{[l|q]}}622 %ret = call <8 x i32> @llvm.experimental.constrained.fptosi.v8i32.v8f64(<8 x double> %a,623 metadata !"fpexcept.strict") #0624 ret <8 x i32> %ret625}626 627define <8 x i32> @strict_vector_fptoui_v8f64_to_v8i32(<8 x double> %a) #0 {628; CHECK-LABEL: strict_vector_fptoui_v8f64_to_v8i32:629; CHECK: # %bb.0:630; CHECK-NEXT: vcvttpd2udq %zmm0, %ymm0631; CHECK-NEXT: ret{{[l|q]}}632 %ret = call <8 x i32> @llvm.experimental.constrained.fptoui.v8i32.v8f64(<8 x double> %a,633 metadata !"fpexcept.strict") #0634 ret <8 x i32> %ret635}636 637define <8 x i16> @strict_vector_fptosi_v8f64_to_v8i16(<8 x double> %a) #0 {638; AVX512VL-LABEL: strict_vector_fptosi_v8f64_to_v8i16:639; AVX512VL: # %bb.0:640; AVX512VL-NEXT: vcvttpd2dq %zmm0, %ymm0641; AVX512VL-NEXT: vpmovdw %ymm0, %xmm0642; AVX512VL-NEXT: vzeroupper643; AVX512VL-NEXT: ret{{[l|q]}}644;645; AVX512DQ-LABEL: strict_vector_fptosi_v8f64_to_v8i16:646; AVX512DQ: # %bb.0:647; AVX512DQ-NEXT: vcvttpd2dq %zmm0, %ymm0648; AVX512DQ-NEXT: vpmovdw %zmm0, %ymm0649; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0650; AVX512DQ-NEXT: vzeroupper651; AVX512DQ-NEXT: ret{{[l|q]}}652 %ret = call <8 x i16> @llvm.experimental.constrained.fptosi.v8i16.v8f64(<8 x double> %a,653 metadata !"fpexcept.strict") #0654 ret <8 x i16> %ret655}656 657define <8 x i16> @strict_vector_fptoui_v8f64_to_v8i16(<8 x double> %a) #0 {658; AVX512VL-LABEL: strict_vector_fptoui_v8f64_to_v8i16:659; AVX512VL: # %bb.0:660; AVX512VL-NEXT: vcvttpd2dq %zmm0, %ymm0661; AVX512VL-NEXT: vpmovdw %ymm0, %xmm0662; AVX512VL-NEXT: vzeroupper663; AVX512VL-NEXT: ret{{[l|q]}}664;665; AVX512DQ-LABEL: strict_vector_fptoui_v8f64_to_v8i16:666; AVX512DQ: # %bb.0:667; AVX512DQ-NEXT: vcvttpd2dq %zmm0, %ymm0668; AVX512DQ-NEXT: vpmovdw %zmm0, %ymm0669; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0670; AVX512DQ-NEXT: vzeroupper671; AVX512DQ-NEXT: ret{{[l|q]}}672 %ret = call <8 x i16> @llvm.experimental.constrained.fptoui.v8i16.v8f64(<8 x double> %a,673 metadata !"fpexcept.strict") #0674 ret <8 x i16> %ret675}676 677define <8 x i8> @strict_vector_fptosi_v8f64_to_v8i8(<8 x double> %a) #0 {678; AVX512VL-LABEL: strict_vector_fptosi_v8f64_to_v8i8:679; AVX512VL: # %bb.0:680; AVX512VL-NEXT: vcvttpd2dq %zmm0, %ymm0681; AVX512VL-NEXT: vpmovdb %ymm0, %xmm0682; AVX512VL-NEXT: vzeroupper683; AVX512VL-NEXT: ret{{[l|q]}}684;685; AVX512DQ-LABEL: strict_vector_fptosi_v8f64_to_v8i8:686; AVX512DQ: # %bb.0:687; AVX512DQ-NEXT: vcvttpd2dq %zmm0, %ymm0688; AVX512DQ-NEXT: vpmovdb %zmm0, %xmm0689; AVX512DQ-NEXT: vzeroupper690; AVX512DQ-NEXT: ret{{[l|q]}}691 %ret = call <8 x i8> @llvm.experimental.constrained.fptosi.v8i8.v8f64(<8 x double> %a,692 metadata !"fpexcept.strict") #0693 ret <8 x i8> %ret694}695 696define <8 x i8> @strict_vector_fptoui_v8f64_to_v8i8(<8 x double> %a) #0 {697; AVX512VL-LABEL: strict_vector_fptoui_v8f64_to_v8i8:698; AVX512VL: # %bb.0:699; AVX512VL-NEXT: vcvttpd2dq %zmm0, %ymm0700; AVX512VL-NEXT: vpmovdb %ymm0, %xmm0701; AVX512VL-NEXT: vzeroupper702; AVX512VL-NEXT: ret{{[l|q]}}703;704; AVX512DQ-LABEL: strict_vector_fptoui_v8f64_to_v8i8:705; AVX512DQ: # %bb.0:706; AVX512DQ-NEXT: vcvttpd2dq %zmm0, %ymm0707; AVX512DQ-NEXT: vpmovdb %zmm0, %xmm0708; AVX512DQ-NEXT: vzeroupper709; AVX512DQ-NEXT: ret{{[l|q]}}710 %ret = call <8 x i8> @llvm.experimental.constrained.fptoui.v8i8.v8f64(<8 x double> %a,711 metadata !"fpexcept.strict") #0712 ret <8 x i8> %ret713}714 715define <8 x i1> @strict_vector_fptosi_v8f64_to_v8i1(<8 x double> %a) #0 {716; AVX512VL-LABEL: strict_vector_fptosi_v8f64_to_v8i1:717; AVX512VL: # %bb.0:718; AVX512VL-NEXT: vcvttpd2dq %zmm0, %ymm0719; AVX512VL-NEXT: vptestmd %ymm0, %ymm0, %k1720; AVX512VL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0721; AVX512VL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}722; AVX512VL-NEXT: vpmovdw %ymm0, %xmm0723; AVX512VL-NEXT: vzeroupper724; AVX512VL-NEXT: ret{{[l|q]}}725;726; AVX512DQ-LABEL: strict_vector_fptosi_v8f64_to_v8i1:727; AVX512DQ: # %bb.0:728; AVX512DQ-NEXT: vcvttpd2dq %zmm0, %ymm0729; AVX512DQ-NEXT: vpmovd2m %zmm0, %k0730; AVX512DQ-NEXT: vpmovm2d %k0, %zmm0731; AVX512DQ-NEXT: vpmovdw %zmm0, %ymm0732; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0733; AVX512DQ-NEXT: vzeroupper734; AVX512DQ-NEXT: ret{{[l|q]}}735 %ret = call <8 x i1> @llvm.experimental.constrained.fptosi.v8i1.v8f64(<8 x double> %a,736 metadata !"fpexcept.strict") #0737 ret <8 x i1> %ret738}739 740define <8 x i1> @strict_vector_fptoui_v8f64_to_v8i1(<8 x double> %a) #0 {741; AVX512VL-LABEL: strict_vector_fptoui_v8f64_to_v8i1:742; AVX512VL: # %bb.0:743; AVX512VL-NEXT: vcvttpd2dq %zmm0, %ymm0744; AVX512VL-NEXT: vpslld $31, %ymm0, %ymm0745; AVX512VL-NEXT: vptestmd %ymm0, %ymm0, %k1746; AVX512VL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0747; AVX512VL-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}748; AVX512VL-NEXT: vpmovdw %ymm0, %xmm0749; AVX512VL-NEXT: vzeroupper750; AVX512VL-NEXT: ret{{[l|q]}}751;752; AVX512DQ-LABEL: strict_vector_fptoui_v8f64_to_v8i1:753; AVX512DQ: # %bb.0:754; AVX512DQ-NEXT: vcvttpd2dq %zmm0, %ymm0755; AVX512DQ-NEXT: vpslld $31, %ymm0, %ymm0756; AVX512DQ-NEXT: vpmovd2m %zmm0, %k0757; AVX512DQ-NEXT: vpmovm2d %k0, %zmm0758; AVX512DQ-NEXT: vpmovdw %zmm0, %ymm0759; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0760; AVX512DQ-NEXT: vzeroupper761; AVX512DQ-NEXT: ret{{[l|q]}}762 %ret = call <8 x i1> @llvm.experimental.constrained.fptoui.v8i1.v8f64(<8 x double> %a,763 metadata !"fpexcept.strict") #0764 ret <8 x i1> %ret765}766 767define <16 x i32> @strict_vector_fptosi_v16f32_to_v16i32(<16 x float> %a) #0 {768; CHECK-LABEL: strict_vector_fptosi_v16f32_to_v16i32:769; CHECK: # %bb.0:770; CHECK-NEXT: vcvttps2dq %zmm0, %zmm0771; CHECK-NEXT: ret{{[l|q]}}772 %ret = call <16 x i32> @llvm.experimental.constrained.fptosi.v16i32.v16f32(<16 x float> %a,773 metadata !"fpexcept.strict") #0774 ret <16 x i32> %ret775}776 777define <16 x i32> @strict_vector_fptoui_v16f32_to_v16i32(<16 x float> %a) #0 {778; CHECK-LABEL: strict_vector_fptoui_v16f32_to_v16i32:779; CHECK: # %bb.0:780; CHECK-NEXT: vcvttps2udq %zmm0, %zmm0781; CHECK-NEXT: ret{{[l|q]}}782 %ret = call <16 x i32> @llvm.experimental.constrained.fptoui.v16i32.v16f32(<16 x float> %a,783 metadata !"fpexcept.strict") #0784 ret <16 x i32> %ret785}786 787define <16 x i16> @strict_vector_fptosi_v16f32_to_v16i16(<16 x float> %a) #0 {788; CHECK-LABEL: strict_vector_fptosi_v16f32_to_v16i16:789; CHECK: # %bb.0:790; CHECK-NEXT: vcvttps2dq %zmm0, %zmm0791; CHECK-NEXT: vpmovdw %zmm0, %ymm0792; CHECK-NEXT: ret{{[l|q]}}793 %ret = call <16 x i16> @llvm.experimental.constrained.fptosi.v16i16.v16f32(<16 x float> %a,794 metadata !"fpexcept.strict") #0795 ret <16 x i16> %ret796}797 798define <16 x i16> @strict_vector_fptoui_v16f32_to_v16i16(<16 x float> %a) #0 {799; CHECK-LABEL: strict_vector_fptoui_v16f32_to_v16i16:800; CHECK: # %bb.0:801; CHECK-NEXT: vcvttps2udq %zmm0, %zmm0802; CHECK-NEXT: vpmovdw %zmm0, %ymm0803; CHECK-NEXT: ret{{[l|q]}}804 %ret = call <16 x i16> @llvm.experimental.constrained.fptoui.v16i16.v16f32(<16 x float> %a,805 metadata !"fpexcept.strict") #0806 ret <16 x i16> %ret807}808 809define <16 x i8> @strict_vector_fptosi_v16f32_to_v16i8(<16 x float> %a) #0 {810; CHECK-LABEL: strict_vector_fptosi_v16f32_to_v16i8:811; CHECK: # %bb.0:812; CHECK-NEXT: vcvttps2dq %zmm0, %zmm0813; CHECK-NEXT: vpmovdb %zmm0, %xmm0814; CHECK-NEXT: vzeroupper815; CHECK-NEXT: ret{{[l|q]}}816 %ret = call <16 x i8> @llvm.experimental.constrained.fptosi.v16i8.v16f32(<16 x float> %a,817 metadata !"fpexcept.strict") #0818 ret <16 x i8> %ret819}820 821define <16 x i8> @strict_vector_fptoui_v16f32_to_v16i8(<16 x float> %a) #0 {822; CHECK-LABEL: strict_vector_fptoui_v16f32_to_v16i8:823; CHECK: # %bb.0:824; CHECK-NEXT: vcvttps2dq %zmm0, %zmm0825; CHECK-NEXT: vpmovdb %zmm0, %xmm0826; CHECK-NEXT: vzeroupper827; CHECK-NEXT: ret{{[l|q]}}828 %ret = call <16 x i8> @llvm.experimental.constrained.fptoui.v16i8.v16f32(<16 x float> %a,829 metadata !"fpexcept.strict") #0830 ret <16 x i8> %ret831}832 833define <16 x i1> @strict_vector_fptosi_v16f32_to_v16i1(<16 x float> %a) #0 {834; AVX512VL-LABEL: strict_vector_fptosi_v16f32_to_v16i1:835; AVX512VL: # %bb.0:836; AVX512VL-NEXT: vcvttps2dq %zmm0, %zmm0837; AVX512VL-NEXT: vptestmd %zmm0, %zmm0, %k1838; AVX512VL-NEXT: vpternlogd {{.*#+}} zmm0 {%k1} {z} = -1839; AVX512VL-NEXT: vpmovdb %zmm0, %xmm0840; AVX512VL-NEXT: vzeroupper841; AVX512VL-NEXT: ret{{[l|q]}}842;843; AVX512DQ-LABEL: strict_vector_fptosi_v16f32_to_v16i1:844; AVX512DQ: # %bb.0:845; AVX512DQ-NEXT: vcvttps2dq %zmm0, %zmm0846; AVX512DQ-NEXT: vpmovd2m %zmm0, %k0847; AVX512DQ-NEXT: vpmovm2d %k0, %zmm0848; AVX512DQ-NEXT: vpmovdb %zmm0, %xmm0849; AVX512DQ-NEXT: vzeroupper850; AVX512DQ-NEXT: ret{{[l|q]}}851 %ret = call <16 x i1> @llvm.experimental.constrained.fptosi.v16i1.v16f32(<16 x float> %a,852 metadata !"fpexcept.strict") #0853 ret <16 x i1> %ret854}855 856define <16 x i1> @strict_vector_fptoui_v16f32_to_v16i1(<16 x float> %a) #0 {857; AVX512VL-LABEL: strict_vector_fptoui_v16f32_to_v16i1:858; AVX512VL: # %bb.0:859; AVX512VL-NEXT: vcvttps2dq %zmm0, %zmm0860; AVX512VL-NEXT: vpslld $31, %zmm0, %zmm0861; AVX512VL-NEXT: vptestmd %zmm0, %zmm0, %k1862; AVX512VL-NEXT: vpternlogd {{.*#+}} zmm0 {%k1} {z} = -1863; AVX512VL-NEXT: vpmovdb %zmm0, %xmm0864; AVX512VL-NEXT: vzeroupper865; AVX512VL-NEXT: ret{{[l|q]}}866;867; AVX512DQ-LABEL: strict_vector_fptoui_v16f32_to_v16i1:868; AVX512DQ: # %bb.0:869; AVX512DQ-NEXT: vcvttps2dq %zmm0, %zmm0870; AVX512DQ-NEXT: vpslld $31, %zmm0, %zmm0871; AVX512DQ-NEXT: vpmovd2m %zmm0, %k0872; AVX512DQ-NEXT: vpmovm2d %k0, %zmm0873; AVX512DQ-NEXT: vpmovdb %zmm0, %xmm0874; AVX512DQ-NEXT: vzeroupper875; AVX512DQ-NEXT: ret{{[l|q]}}876 %ret = call <16 x i1> @llvm.experimental.constrained.fptoui.v16i1.v16f32(<16 x float> %a,877 metadata !"fpexcept.strict") #0878 ret <16 x i1> %ret879}880 881 882attributes #0 = { strictfp }883