1500 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 -O3 | FileCheck %s --check-prefixes=SSE,SSE-323; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 -O3 | FileCheck %s --check-prefixes=SSE,SSE-644; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 -O3 | FileCheck %s --check-prefixes=SSE41,SSE41-325; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 -O3 | FileCheck %s --check-prefixes=SSE41,SSE41-646; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx -O3 | FileCheck %s --check-prefixes=AVX,AVX1,AVX-32,AVX1-327; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx -O3 | FileCheck %s --check-prefixes=AVX,AVX1,AVX-64,AVX1-648; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512f -O3 | FileCheck %s --check-prefixes=AVX,AVX512F,AVX-329; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f -O3 | FileCheck %s --check-prefixes=AVX,AVX512F,AVX-64,AVX512F-6410; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=avx512vl -O3 | FileCheck %s --check-prefixes=AVX,AVX512VL,AVX-32,AVX512VL-3211; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512vl -O3 | FileCheck %s --check-prefixes=AVX,AVX512VL,AVX-64,AVX512VL-6412; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=avx512f,avx512dq -O3 | FileCheck %s --check-prefixes=AVX,AVX512DQ,AVX512DQ-3213; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f,avx512dq -O3 | FileCheck %s --check-prefixes=AVX,AVX512DQ,AVX512DQ-6414; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=avx512dq,avx512vl -O3 | FileCheck %s --check-prefixes=AVX,AVX512DQVL,AVX512DQVL-3215; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512dq,avx512vl -O3 | FileCheck %s --check-prefixes=AVX,AVX512DQVL,AVX512DQVL-6416 17declare <2 x float> @llvm.experimental.constrained.sitofp.v2f32.v2i32(<2 x i32>, metadata, metadata)18declare <2 x float> @llvm.experimental.constrained.uitofp.v2f32.v2i32(<2 x i32>, metadata, metadata)19declare <2 x float> @llvm.experimental.constrained.sitofp.v2f32.v2i64(<2 x i64>, metadata, metadata)20declare <2 x float> @llvm.experimental.constrained.uitofp.v2f32.v2i64(<2 x i64>, metadata, metadata)21declare <4 x float> @llvm.experimental.constrained.sitofp.v4f32.v4i1(<4 x i1>, metadata, metadata)22declare <4 x float> @llvm.experimental.constrained.uitofp.v4f32.v4i1(<4 x i1>, metadata, metadata)23declare <4 x float> @llvm.experimental.constrained.sitofp.v4f32.v4i8(<4 x i8>, metadata, metadata)24declare <4 x float> @llvm.experimental.constrained.uitofp.v4f32.v4i8(<4 x i8>, metadata, metadata)25declare <4 x float> @llvm.experimental.constrained.sitofp.v4f32.v4i16(<4 x i16>, metadata, metadata)26declare <4 x float> @llvm.experimental.constrained.uitofp.v4f32.v4i16(<4 x i16>, metadata, metadata)27declare <4 x float> @llvm.experimental.constrained.sitofp.v4f32.v4i32(<4 x i32>, metadata, metadata)28declare <4 x float> @llvm.experimental.constrained.uitofp.v4f32.v4i32(<4 x i32>, metadata, metadata)29declare <2 x double> @llvm.experimental.constrained.sitofp.v2f64.v2i1(<2 x i1>, metadata, metadata)30declare <2 x double> @llvm.experimental.constrained.uitofp.v2f64.v2i1(<2 x i1>, metadata, metadata)31declare <2 x double> @llvm.experimental.constrained.sitofp.v2f64.v2i8(<2 x i8>, metadata, metadata)32declare <2 x double> @llvm.experimental.constrained.uitofp.v2f64.v2i8(<2 x i8>, metadata, metadata)33declare <2 x double> @llvm.experimental.constrained.sitofp.v2f64.v2i16(<2 x i16>, metadata, metadata)34declare <2 x double> @llvm.experimental.constrained.uitofp.v2f64.v2i16(<2 x i16>, metadata, metadata)35declare <2 x double> @llvm.experimental.constrained.sitofp.v2f64.v2i32(<2 x i32>, metadata, metadata)36declare <2 x double> @llvm.experimental.constrained.uitofp.v2f64.v2i32(<2 x i32>, metadata, metadata)37declare <2 x double> @llvm.experimental.constrained.sitofp.v2f64.v2i64(<2 x i64>, metadata, metadata)38declare <2 x double> @llvm.experimental.constrained.uitofp.v2f64.v2i64(<2 x i64>, metadata, metadata)39 40define <2 x float> @sitofp_v2i32_v2f32(<2 x i32> %x) #0 {41; SSE-LABEL: sitofp_v2i32_v2f32:42; SSE: # %bb.0:43; SSE-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero44; SSE-NEXT: cvtdq2ps %xmm0, %xmm045; SSE-NEXT: ret{{[l|q]}}46;47; SSE41-LABEL: sitofp_v2i32_v2f32:48; SSE41: # %bb.0:49; SSE41-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero50; SSE41-NEXT: cvtdq2ps %xmm0, %xmm051; SSE41-NEXT: ret{{[l|q]}}52;53; AVX-LABEL: sitofp_v2i32_v2f32:54; AVX: # %bb.0:55; AVX-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero56; AVX-NEXT: vcvtdq2ps %xmm0, %xmm057; AVX-NEXT: ret{{[l|q]}}58 %result = call <2 x float> @llvm.experimental.constrained.sitofp.v2f32.v2i32(<2 x i32> %x,59 metadata !"round.dynamic",60 metadata !"fpexcept.strict") #061 ret <2 x float> %result62}63 64define <2 x float> @uitofp_v2i32_v2f32(<2 x i32> %x) #0 {65; SSE-LABEL: uitofp_v2i32_v2f32:66; SSE: # %bb.0:67; SSE-NEXT: xorpd %xmm1, %xmm168; SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]69; SSE-NEXT: movapd {{.*#+}} xmm1 = [4.503599627370496E+15,4.503599627370496E+15]70; SSE-NEXT: orpd %xmm1, %xmm071; SSE-NEXT: subpd %xmm1, %xmm072; SSE-NEXT: cvtpd2ps %xmm0, %xmm073; SSE-NEXT: ret{{[l|q]}}74;75; SSE41-LABEL: uitofp_v2i32_v2f32:76; SSE41: # %bb.0:77; SSE41-NEXT: xorpd %xmm1, %xmm178; SSE41-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]79; SSE41-NEXT: movapd {{.*#+}} xmm1 = [4.503599627370496E+15,4.503599627370496E+15]80; SSE41-NEXT: orpd %xmm1, %xmm081; SSE41-NEXT: subpd %xmm1, %xmm082; SSE41-NEXT: cvtpd2ps %xmm0, %xmm083; SSE41-NEXT: ret{{[l|q]}}84;85; AVX1-LABEL: uitofp_v2i32_v2f32:86; AVX1: # %bb.0:87; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero88; AVX1-NEXT: vmovddup {{.*#+}} xmm1 = [4.503599627370496E+15,4.503599627370496E+15]89; AVX1-NEXT: # xmm1 = mem[0,0]90; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm091; AVX1-NEXT: vsubpd %xmm1, %xmm0, %xmm092; AVX1-NEXT: vcvtpd2ps %xmm0, %xmm093; AVX1-NEXT: ret{{[l|q]}}94;95; AVX512F-LABEL: uitofp_v2i32_v2f32:96; AVX512F: # %bb.0:97; AVX512F-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero98; AVX512F-NEXT: vcvtudq2ps %zmm0, %zmm099; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0100; AVX512F-NEXT: vzeroupper101; AVX512F-NEXT: ret{{[l|q]}}102;103; AVX512VL-LABEL: uitofp_v2i32_v2f32:104; AVX512VL: # %bb.0:105; AVX512VL-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero106; AVX512VL-NEXT: vcvtudq2ps %xmm0, %xmm0107; AVX512VL-NEXT: ret{{[l|q]}}108;109; AVX512DQ-LABEL: uitofp_v2i32_v2f32:110; AVX512DQ: # %bb.0:111; AVX512DQ-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero112; AVX512DQ-NEXT: vcvtudq2ps %zmm0, %zmm0113; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0114; AVX512DQ-NEXT: vzeroupper115; AVX512DQ-NEXT: ret{{[l|q]}}116;117; AVX512DQVL-LABEL: uitofp_v2i32_v2f32:118; AVX512DQVL: # %bb.0:119; AVX512DQVL-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero120; AVX512DQVL-NEXT: vcvtudq2ps %xmm0, %xmm0121; AVX512DQVL-NEXT: ret{{[l|q]}}122 %result = call <2 x float> @llvm.experimental.constrained.uitofp.v2f32.v2i32(<2 x i32> %x,123 metadata !"round.dynamic",124 metadata !"fpexcept.strict") #0125 ret <2 x float> %result126}127 128define <2 x float> @sitofp_v2i64_v2f32(<2 x i64> %x) #0 {129; SSE-32-LABEL: sitofp_v2i64_v2f32:130; SSE-32: # %bb.0:131; SSE-32-NEXT: pushl %ebp132; SSE-32-NEXT: .cfi_def_cfa_offset 8133; SSE-32-NEXT: .cfi_offset %ebp, -8134; SSE-32-NEXT: movl %esp, %ebp135; SSE-32-NEXT: .cfi_def_cfa_register %ebp136; SSE-32-NEXT: andl $-8, %esp137; SSE-32-NEXT: subl $24, %esp138; SSE-32-NEXT: movq %xmm0, {{[0-9]+}}(%esp)139; SSE-32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]140; SSE-32-NEXT: movq %xmm0, {{[0-9]+}}(%esp)141; SSE-32-NEXT: fildll {{[0-9]+}}(%esp)142; SSE-32-NEXT: fstps (%esp)143; SSE-32-NEXT: fildll {{[0-9]+}}(%esp)144; SSE-32-NEXT: fstps {{[0-9]+}}(%esp)145; SSE-32-NEXT: wait146; SSE-32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero147; SSE-32-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero148; SSE-32-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]149; SSE-32-NEXT: movl %ebp, %esp150; SSE-32-NEXT: popl %ebp151; SSE-32-NEXT: .cfi_def_cfa %esp, 4152; SSE-32-NEXT: retl153;154; SSE-64-LABEL: sitofp_v2i64_v2f32:155; SSE-64: # %bb.0:156; SSE-64-NEXT: movq %xmm0, %rax157; SSE-64-NEXT: cvtsi2ss %rax, %xmm1158; SSE-64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]159; SSE-64-NEXT: movq %xmm0, %rax160; SSE-64-NEXT: xorps %xmm0, %xmm0161; SSE-64-NEXT: cvtsi2ss %rax, %xmm0162; SSE-64-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]163; SSE-64-NEXT: movaps %xmm1, %xmm0164; SSE-64-NEXT: retq165;166; SSE41-32-LABEL: sitofp_v2i64_v2f32:167; SSE41-32: # %bb.0:168; SSE41-32-NEXT: pushl %ebp169; SSE41-32-NEXT: .cfi_def_cfa_offset 8170; SSE41-32-NEXT: .cfi_offset %ebp, -8171; SSE41-32-NEXT: movl %esp, %ebp172; SSE41-32-NEXT: .cfi_def_cfa_register %ebp173; SSE41-32-NEXT: andl $-8, %esp174; SSE41-32-NEXT: subl $24, %esp175; SSE41-32-NEXT: movq %xmm0, {{[0-9]+}}(%esp)176; SSE41-32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]177; SSE41-32-NEXT: movq %xmm0, {{[0-9]+}}(%esp)178; SSE41-32-NEXT: fildll {{[0-9]+}}(%esp)179; SSE41-32-NEXT: fstps (%esp)180; SSE41-32-NEXT: fildll {{[0-9]+}}(%esp)181; SSE41-32-NEXT: fstps {{[0-9]+}}(%esp)182; SSE41-32-NEXT: wait183; SSE41-32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero184; SSE41-32-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero185; SSE41-32-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]186; SSE41-32-NEXT: movl %ebp, %esp187; SSE41-32-NEXT: popl %ebp188; SSE41-32-NEXT: .cfi_def_cfa %esp, 4189; SSE41-32-NEXT: retl190;191; SSE41-64-LABEL: sitofp_v2i64_v2f32:192; SSE41-64: # %bb.0:193; SSE41-64-NEXT: movq %xmm0, %rax194; SSE41-64-NEXT: cvtsi2ss %rax, %xmm1195; SSE41-64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]196; SSE41-64-NEXT: movq %xmm0, %rax197; SSE41-64-NEXT: xorps %xmm0, %xmm0198; SSE41-64-NEXT: cvtsi2ss %rax, %xmm0199; SSE41-64-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]200; SSE41-64-NEXT: movaps %xmm1, %xmm0201; SSE41-64-NEXT: retq202;203; AVX-32-LABEL: sitofp_v2i64_v2f32:204; AVX-32: # %bb.0:205; AVX-32-NEXT: pushl %ebp206; AVX-32-NEXT: .cfi_def_cfa_offset 8207; AVX-32-NEXT: .cfi_offset %ebp, -8208; AVX-32-NEXT: movl %esp, %ebp209; AVX-32-NEXT: .cfi_def_cfa_register %ebp210; AVX-32-NEXT: andl $-8, %esp211; AVX-32-NEXT: subl $24, %esp212; AVX-32-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)213; AVX-32-NEXT: vshufps {{.*#+}} xmm0 = xmm0[2,3,2,3]214; AVX-32-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)215; AVX-32-NEXT: fildll {{[0-9]+}}(%esp)216; AVX-32-NEXT: fstps (%esp)217; AVX-32-NEXT: fildll {{[0-9]+}}(%esp)218; AVX-32-NEXT: fstps {{[0-9]+}}(%esp)219; AVX-32-NEXT: wait220; AVX-32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero221; AVX-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3]222; AVX-32-NEXT: movl %ebp, %esp223; AVX-32-NEXT: popl %ebp224; AVX-32-NEXT: .cfi_def_cfa %esp, 4225; AVX-32-NEXT: retl226;227; AVX-64-LABEL: sitofp_v2i64_v2f32:228; AVX-64: # %bb.0:229; AVX-64-NEXT: vpextrq $1, %xmm0, %rax230; AVX-64-NEXT: vcvtsi2ss %rax, %xmm15, %xmm1231; AVX-64-NEXT: vmovq %xmm0, %rax232; AVX-64-NEXT: vcvtsi2ss %rax, %xmm15, %xmm0233; AVX-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]234; AVX-64-NEXT: retq235;236; AVX512DQ-32-LABEL: sitofp_v2i64_v2f32:237; AVX512DQ-32: # %bb.0:238; AVX512DQ-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0239; AVX512DQ-32-NEXT: vcvtqq2ps %zmm0, %ymm1240; AVX512DQ-32-NEXT: vshufps {{.*#+}} xmm0 = xmm0[2,3,2,3]241; AVX512DQ-32-NEXT: vcvtqq2ps %zmm0, %ymm0242; AVX512DQ-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],zero,zero243; AVX512DQ-32-NEXT: vzeroupper244; AVX512DQ-32-NEXT: retl245;246; AVX512DQ-64-LABEL: sitofp_v2i64_v2f32:247; AVX512DQ-64: # %bb.0:248; AVX512DQ-64-NEXT: vpextrq $1, %xmm0, %rax249; AVX512DQ-64-NEXT: vcvtsi2ss %rax, %xmm15, %xmm1250; AVX512DQ-64-NEXT: vmovq %xmm0, %rax251; AVX512DQ-64-NEXT: vcvtsi2ss %rax, %xmm15, %xmm0252; AVX512DQ-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]253; AVX512DQ-64-NEXT: retq254;255; AVX512DQVL-LABEL: sitofp_v2i64_v2f32:256; AVX512DQVL: # %bb.0:257; AVX512DQVL-NEXT: vcvtqq2ps %xmm0, %xmm0258; AVX512DQVL-NEXT: ret{{[l|q]}}259 %result = call <2 x float> @llvm.experimental.constrained.sitofp.v2f32.v2i64(<2 x i64> %x,260 metadata !"round.dynamic",261 metadata !"fpexcept.strict") #0262 ret <2 x float> %result263}264 265define <2 x float> @uitofp_v2i64_v2f32(<2 x i64> %x) #0 {266; SSE-32-LABEL: uitofp_v2i64_v2f32:267; SSE-32: # %bb.0:268; SSE-32-NEXT: pushl %ebp269; SSE-32-NEXT: .cfi_def_cfa_offset 8270; SSE-32-NEXT: .cfi_offset %ebp, -8271; SSE-32-NEXT: movl %esp, %ebp272; SSE-32-NEXT: .cfi_def_cfa_register %ebp273; SSE-32-NEXT: andl $-8, %esp274; SSE-32-NEXT: subl $24, %esp275; SSE-32-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]276; SSE-32-NEXT: movq %xmm1, {{[0-9]+}}(%esp)277; SSE-32-NEXT: movq %xmm0, {{[0-9]+}}(%esp)278; SSE-32-NEXT: pshufd {{.*#+}} xmm1 = xmm0[3,3,3,3]279; SSE-32-NEXT: movd %xmm1, %eax280; SSE-32-NEXT: shrl $31, %eax281; SSE-32-NEXT: fildll {{[0-9]+}}(%esp)282; SSE-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)283; SSE-32-NEXT: fstps (%esp)284; SSE-32-NEXT: wait285; SSE-32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]286; SSE-32-NEXT: movd %xmm0, %eax287; SSE-32-NEXT: shrl $31, %eax288; SSE-32-NEXT: fildll {{[0-9]+}}(%esp)289; SSE-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)290; SSE-32-NEXT: fstps {{[0-9]+}}(%esp)291; SSE-32-NEXT: wait292; SSE-32-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero293; SSE-32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero294; SSE-32-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]295; SSE-32-NEXT: movl %ebp, %esp296; SSE-32-NEXT: popl %ebp297; SSE-32-NEXT: .cfi_def_cfa %esp, 4298; SSE-32-NEXT: retl299;300; SSE-64-LABEL: uitofp_v2i64_v2f32:301; SSE-64: # %bb.0:302; SSE-64-NEXT: movdqa %xmm0, %xmm1303; SSE-64-NEXT: movq %xmm0, %rax304; SSE-64-NEXT: movq %rax, %rcx305; SSE-64-NEXT: shrq %rcx306; SSE-64-NEXT: movl %eax, %edx307; SSE-64-NEXT: andl $1, %edx308; SSE-64-NEXT: orq %rcx, %rdx309; SSE-64-NEXT: testq %rax, %rax310; SSE-64-NEXT: cmovnsq %rax, %rdx311; SSE-64-NEXT: xorps %xmm0, %xmm0312; SSE-64-NEXT: cvtsi2ss %rdx, %xmm0313; SSE-64-NEXT: jns .LBB3_2314; SSE-64-NEXT: # %bb.1:315; SSE-64-NEXT: addss %xmm0, %xmm0316; SSE-64-NEXT: .LBB3_2:317; SSE-64-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]318; SSE-64-NEXT: movq %xmm1, %rax319; SSE-64-NEXT: movq %rax, %rcx320; SSE-64-NEXT: shrq %rcx321; SSE-64-NEXT: movl %eax, %edx322; SSE-64-NEXT: andl $1, %edx323; SSE-64-NEXT: orq %rcx, %rdx324; SSE-64-NEXT: testq %rax, %rax325; SSE-64-NEXT: cmovnsq %rax, %rdx326; SSE-64-NEXT: xorps %xmm1, %xmm1327; SSE-64-NEXT: cvtsi2ss %rdx, %xmm1328; SSE-64-NEXT: jns .LBB3_4329; SSE-64-NEXT: # %bb.3:330; SSE-64-NEXT: addss %xmm1, %xmm1331; SSE-64-NEXT: .LBB3_4:332; SSE-64-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]333; SSE-64-NEXT: retq334;335; SSE41-32-LABEL: uitofp_v2i64_v2f32:336; SSE41-32: # %bb.0:337; SSE41-32-NEXT: pushl %ebp338; SSE41-32-NEXT: .cfi_def_cfa_offset 8339; SSE41-32-NEXT: .cfi_offset %ebp, -8340; SSE41-32-NEXT: movl %esp, %ebp341; SSE41-32-NEXT: .cfi_def_cfa_register %ebp342; SSE41-32-NEXT: andl $-8, %esp343; SSE41-32-NEXT: subl $24, %esp344; SSE41-32-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]345; SSE41-32-NEXT: movq %xmm1, {{[0-9]+}}(%esp)346; SSE41-32-NEXT: movq %xmm0, {{[0-9]+}}(%esp)347; SSE41-32-NEXT: pshufd {{.*#+}} xmm1 = xmm0[3,3,3,3]348; SSE41-32-NEXT: movd %xmm1, %eax349; SSE41-32-NEXT: shrl $31, %eax350; SSE41-32-NEXT: fildll {{[0-9]+}}(%esp)351; SSE41-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)352; SSE41-32-NEXT: fstps (%esp)353; SSE41-32-NEXT: wait354; SSE41-32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]355; SSE41-32-NEXT: movd %xmm0, %eax356; SSE41-32-NEXT: shrl $31, %eax357; SSE41-32-NEXT: fildll {{[0-9]+}}(%esp)358; SSE41-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)359; SSE41-32-NEXT: fstps {{[0-9]+}}(%esp)360; SSE41-32-NEXT: wait361; SSE41-32-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero362; SSE41-32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero363; SSE41-32-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]364; SSE41-32-NEXT: movl %ebp, %esp365; SSE41-32-NEXT: popl %ebp366; SSE41-32-NEXT: .cfi_def_cfa %esp, 4367; SSE41-32-NEXT: retl368;369; SSE41-64-LABEL: uitofp_v2i64_v2f32:370; SSE41-64: # %bb.0:371; SSE41-64-NEXT: movdqa %xmm0, %xmm1372; SSE41-64-NEXT: movq %xmm0, %rax373; SSE41-64-NEXT: movq %rax, %rcx374; SSE41-64-NEXT: shrq %rcx375; SSE41-64-NEXT: movl %eax, %edx376; SSE41-64-NEXT: andl $1, %edx377; SSE41-64-NEXT: orq %rcx, %rdx378; SSE41-64-NEXT: testq %rax, %rax379; SSE41-64-NEXT: cmovnsq %rax, %rdx380; SSE41-64-NEXT: xorps %xmm0, %xmm0381; SSE41-64-NEXT: cvtsi2ss %rdx, %xmm0382; SSE41-64-NEXT: jns .LBB3_2383; SSE41-64-NEXT: # %bb.1:384; SSE41-64-NEXT: addss %xmm0, %xmm0385; SSE41-64-NEXT: .LBB3_2:386; SSE41-64-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]387; SSE41-64-NEXT: movq %xmm1, %rax388; SSE41-64-NEXT: movq %rax, %rcx389; SSE41-64-NEXT: shrq %rcx390; SSE41-64-NEXT: movl %eax, %edx391; SSE41-64-NEXT: andl $1, %edx392; SSE41-64-NEXT: orq %rcx, %rdx393; SSE41-64-NEXT: testq %rax, %rax394; SSE41-64-NEXT: cmovnsq %rax, %rdx395; SSE41-64-NEXT: xorps %xmm1, %xmm1396; SSE41-64-NEXT: cvtsi2ss %rdx, %xmm1397; SSE41-64-NEXT: jns .LBB3_4398; SSE41-64-NEXT: # %bb.3:399; SSE41-64-NEXT: addss %xmm1, %xmm1400; SSE41-64-NEXT: .LBB3_4:401; SSE41-64-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]402; SSE41-64-NEXT: retq403;404; AVX-32-LABEL: uitofp_v2i64_v2f32:405; AVX-32: # %bb.0:406; AVX-32-NEXT: pushl %ebp407; AVX-32-NEXT: .cfi_def_cfa_offset 8408; AVX-32-NEXT: .cfi_offset %ebp, -8409; AVX-32-NEXT: movl %esp, %ebp410; AVX-32-NEXT: .cfi_def_cfa_register %ebp411; AVX-32-NEXT: andl $-8, %esp412; AVX-32-NEXT: subl $24, %esp413; AVX-32-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)414; AVX-32-NEXT: vshufps {{.*#+}} xmm1 = xmm0[2,3,2,3]415; AVX-32-NEXT: vmovlps %xmm1, {{[0-9]+}}(%esp)416; AVX-32-NEXT: vextractps $1, %xmm0, %eax417; AVX-32-NEXT: shrl $31, %eax418; AVX-32-NEXT: fildll {{[0-9]+}}(%esp)419; AVX-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)420; AVX-32-NEXT: fstps {{[0-9]+}}(%esp)421; AVX-32-NEXT: wait422; AVX-32-NEXT: vextractps $3, %xmm0, %eax423; AVX-32-NEXT: shrl $31, %eax424; AVX-32-NEXT: fildll {{[0-9]+}}(%esp)425; AVX-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)426; AVX-32-NEXT: fstps (%esp)427; AVX-32-NEXT: wait428; AVX-32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero429; AVX-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3]430; AVX-32-NEXT: movl %ebp, %esp431; AVX-32-NEXT: popl %ebp432; AVX-32-NEXT: .cfi_def_cfa %esp, 4433; AVX-32-NEXT: retl434;435; AVX1-64-LABEL: uitofp_v2i64_v2f32:436; AVX1-64: # %bb.0:437; AVX1-64-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1438; AVX1-64-NEXT: vpsrlq $1, %xmm0, %xmm2439; AVX1-64-NEXT: vpor %xmm1, %xmm2, %xmm1440; AVX1-64-NEXT: vblendvpd %xmm0, %xmm1, %xmm0, %xmm1441; AVX1-64-NEXT: vpextrq $1, %xmm1, %rax442; AVX1-64-NEXT: vcvtsi2ss %rax, %xmm15, %xmm2443; AVX1-64-NEXT: vmovq %xmm1, %rax444; AVX1-64-NEXT: vcvtsi2ss %rax, %xmm15, %xmm1445; AVX1-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],xmm2[0],zero,zero446; AVX1-64-NEXT: vaddps %xmm1, %xmm1, %xmm2447; AVX1-64-NEXT: vpxor %xmm3, %xmm3, %xmm3448; AVX1-64-NEXT: vpcmpgtq %xmm0, %xmm3, %xmm0449; AVX1-64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,3,2,3]450; AVX1-64-NEXT: vblendvps %xmm0, %xmm2, %xmm1, %xmm0451; AVX1-64-NEXT: retq452;453; AVX512F-64-LABEL: uitofp_v2i64_v2f32:454; AVX512F-64: # %bb.0:455; AVX512F-64-NEXT: vpextrq $1, %xmm0, %rax456; AVX512F-64-NEXT: vcvtusi2ss %rax, %xmm15, %xmm1457; AVX512F-64-NEXT: vmovq %xmm0, %rax458; AVX512F-64-NEXT: vcvtusi2ss %rax, %xmm15, %xmm0459; AVX512F-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]460; AVX512F-64-NEXT: retq461;462; AVX512VL-64-LABEL: uitofp_v2i64_v2f32:463; AVX512VL-64: # %bb.0:464; AVX512VL-64-NEXT: vpextrq $1, %xmm0, %rax465; AVX512VL-64-NEXT: vcvtusi2ss %rax, %xmm15, %xmm1466; AVX512VL-64-NEXT: vmovq %xmm0, %rax467; AVX512VL-64-NEXT: vcvtusi2ss %rax, %xmm15, %xmm0468; AVX512VL-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]469; AVX512VL-64-NEXT: retq470;471; AVX512DQ-32-LABEL: uitofp_v2i64_v2f32:472; AVX512DQ-32: # %bb.0:473; AVX512DQ-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0474; AVX512DQ-32-NEXT: vcvtuqq2ps %zmm0, %ymm1475; AVX512DQ-32-NEXT: vshufps {{.*#+}} xmm0 = xmm0[2,3,2,3]476; AVX512DQ-32-NEXT: vcvtuqq2ps %zmm0, %ymm0477; AVX512DQ-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],zero,zero478; AVX512DQ-32-NEXT: vzeroupper479; AVX512DQ-32-NEXT: retl480;481; AVX512DQ-64-LABEL: uitofp_v2i64_v2f32:482; AVX512DQ-64: # %bb.0:483; AVX512DQ-64-NEXT: vpextrq $1, %xmm0, %rax484; AVX512DQ-64-NEXT: vcvtusi2ss %rax, %xmm15, %xmm1485; AVX512DQ-64-NEXT: vmovq %xmm0, %rax486; AVX512DQ-64-NEXT: vcvtusi2ss %rax, %xmm15, %xmm0487; AVX512DQ-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]488; AVX512DQ-64-NEXT: retq489;490; AVX512DQVL-LABEL: uitofp_v2i64_v2f32:491; AVX512DQVL: # %bb.0:492; AVX512DQVL-NEXT: vcvtuqq2ps %xmm0, %xmm0493; AVX512DQVL-NEXT: ret{{[l|q]}}494 %result = call <2 x float> @llvm.experimental.constrained.uitofp.v2f32.v2i64(<2 x i64> %x,495 metadata !"round.dynamic",496 metadata !"fpexcept.strict") #0497 ret <2 x float> %result498}499 500define <4 x float> @sitofp_v4i1_v4f32(<4 x i1> %x) #0 {501; SSE-LABEL: sitofp_v4i1_v4f32:502; SSE: # %bb.0:503; SSE-NEXT: pslld $31, %xmm0504; SSE-NEXT: psrad $31, %xmm0505; SSE-NEXT: cvtdq2ps %xmm0, %xmm0506; SSE-NEXT: ret{{[l|q]}}507;508; SSE41-LABEL: sitofp_v4i1_v4f32:509; SSE41: # %bb.0:510; SSE41-NEXT: pslld $31, %xmm0511; SSE41-NEXT: psrad $31, %xmm0512; SSE41-NEXT: cvtdq2ps %xmm0, %xmm0513; SSE41-NEXT: ret{{[l|q]}}514;515; AVX-LABEL: sitofp_v4i1_v4f32:516; AVX: # %bb.0:517; AVX-NEXT: vpslld $31, %xmm0, %xmm0518; AVX-NEXT: vpsrad $31, %xmm0, %xmm0519; AVX-NEXT: vcvtdq2ps %xmm0, %xmm0520; AVX-NEXT: ret{{[l|q]}}521 %result = call <4 x float> @llvm.experimental.constrained.sitofp.v4f32.v4i1(<4 x i1> %x,522 metadata !"round.dynamic",523 metadata !"fpexcept.strict") #0524 ret <4 x float> %result525}526 527define <4 x float> @uitofp_v4i1_v4f32(<4 x i1> %x) #0 {528; SSE-32-LABEL: uitofp_v4i1_v4f32:529; SSE-32: # %bb.0:530; SSE-32-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0531; SSE-32-NEXT: cvtdq2ps %xmm0, %xmm0532; SSE-32-NEXT: retl533;534; SSE-64-LABEL: uitofp_v4i1_v4f32:535; SSE-64: # %bb.0:536; SSE-64-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0537; SSE-64-NEXT: cvtdq2ps %xmm0, %xmm0538; SSE-64-NEXT: retq539;540; SSE41-32-LABEL: uitofp_v4i1_v4f32:541; SSE41-32: # %bb.0:542; SSE41-32-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0543; SSE41-32-NEXT: cvtdq2ps %xmm0, %xmm0544; SSE41-32-NEXT: retl545;546; SSE41-64-LABEL: uitofp_v4i1_v4f32:547; SSE41-64: # %bb.0:548; SSE41-64-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0549; SSE41-64-NEXT: cvtdq2ps %xmm0, %xmm0550; SSE41-64-NEXT: retq551;552; AVX1-32-LABEL: uitofp_v4i1_v4f32:553; AVX1-32: # %bb.0:554; AVX1-32-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0555; AVX1-32-NEXT: vcvtdq2ps %xmm0, %xmm0556; AVX1-32-NEXT: retl557;558; AVX1-64-LABEL: uitofp_v4i1_v4f32:559; AVX1-64: # %bb.0:560; AVX1-64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0561; AVX1-64-NEXT: vcvtdq2ps %xmm0, %xmm0562; AVX1-64-NEXT: retq563;564; AVX512F-LABEL: uitofp_v4i1_v4f32:565; AVX512F: # %bb.0:566; AVX512F-NEXT: vbroadcastss {{.*#+}} xmm1 = [1,1,1,1]567; AVX512F-NEXT: vandps %xmm1, %xmm0, %xmm0568; AVX512F-NEXT: vcvtdq2ps %xmm0, %xmm0569; AVX512F-NEXT: ret{{[l|q]}}570;571; AVX512VL-32-LABEL: uitofp_v4i1_v4f32:572; AVX512VL-32: # %bb.0:573; AVX512VL-32-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}{1to4}, %xmm0, %xmm0574; AVX512VL-32-NEXT: vcvtdq2ps %xmm0, %xmm0575; AVX512VL-32-NEXT: retl576;577; AVX512VL-64-LABEL: uitofp_v4i1_v4f32:578; AVX512VL-64: # %bb.0:579; AVX512VL-64-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0580; AVX512VL-64-NEXT: vcvtdq2ps %xmm0, %xmm0581; AVX512VL-64-NEXT: retq582;583; AVX512DQ-LABEL: uitofp_v4i1_v4f32:584; AVX512DQ: # %bb.0:585; AVX512DQ-NEXT: vbroadcastss {{.*#+}} xmm1 = [1,1,1,1]586; AVX512DQ-NEXT: vandps %xmm1, %xmm0, %xmm0587; AVX512DQ-NEXT: vcvtdq2ps %xmm0, %xmm0588; AVX512DQ-NEXT: ret{{[l|q]}}589;590; AVX512DQVL-32-LABEL: uitofp_v4i1_v4f32:591; AVX512DQVL-32: # %bb.0:592; AVX512DQVL-32-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}{1to4}, %xmm0, %xmm0593; AVX512DQVL-32-NEXT: vcvtdq2ps %xmm0, %xmm0594; AVX512DQVL-32-NEXT: retl595;596; AVX512DQVL-64-LABEL: uitofp_v4i1_v4f32:597; AVX512DQVL-64: # %bb.0:598; AVX512DQVL-64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0599; AVX512DQVL-64-NEXT: vcvtdq2ps %xmm0, %xmm0600; AVX512DQVL-64-NEXT: retq601 %result = call <4 x float> @llvm.experimental.constrained.uitofp.v4f32.v4i1(<4 x i1> %x,602 metadata !"round.dynamic",603 metadata !"fpexcept.strict") #0604 ret <4 x float> %result605}606 607define <4 x float> @sitofp_v4i8_v4f32(<4 x i8> %x) #0 {608; SSE-LABEL: sitofp_v4i8_v4f32:609; SSE: # %bb.0:610; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]611; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]612; SSE-NEXT: psrad $24, %xmm0613; SSE-NEXT: cvtdq2ps %xmm0, %xmm0614; SSE-NEXT: ret{{[l|q]}}615;616; SSE41-LABEL: sitofp_v4i8_v4f32:617; SSE41: # %bb.0:618; SSE41-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]619; SSE41-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]620; SSE41-NEXT: psrad $24, %xmm0621; SSE41-NEXT: cvtdq2ps %xmm0, %xmm0622; SSE41-NEXT: ret{{[l|q]}}623;624; AVX-LABEL: sitofp_v4i8_v4f32:625; AVX: # %bb.0:626; AVX-NEXT: vpmovsxbd %xmm0, %xmm0627; AVX-NEXT: vcvtdq2ps %xmm0, %xmm0628; AVX-NEXT: ret{{[l|q]}}629 %result = call <4 x float> @llvm.experimental.constrained.sitofp.v4f32.v4i8(<4 x i8> %x,630 metadata !"round.dynamic",631 metadata !"fpexcept.strict") #0632 ret <4 x float> %result633}634 635define <4 x float> @uitofp_v4i8_v4f32(<4 x i8> %x) #0 {636; SSE-LABEL: uitofp_v4i8_v4f32:637; SSE: # %bb.0:638; SSE-NEXT: pxor %xmm1, %xmm1639; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]640; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]641; SSE-NEXT: cvtdq2ps %xmm0, %xmm0642; SSE-NEXT: ret{{[l|q]}}643;644; SSE41-LABEL: uitofp_v4i8_v4f32:645; SSE41: # %bb.0:646; SSE41-NEXT: pxor %xmm1, %xmm1647; SSE41-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]648; SSE41-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]649; SSE41-NEXT: cvtdq2ps %xmm0, %xmm0650; SSE41-NEXT: ret{{[l|q]}}651;652; AVX-LABEL: uitofp_v4i8_v4f32:653; AVX: # %bb.0:654; AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero655; AVX-NEXT: vcvtdq2ps %xmm0, %xmm0656; AVX-NEXT: ret{{[l|q]}}657 %result = call <4 x float> @llvm.experimental.constrained.uitofp.v4f32.v4i8(<4 x i8> %x,658 metadata !"round.dynamic",659 metadata !"fpexcept.strict") #0660 ret <4 x float> %result661}662 663define <4 x float> @sitofp_v4i16_v4f32(<4 x i16> %x) #0 {664; SSE-LABEL: sitofp_v4i16_v4f32:665; SSE: # %bb.0:666; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]667; SSE-NEXT: psrad $16, %xmm0668; SSE-NEXT: cvtdq2ps %xmm0, %xmm0669; SSE-NEXT: ret{{[l|q]}}670;671; SSE41-LABEL: sitofp_v4i16_v4f32:672; SSE41: # %bb.0:673; SSE41-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]674; SSE41-NEXT: psrad $16, %xmm0675; SSE41-NEXT: cvtdq2ps %xmm0, %xmm0676; SSE41-NEXT: ret{{[l|q]}}677;678; AVX-LABEL: sitofp_v4i16_v4f32:679; AVX: # %bb.0:680; AVX-NEXT: vpmovsxwd %xmm0, %xmm0681; AVX-NEXT: vcvtdq2ps %xmm0, %xmm0682; AVX-NEXT: ret{{[l|q]}}683 %result = call <4 x float> @llvm.experimental.constrained.sitofp.v4f32.v4i16(<4 x i16> %x,684 metadata !"round.dynamic",685 metadata !"fpexcept.strict") #0686 ret <4 x float> %result687}688 689define <4 x float> @uitofp_v4i16_v4f32(<4 x i16> %x) #0 {690; SSE-LABEL: uitofp_v4i16_v4f32:691; SSE: # %bb.0:692; SSE-NEXT: pxor %xmm1, %xmm1693; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]694; SSE-NEXT: cvtdq2ps %xmm0, %xmm0695; SSE-NEXT: ret{{[l|q]}}696;697; SSE41-LABEL: uitofp_v4i16_v4f32:698; SSE41: # %bb.0:699; SSE41-NEXT: pxor %xmm1, %xmm1700; SSE41-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]701; SSE41-NEXT: cvtdq2ps %xmm0, %xmm0702; SSE41-NEXT: ret{{[l|q]}}703;704; AVX-LABEL: uitofp_v4i16_v4f32:705; AVX: # %bb.0:706; AVX-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero707; AVX-NEXT: vcvtdq2ps %xmm0, %xmm0708; AVX-NEXT: ret{{[l|q]}}709 %result = call <4 x float> @llvm.experimental.constrained.uitofp.v4f32.v4i16(<4 x i16> %x,710 metadata !"round.dynamic",711 metadata !"fpexcept.strict") #0712 ret <4 x float> %result713}714 715define <4 x float> @sitofp_v4i32_v4f32(<4 x i32> %x) #0 {716; SSE-LABEL: sitofp_v4i32_v4f32:717; SSE: # %bb.0:718; SSE-NEXT: cvtdq2ps %xmm0, %xmm0719; SSE-NEXT: ret{{[l|q]}}720;721; SSE41-LABEL: sitofp_v4i32_v4f32:722; SSE41: # %bb.0:723; SSE41-NEXT: cvtdq2ps %xmm0, %xmm0724; SSE41-NEXT: ret{{[l|q]}}725;726; AVX-LABEL: sitofp_v4i32_v4f32:727; AVX: # %bb.0:728; AVX-NEXT: vcvtdq2ps %xmm0, %xmm0729; AVX-NEXT: ret{{[l|q]}}730 %result = call <4 x float> @llvm.experimental.constrained.sitofp.v4f32.v4i32(<4 x i32> %x,731 metadata !"round.dynamic",732 metadata !"fpexcept.strict") #0733 ret <4 x float> %result734}735 736define <4 x float> @uitofp_v4i32_v4f32(<4 x i32> %x) #0 {737; SSE-32-LABEL: uitofp_v4i32_v4f32:738; SSE-32: # %bb.0:739; SSE-32-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535]740; SSE-32-NEXT: pand %xmm0, %xmm1741; SSE-32-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1742; SSE-32-NEXT: psrld $16, %xmm0743; SSE-32-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0744; SSE-32-NEXT: subps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0745; SSE-32-NEXT: addps %xmm1, %xmm0746; SSE-32-NEXT: retl747;748; SSE-64-LABEL: uitofp_v4i32_v4f32:749; SSE-64: # %bb.0:750; SSE-64-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535]751; SSE-64-NEXT: pand %xmm0, %xmm1752; SSE-64-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1753; SSE-64-NEXT: psrld $16, %xmm0754; SSE-64-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0755; SSE-64-NEXT: subps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0756; SSE-64-NEXT: addps %xmm1, %xmm0757; SSE-64-NEXT: retq758;759; SSE41-32-LABEL: uitofp_v4i32_v4f32:760; SSE41-32: # %bb.0:761; SSE41-32-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535]762; SSE41-32-NEXT: pand %xmm0, %xmm1763; SSE41-32-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1764; SSE41-32-NEXT: psrld $16, %xmm0765; SSE41-32-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0766; SSE41-32-NEXT: subps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0767; SSE41-32-NEXT: addps %xmm1, %xmm0768; SSE41-32-NEXT: retl769;770; SSE41-64-LABEL: uitofp_v4i32_v4f32:771; SSE41-64: # %bb.0:772; SSE41-64-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535]773; SSE41-64-NEXT: pand %xmm0, %xmm1774; SSE41-64-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1775; SSE41-64-NEXT: psrld $16, %xmm0776; SSE41-64-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0777; SSE41-64-NEXT: subps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0778; SSE41-64-NEXT: addps %xmm1, %xmm0779; SSE41-64-NEXT: retq780;781; AVX1-32-LABEL: uitofp_v4i32_v4f32:782; AVX1-32: # %bb.0:783; AVX1-32-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]784; AVX1-32-NEXT: vpsrld $16, %xmm0, %xmm0785; AVX1-32-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]786; AVX1-32-NEXT: vsubps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0787; AVX1-32-NEXT: vaddps %xmm0, %xmm1, %xmm0788; AVX1-32-NEXT: retl789;790; AVX1-64-LABEL: uitofp_v4i32_v4f32:791; AVX1-64: # %bb.0:792; AVX1-64-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]793; AVX1-64-NEXT: vpsrld $16, %xmm0, %xmm0794; AVX1-64-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]795; AVX1-64-NEXT: vsubps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0796; AVX1-64-NEXT: vaddps %xmm0, %xmm1, %xmm0797; AVX1-64-NEXT: retq798;799; AVX512F-LABEL: uitofp_v4i32_v4f32:800; AVX512F: # %bb.0:801; AVX512F-NEXT: vmovaps %xmm0, %xmm0802; AVX512F-NEXT: vcvtudq2ps %zmm0, %zmm0803; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0804; AVX512F-NEXT: vzeroupper805; AVX512F-NEXT: ret{{[l|q]}}806;807; AVX512VL-LABEL: uitofp_v4i32_v4f32:808; AVX512VL: # %bb.0:809; AVX512VL-NEXT: vcvtudq2ps %xmm0, %xmm0810; AVX512VL-NEXT: ret{{[l|q]}}811;812; AVX512DQ-LABEL: uitofp_v4i32_v4f32:813; AVX512DQ: # %bb.0:814; AVX512DQ-NEXT: vmovaps %xmm0, %xmm0815; AVX512DQ-NEXT: vcvtudq2ps %zmm0, %zmm0816; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0817; AVX512DQ-NEXT: vzeroupper818; AVX512DQ-NEXT: ret{{[l|q]}}819;820; AVX512DQVL-LABEL: uitofp_v4i32_v4f32:821; AVX512DQVL: # %bb.0:822; AVX512DQVL-NEXT: vcvtudq2ps %xmm0, %xmm0823; AVX512DQVL-NEXT: ret{{[l|q]}}824 %result = call <4 x float> @llvm.experimental.constrained.uitofp.v4f32.v4i32(<4 x i32> %x,825 metadata !"round.dynamic",826 metadata !"fpexcept.strict") #0827 ret <4 x float> %result828}829 830define <2 x double> @sitofp_v2i1_v2f64(<2 x i1> %x) #0 {831; SSE-LABEL: sitofp_v2i1_v2f64:832; SSE: # %bb.0:833; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]834; SSE-NEXT: pslld $31, %xmm0835; SSE-NEXT: psrad $31, %xmm0836; SSE-NEXT: cvtdq2pd %xmm0, %xmm0837; SSE-NEXT: ret{{[l|q]}}838;839; SSE41-LABEL: sitofp_v2i1_v2f64:840; SSE41: # %bb.0:841; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]842; SSE41-NEXT: pslld $31, %xmm0843; SSE41-NEXT: psrad $31, %xmm0844; SSE41-NEXT: cvtdq2pd %xmm0, %xmm0845; SSE41-NEXT: ret{{[l|q]}}846;847; AVX-LABEL: sitofp_v2i1_v2f64:848; AVX: # %bb.0:849; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]850; AVX-NEXT: vpslld $31, %xmm0, %xmm0851; AVX-NEXT: vpsrad $31, %xmm0, %xmm0852; AVX-NEXT: vcvtdq2pd %xmm0, %xmm0853; AVX-NEXT: ret{{[l|q]}}854 %result = call <2 x double> @llvm.experimental.constrained.sitofp.v2f64.v2i1(<2 x i1> %x,855 metadata !"round.dynamic",856 metadata !"fpexcept.strict") #0857 ret <2 x double> %result858}859 860define <2 x double> @uitofp_v2i1_v2f64(<2 x i1> %x) #0 {861; SSE-32-LABEL: uitofp_v2i1_v2f64:862; SSE-32: # %bb.0:863; SSE-32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]864; SSE-32-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0865; SSE-32-NEXT: cvtdq2pd %xmm0, %xmm0866; SSE-32-NEXT: retl867;868; SSE-64-LABEL: uitofp_v2i1_v2f64:869; SSE-64: # %bb.0:870; SSE-64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]871; SSE-64-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0872; SSE-64-NEXT: cvtdq2pd %xmm0, %xmm0873; SSE-64-NEXT: retq874;875; SSE41-32-LABEL: uitofp_v2i1_v2f64:876; SSE41-32: # %bb.0:877; SSE41-32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]878; SSE41-32-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0879; SSE41-32-NEXT: cvtdq2pd %xmm0, %xmm0880; SSE41-32-NEXT: retl881;882; SSE41-64-LABEL: uitofp_v2i1_v2f64:883; SSE41-64: # %bb.0:884; SSE41-64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]885; SSE41-64-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0886; SSE41-64-NEXT: cvtdq2pd %xmm0, %xmm0887; SSE41-64-NEXT: retq888;889; AVX1-32-LABEL: uitofp_v2i1_v2f64:890; AVX1-32: # %bb.0:891; AVX1-32-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2,2,3]892; AVX1-32-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0893; AVX1-32-NEXT: vcvtdq2pd %xmm0, %xmm0894; AVX1-32-NEXT: retl895;896; AVX1-64-LABEL: uitofp_v2i1_v2f64:897; AVX1-64: # %bb.0:898; AVX1-64-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2,2,3]899; AVX1-64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0900; AVX1-64-NEXT: vcvtdq2pd %xmm0, %xmm0901; AVX1-64-NEXT: retq902;903; AVX512F-LABEL: uitofp_v2i1_v2f64:904; AVX512F: # %bb.0:905; AVX512F-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2,2,3]906; AVX512F-NEXT: vbroadcastss {{.*#+}} xmm1 = [1,1,1,1]907; AVX512F-NEXT: vandps %xmm1, %xmm0, %xmm0908; AVX512F-NEXT: vcvtdq2pd %xmm0, %xmm0909; AVX512F-NEXT: ret{{[l|q]}}910;911; AVX512VL-32-LABEL: uitofp_v2i1_v2f64:912; AVX512VL-32: # %bb.0:913; AVX512VL-32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]914; AVX512VL-32-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}{1to4}, %xmm0, %xmm0915; AVX512VL-32-NEXT: vcvtdq2pd %xmm0, %xmm0916; AVX512VL-32-NEXT: retl917;918; AVX512VL-64-LABEL: uitofp_v2i1_v2f64:919; AVX512VL-64: # %bb.0:920; AVX512VL-64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]921; AVX512VL-64-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0922; AVX512VL-64-NEXT: vcvtdq2pd %xmm0, %xmm0923; AVX512VL-64-NEXT: retq924;925; AVX512DQ-LABEL: uitofp_v2i1_v2f64:926; AVX512DQ: # %bb.0:927; AVX512DQ-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2,2,3]928; AVX512DQ-NEXT: vbroadcastss {{.*#+}} xmm1 = [1,1,1,1]929; AVX512DQ-NEXT: vandps %xmm1, %xmm0, %xmm0930; AVX512DQ-NEXT: vcvtdq2pd %xmm0, %xmm0931; AVX512DQ-NEXT: ret{{[l|q]}}932;933; AVX512DQVL-32-LABEL: uitofp_v2i1_v2f64:934; AVX512DQVL-32: # %bb.0:935; AVX512DQVL-32-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2,2,3]936; AVX512DQVL-32-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}{1to4}, %xmm0, %xmm0937; AVX512DQVL-32-NEXT: vcvtdq2pd %xmm0, %xmm0938; AVX512DQVL-32-NEXT: retl939;940; AVX512DQVL-64-LABEL: uitofp_v2i1_v2f64:941; AVX512DQVL-64: # %bb.0:942; AVX512DQVL-64-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2,2,3]943; AVX512DQVL-64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0944; AVX512DQVL-64-NEXT: vcvtdq2pd %xmm0, %xmm0945; AVX512DQVL-64-NEXT: retq946 %result = call <2 x double> @llvm.experimental.constrained.uitofp.v2f64.v2i1(<2 x i1> %x,947 metadata !"round.dynamic",948 metadata !"fpexcept.strict") #0949 ret <2 x double> %result950}951 952define <2 x double> @sitofp_v2i8_v2f64(<2 x i8> %x) #0 {953; SSE-LABEL: sitofp_v2i8_v2f64:954; SSE: # %bb.0:955; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]956; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]957; SSE-NEXT: psrad $24, %xmm0958; SSE-NEXT: cvtdq2pd %xmm0, %xmm0959; SSE-NEXT: ret{{[l|q]}}960;961; SSE41-LABEL: sitofp_v2i8_v2f64:962; SSE41: # %bb.0:963; SSE41-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]964; SSE41-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]965; SSE41-NEXT: psrad $24, %xmm0966; SSE41-NEXT: cvtdq2pd %xmm0, %xmm0967; SSE41-NEXT: ret{{[l|q]}}968;969; AVX-LABEL: sitofp_v2i8_v2f64:970; AVX: # %bb.0:971; AVX-NEXT: vpmovsxbd %xmm0, %xmm0972; AVX-NEXT: vcvtdq2pd %xmm0, %xmm0973; AVX-NEXT: ret{{[l|q]}}974 %result = call <2 x double> @llvm.experimental.constrained.sitofp.v2f64.v2i8(<2 x i8> %x,975 metadata !"round.dynamic",976 metadata !"fpexcept.strict") #0977 ret <2 x double> %result978}979 980define <2 x double> @uitofp_v2i8_v2f64(<2 x i8> %x) #0 {981; SSE-LABEL: uitofp_v2i8_v2f64:982; SSE: # %bb.0:983; SSE-NEXT: pxor %xmm1, %xmm1984; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]985; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]986; SSE-NEXT: cvtdq2pd %xmm0, %xmm0987; SSE-NEXT: ret{{[l|q]}}988;989; SSE41-LABEL: uitofp_v2i8_v2f64:990; SSE41: # %bb.0:991; SSE41-NEXT: pxor %xmm1, %xmm1992; SSE41-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]993; SSE41-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]994; SSE41-NEXT: cvtdq2pd %xmm0, %xmm0995; SSE41-NEXT: ret{{[l|q]}}996;997; AVX-LABEL: uitofp_v2i8_v2f64:998; AVX: # %bb.0:999; AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero1000; AVX-NEXT: vcvtdq2pd %xmm0, %xmm01001; AVX-NEXT: ret{{[l|q]}}1002 %result = call <2 x double> @llvm.experimental.constrained.uitofp.v2f64.v2i8(<2 x i8> %x,1003 metadata !"round.dynamic",1004 metadata !"fpexcept.strict") #01005 ret <2 x double> %result1006}1007 1008define <2 x double> @sitofp_v2i16_v2f64(<2 x i16> %x) #0 {1009; SSE-LABEL: sitofp_v2i16_v2f64:1010; SSE: # %bb.0:1011; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]1012; SSE-NEXT: psrad $16, %xmm01013; SSE-NEXT: cvtdq2pd %xmm0, %xmm01014; SSE-NEXT: ret{{[l|q]}}1015;1016; SSE41-LABEL: sitofp_v2i16_v2f64:1017; SSE41: # %bb.0:1018; SSE41-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]1019; SSE41-NEXT: psrad $16, %xmm01020; SSE41-NEXT: cvtdq2pd %xmm0, %xmm01021; SSE41-NEXT: ret{{[l|q]}}1022;1023; AVX-LABEL: sitofp_v2i16_v2f64:1024; AVX: # %bb.0:1025; AVX-NEXT: vpmovsxwd %xmm0, %xmm01026; AVX-NEXT: vcvtdq2pd %xmm0, %xmm01027; AVX-NEXT: ret{{[l|q]}}1028 %result = call <2 x double> @llvm.experimental.constrained.sitofp.v2f64.v2i16(<2 x i16> %x,1029 metadata !"round.dynamic",1030 metadata !"fpexcept.strict") #01031 ret <2 x double> %result1032}1033 1034define <2 x double> @uitofp_v2i16_v2f64(<2 x i16> %x) #0 {1035; SSE-LABEL: uitofp_v2i16_v2f64:1036; SSE: # %bb.0:1037; SSE-NEXT: pxor %xmm1, %xmm11038; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]1039; SSE-NEXT: cvtdq2pd %xmm0, %xmm01040; SSE-NEXT: ret{{[l|q]}}1041;1042; SSE41-LABEL: uitofp_v2i16_v2f64:1043; SSE41: # %bb.0:1044; SSE41-NEXT: pxor %xmm1, %xmm11045; SSE41-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]1046; SSE41-NEXT: cvtdq2pd %xmm0, %xmm01047; SSE41-NEXT: ret{{[l|q]}}1048;1049; AVX-LABEL: uitofp_v2i16_v2f64:1050; AVX: # %bb.0:1051; AVX-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero1052; AVX-NEXT: vcvtdq2pd %xmm0, %xmm01053; AVX-NEXT: ret{{[l|q]}}1054 %result = call <2 x double> @llvm.experimental.constrained.uitofp.v2f64.v2i16(<2 x i16> %x,1055 metadata !"round.dynamic",1056 metadata !"fpexcept.strict") #01057 ret <2 x double> %result1058}1059 1060define <2 x double> @sitofp_v2i32_v2f64(<2 x i32> %x) #0 {1061; SSE-LABEL: sitofp_v2i32_v2f64:1062; SSE: # %bb.0:1063; SSE-NEXT: cvtdq2pd %xmm0, %xmm01064; SSE-NEXT: ret{{[l|q]}}1065;1066; SSE41-LABEL: sitofp_v2i32_v2f64:1067; SSE41: # %bb.0:1068; SSE41-NEXT: cvtdq2pd %xmm0, %xmm01069; SSE41-NEXT: ret{{[l|q]}}1070;1071; AVX-LABEL: sitofp_v2i32_v2f64:1072; AVX: # %bb.0:1073; AVX-NEXT: vcvtdq2pd %xmm0, %xmm01074; AVX-NEXT: ret{{[l|q]}}1075 %result = call <2 x double> @llvm.experimental.constrained.sitofp.v2f64.v2i32(<2 x i32> %x,1076 metadata !"round.dynamic",1077 metadata !"fpexcept.strict") #01078 ret <2 x double> %result1079}1080 1081define <2 x double> @uitofp_v2i32_v2f64(<2 x i32> %x) #0 {1082; SSE-LABEL: uitofp_v2i32_v2f64:1083; SSE: # %bb.0:1084; SSE-NEXT: xorpd %xmm1, %xmm11085; SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]1086; SSE-NEXT: movapd {{.*#+}} xmm1 = [4.503599627370496E+15,4.503599627370496E+15]1087; SSE-NEXT: orpd %xmm1, %xmm01088; SSE-NEXT: subpd %xmm1, %xmm01089; SSE-NEXT: ret{{[l|q]}}1090;1091; SSE41-LABEL: uitofp_v2i32_v2f64:1092; SSE41: # %bb.0:1093; SSE41-NEXT: xorpd %xmm1, %xmm11094; SSE41-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]1095; SSE41-NEXT: movapd {{.*#+}} xmm1 = [4.503599627370496E+15,4.503599627370496E+15]1096; SSE41-NEXT: orpd %xmm1, %xmm01097; SSE41-NEXT: subpd %xmm1, %xmm01098; SSE41-NEXT: ret{{[l|q]}}1099;1100; AVX1-LABEL: uitofp_v2i32_v2f64:1101; AVX1: # %bb.0:1102; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero1103; AVX1-NEXT: vmovddup {{.*#+}} xmm1 = [4.503599627370496E+15,4.503599627370496E+15]1104; AVX1-NEXT: # xmm1 = mem[0,0]1105; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm01106; AVX1-NEXT: vsubpd %xmm1, %xmm0, %xmm01107; AVX1-NEXT: ret{{[l|q]}}1108;1109; AVX512F-LABEL: uitofp_v2i32_v2f64:1110; AVX512F: # %bb.0:1111; AVX512F-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero1112; AVX512F-NEXT: vcvtudq2pd %ymm0, %zmm01113; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm01114; AVX512F-NEXT: vzeroupper1115; AVX512F-NEXT: ret{{[l|q]}}1116;1117; AVX512VL-LABEL: uitofp_v2i32_v2f64:1118; AVX512VL: # %bb.0:1119; AVX512VL-NEXT: vcvtudq2pd %xmm0, %xmm01120; AVX512VL-NEXT: ret{{[l|q]}}1121;1122; AVX512DQ-LABEL: uitofp_v2i32_v2f64:1123; AVX512DQ: # %bb.0:1124; AVX512DQ-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero1125; AVX512DQ-NEXT: vcvtudq2pd %ymm0, %zmm01126; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm01127; AVX512DQ-NEXT: vzeroupper1128; AVX512DQ-NEXT: ret{{[l|q]}}1129;1130; AVX512DQVL-LABEL: uitofp_v2i32_v2f64:1131; AVX512DQVL: # %bb.0:1132; AVX512DQVL-NEXT: vcvtudq2pd %xmm0, %xmm01133; AVX512DQVL-NEXT: ret{{[l|q]}}1134 %result = call <2 x double> @llvm.experimental.constrained.uitofp.v2f64.v2i32(<2 x i32> %x,1135 metadata !"round.dynamic",1136 metadata !"fpexcept.strict") #01137 ret <2 x double> %result1138}1139 1140define <2 x double> @sitofp_v2i64_v2f64(<2 x i64> %x) #0 {1141; SSE-32-LABEL: sitofp_v2i64_v2f64:1142; SSE-32: # %bb.0:1143; SSE-32-NEXT: pushl %ebp1144; SSE-32-NEXT: .cfi_def_cfa_offset 81145; SSE-32-NEXT: .cfi_offset %ebp, -81146; SSE-32-NEXT: movl %esp, %ebp1147; SSE-32-NEXT: .cfi_def_cfa_register %ebp1148; SSE-32-NEXT: andl $-8, %esp1149; SSE-32-NEXT: subl $32, %esp1150; SSE-32-NEXT: movq %xmm0, {{[0-9]+}}(%esp)1151; SSE-32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]1152; SSE-32-NEXT: movq %xmm0, {{[0-9]+}}(%esp)1153; SSE-32-NEXT: fildll {{[0-9]+}}(%esp)1154; SSE-32-NEXT: fstpl {{[0-9]+}}(%esp)1155; SSE-32-NEXT: fildll {{[0-9]+}}(%esp)1156; SSE-32-NEXT: fstpl (%esp)1157; SSE-32-NEXT: wait1158; SSE-32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero1159; SSE-32-NEXT: movhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1]1160; SSE-32-NEXT: movl %ebp, %esp1161; SSE-32-NEXT: popl %ebp1162; SSE-32-NEXT: .cfi_def_cfa %esp, 41163; SSE-32-NEXT: retl1164;1165; SSE-64-LABEL: sitofp_v2i64_v2f64:1166; SSE-64: # %bb.0:1167; SSE-64-NEXT: movq %xmm0, %rax1168; SSE-64-NEXT: cvtsi2sd %rax, %xmm11169; SSE-64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]1170; SSE-64-NEXT: movq %xmm0, %rax1171; SSE-64-NEXT: xorps %xmm0, %xmm01172; SSE-64-NEXT: cvtsi2sd %rax, %xmm01173; SSE-64-NEXT: unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm0[0]1174; SSE-64-NEXT: movapd %xmm1, %xmm01175; SSE-64-NEXT: retq1176;1177; SSE41-32-LABEL: sitofp_v2i64_v2f64:1178; SSE41-32: # %bb.0:1179; SSE41-32-NEXT: pushl %ebp1180; SSE41-32-NEXT: .cfi_def_cfa_offset 81181; SSE41-32-NEXT: .cfi_offset %ebp, -81182; SSE41-32-NEXT: movl %esp, %ebp1183; SSE41-32-NEXT: .cfi_def_cfa_register %ebp1184; SSE41-32-NEXT: andl $-8, %esp1185; SSE41-32-NEXT: subl $32, %esp1186; SSE41-32-NEXT: movq %xmm0, {{[0-9]+}}(%esp)1187; SSE41-32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]1188; SSE41-32-NEXT: movq %xmm0, {{[0-9]+}}(%esp)1189; SSE41-32-NEXT: fildll {{[0-9]+}}(%esp)1190; SSE41-32-NEXT: fstpl {{[0-9]+}}(%esp)1191; SSE41-32-NEXT: fildll {{[0-9]+}}(%esp)1192; SSE41-32-NEXT: fstpl (%esp)1193; SSE41-32-NEXT: wait1194; SSE41-32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero1195; SSE41-32-NEXT: movhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1]1196; SSE41-32-NEXT: movl %ebp, %esp1197; SSE41-32-NEXT: popl %ebp1198; SSE41-32-NEXT: .cfi_def_cfa %esp, 41199; SSE41-32-NEXT: retl1200;1201; SSE41-64-LABEL: sitofp_v2i64_v2f64:1202; SSE41-64: # %bb.0:1203; SSE41-64-NEXT: movq %xmm0, %rax1204; SSE41-64-NEXT: cvtsi2sd %rax, %xmm11205; SSE41-64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]1206; SSE41-64-NEXT: movq %xmm0, %rax1207; SSE41-64-NEXT: xorps %xmm0, %xmm01208; SSE41-64-NEXT: cvtsi2sd %rax, %xmm01209; SSE41-64-NEXT: unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm0[0]1210; SSE41-64-NEXT: movapd %xmm1, %xmm01211; SSE41-64-NEXT: retq1212;1213; AVX-32-LABEL: sitofp_v2i64_v2f64:1214; AVX-32: # %bb.0:1215; AVX-32-NEXT: pushl %ebp1216; AVX-32-NEXT: .cfi_def_cfa_offset 81217; AVX-32-NEXT: .cfi_offset %ebp, -81218; AVX-32-NEXT: movl %esp, %ebp1219; AVX-32-NEXT: .cfi_def_cfa_register %ebp1220; AVX-32-NEXT: andl $-8, %esp1221; AVX-32-NEXT: subl $32, %esp1222; AVX-32-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)1223; AVX-32-NEXT: vshufps {{.*#+}} xmm0 = xmm0[2,3,2,3]1224; AVX-32-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)1225; AVX-32-NEXT: fildll {{[0-9]+}}(%esp)1226; AVX-32-NEXT: fstpl {{[0-9]+}}(%esp)1227; AVX-32-NEXT: fildll {{[0-9]+}}(%esp)1228; AVX-32-NEXT: fstpl (%esp)1229; AVX-32-NEXT: wait1230; AVX-32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero1231; AVX-32-NEXT: vmovhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1]1232; AVX-32-NEXT: movl %ebp, %esp1233; AVX-32-NEXT: popl %ebp1234; AVX-32-NEXT: .cfi_def_cfa %esp, 41235; AVX-32-NEXT: retl1236;1237; AVX-64-LABEL: sitofp_v2i64_v2f64:1238; AVX-64: # %bb.0:1239; AVX-64-NEXT: vpextrq $1, %xmm0, %rax1240; AVX-64-NEXT: vcvtsi2sd %rax, %xmm15, %xmm11241; AVX-64-NEXT: vmovq %xmm0, %rax1242; AVX-64-NEXT: vcvtsi2sd %rax, %xmm15, %xmm01243; AVX-64-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]1244; AVX-64-NEXT: retq1245;1246; AVX512DQ-LABEL: sitofp_v2i64_v2f64:1247; AVX512DQ: # %bb.0:1248; AVX512DQ-NEXT: vmovaps %xmm0, %xmm01249; AVX512DQ-NEXT: vcvtqq2pd %zmm0, %zmm01250; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm01251; AVX512DQ-NEXT: vzeroupper1252; AVX512DQ-NEXT: ret{{[l|q]}}1253;1254; AVX512DQVL-LABEL: sitofp_v2i64_v2f64:1255; AVX512DQVL: # %bb.0:1256; AVX512DQVL-NEXT: vcvtqq2pd %xmm0, %xmm01257; AVX512DQVL-NEXT: ret{{[l|q]}}1258 %result = call <2 x double> @llvm.experimental.constrained.sitofp.v2f64.v2i64(<2 x i64> %x,1259 metadata !"round.dynamic",1260 metadata !"fpexcept.strict") #01261 ret <2 x double> %result1262}1263 1264define <2 x double> @uitofp_v2i64_v2f64(<2 x i64> %x) #0 {1265; SSE-32-LABEL: uitofp_v2i64_v2f64:1266; SSE-32: # %bb.0:1267; SSE-32-NEXT: pushl %ebp1268; SSE-32-NEXT: .cfi_def_cfa_offset 81269; SSE-32-NEXT: .cfi_offset %ebp, -81270; SSE-32-NEXT: movl %esp, %ebp1271; SSE-32-NEXT: .cfi_def_cfa_register %ebp1272; SSE-32-NEXT: andl $-8, %esp1273; SSE-32-NEXT: subl $32, %esp1274; SSE-32-NEXT: movq %xmm0, {{[0-9]+}}(%esp)1275; SSE-32-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]1276; SSE-32-NEXT: movq %xmm1, {{[0-9]+}}(%esp)1277; SSE-32-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]1278; SSE-32-NEXT: movd %xmm1, %eax1279; SSE-32-NEXT: shrl $31, %eax1280; SSE-32-NEXT: fildll {{[0-9]+}}(%esp)1281; SSE-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)1282; SSE-32-NEXT: fstpl {{[0-9]+}}(%esp)1283; SSE-32-NEXT: wait1284; SSE-32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,3,3,3]1285; SSE-32-NEXT: movd %xmm0, %eax1286; SSE-32-NEXT: shrl $31, %eax1287; SSE-32-NEXT: fildll {{[0-9]+}}(%esp)1288; SSE-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)1289; SSE-32-NEXT: fstpl (%esp)1290; SSE-32-NEXT: wait1291; SSE-32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero1292; SSE-32-NEXT: movhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1]1293; SSE-32-NEXT: movl %ebp, %esp1294; SSE-32-NEXT: popl %ebp1295; SSE-32-NEXT: .cfi_def_cfa %esp, 41296; SSE-32-NEXT: retl1297;1298; SSE-64-LABEL: uitofp_v2i64_v2f64:1299; SSE-64: # %bb.0:1300; SSE-64-NEXT: movdqa %xmm0, %xmm11301; SSE-64-NEXT: movq %xmm0, %rax1302; SSE-64-NEXT: movq %rax, %rcx1303; SSE-64-NEXT: shrq %rcx1304; SSE-64-NEXT: movl %eax, %edx1305; SSE-64-NEXT: andl $1, %edx1306; SSE-64-NEXT: orq %rcx, %rdx1307; SSE-64-NEXT: testq %rax, %rax1308; SSE-64-NEXT: cmovnsq %rax, %rdx1309; SSE-64-NEXT: xorps %xmm0, %xmm01310; SSE-64-NEXT: cvtsi2sd %rdx, %xmm01311; SSE-64-NEXT: jns .LBB21_21312; SSE-64-NEXT: # %bb.1:1313; SSE-64-NEXT: addsd %xmm0, %xmm01314; SSE-64-NEXT: .LBB21_2:1315; SSE-64-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]1316; SSE-64-NEXT: movq %xmm1, %rax1317; SSE-64-NEXT: movq %rax, %rcx1318; SSE-64-NEXT: shrq %rcx1319; SSE-64-NEXT: movl %eax, %edx1320; SSE-64-NEXT: andl $1, %edx1321; SSE-64-NEXT: orq %rcx, %rdx1322; SSE-64-NEXT: testq %rax, %rax1323; SSE-64-NEXT: cmovnsq %rax, %rdx1324; SSE-64-NEXT: xorps %xmm1, %xmm11325; SSE-64-NEXT: cvtsi2sd %rdx, %xmm11326; SSE-64-NEXT: jns .LBB21_41327; SSE-64-NEXT: # %bb.3:1328; SSE-64-NEXT: addsd %xmm1, %xmm11329; SSE-64-NEXT: .LBB21_4:1330; SSE-64-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]1331; SSE-64-NEXT: retq1332;1333; SSE41-32-LABEL: uitofp_v2i64_v2f64:1334; SSE41-32: # %bb.0:1335; SSE41-32-NEXT: pushl %ebp1336; SSE41-32-NEXT: .cfi_def_cfa_offset 81337; SSE41-32-NEXT: .cfi_offset %ebp, -81338; SSE41-32-NEXT: movl %esp, %ebp1339; SSE41-32-NEXT: .cfi_def_cfa_register %ebp1340; SSE41-32-NEXT: andl $-8, %esp1341; SSE41-32-NEXT: subl $32, %esp1342; SSE41-32-NEXT: movq %xmm0, {{[0-9]+}}(%esp)1343; SSE41-32-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]1344; SSE41-32-NEXT: movq %xmm1, {{[0-9]+}}(%esp)1345; SSE41-32-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]1346; SSE41-32-NEXT: movd %xmm1, %eax1347; SSE41-32-NEXT: shrl $31, %eax1348; SSE41-32-NEXT: fildll {{[0-9]+}}(%esp)1349; SSE41-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)1350; SSE41-32-NEXT: fstpl {{[0-9]+}}(%esp)1351; SSE41-32-NEXT: wait1352; SSE41-32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,3,3,3]1353; SSE41-32-NEXT: movd %xmm0, %eax1354; SSE41-32-NEXT: shrl $31, %eax1355; SSE41-32-NEXT: fildll {{[0-9]+}}(%esp)1356; SSE41-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)1357; SSE41-32-NEXT: fstpl (%esp)1358; SSE41-32-NEXT: wait1359; SSE41-32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero1360; SSE41-32-NEXT: movhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1]1361; SSE41-32-NEXT: movl %ebp, %esp1362; SSE41-32-NEXT: popl %ebp1363; SSE41-32-NEXT: .cfi_def_cfa %esp, 41364; SSE41-32-NEXT: retl1365;1366; SSE41-64-LABEL: uitofp_v2i64_v2f64:1367; SSE41-64: # %bb.0:1368; SSE41-64-NEXT: movdqa %xmm0, %xmm11369; SSE41-64-NEXT: movq %xmm0, %rax1370; SSE41-64-NEXT: movq %rax, %rcx1371; SSE41-64-NEXT: shrq %rcx1372; SSE41-64-NEXT: movl %eax, %edx1373; SSE41-64-NEXT: andl $1, %edx1374; SSE41-64-NEXT: orq %rcx, %rdx1375; SSE41-64-NEXT: testq %rax, %rax1376; SSE41-64-NEXT: cmovnsq %rax, %rdx1377; SSE41-64-NEXT: xorps %xmm0, %xmm01378; SSE41-64-NEXT: cvtsi2sd %rdx, %xmm01379; SSE41-64-NEXT: jns .LBB21_21380; SSE41-64-NEXT: # %bb.1:1381; SSE41-64-NEXT: addsd %xmm0, %xmm01382; SSE41-64-NEXT: .LBB21_2:1383; SSE41-64-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]1384; SSE41-64-NEXT: movq %xmm1, %rax1385; SSE41-64-NEXT: movq %rax, %rcx1386; SSE41-64-NEXT: shrq %rcx1387; SSE41-64-NEXT: movl %eax, %edx1388; SSE41-64-NEXT: andl $1, %edx1389; SSE41-64-NEXT: orq %rcx, %rdx1390; SSE41-64-NEXT: testq %rax, %rax1391; SSE41-64-NEXT: cmovnsq %rax, %rdx1392; SSE41-64-NEXT: xorps %xmm1, %xmm11393; SSE41-64-NEXT: cvtsi2sd %rdx, %xmm11394; SSE41-64-NEXT: jns .LBB21_41395; SSE41-64-NEXT: # %bb.3:1396; SSE41-64-NEXT: addsd %xmm1, %xmm11397; SSE41-64-NEXT: .LBB21_4:1398; SSE41-64-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]1399; SSE41-64-NEXT: retq1400;1401; AVX-32-LABEL: uitofp_v2i64_v2f64:1402; AVX-32: # %bb.0:1403; AVX-32-NEXT: pushl %ebp1404; AVX-32-NEXT: .cfi_def_cfa_offset 81405; AVX-32-NEXT: .cfi_offset %ebp, -81406; AVX-32-NEXT: movl %esp, %ebp1407; AVX-32-NEXT: .cfi_def_cfa_register %ebp1408; AVX-32-NEXT: andl $-8, %esp1409; AVX-32-NEXT: subl $32, %esp1410; AVX-32-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)1411; AVX-32-NEXT: vshufps {{.*#+}} xmm1 = xmm0[2,3,2,3]1412; AVX-32-NEXT: vmovlps %xmm1, {{[0-9]+}}(%esp)1413; AVX-32-NEXT: vextractps $1, %xmm0, %eax1414; AVX-32-NEXT: shrl $31, %eax1415; AVX-32-NEXT: fildll {{[0-9]+}}(%esp)1416; AVX-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)1417; AVX-32-NEXT: fstpl {{[0-9]+}}(%esp)1418; AVX-32-NEXT: wait1419; AVX-32-NEXT: vextractps $3, %xmm0, %eax1420; AVX-32-NEXT: shrl $31, %eax1421; AVX-32-NEXT: fildll {{[0-9]+}}(%esp)1422; AVX-32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)1423; AVX-32-NEXT: fstpl (%esp)1424; AVX-32-NEXT: wait1425; AVX-32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero1426; AVX-32-NEXT: vmovhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1]1427; AVX-32-NEXT: movl %ebp, %esp1428; AVX-32-NEXT: popl %ebp1429; AVX-32-NEXT: .cfi_def_cfa %esp, 41430; AVX-32-NEXT: retl1431;1432; AVX1-64-LABEL: uitofp_v2i64_v2f64:1433; AVX1-64: # %bb.0:1434; AVX1-64-NEXT: vpextrq $1, %xmm0, %rax1435; AVX1-64-NEXT: movq %rax, %rcx1436; AVX1-64-NEXT: shrq %rcx1437; AVX1-64-NEXT: movl %eax, %edx1438; AVX1-64-NEXT: andl $1, %edx1439; AVX1-64-NEXT: orq %rcx, %rdx1440; AVX1-64-NEXT: testq %rax, %rax1441; AVX1-64-NEXT: cmovnsq %rax, %rdx1442; AVX1-64-NEXT: vcvtsi2sd %rdx, %xmm15, %xmm11443; AVX1-64-NEXT: jns .LBB21_21444; AVX1-64-NEXT: # %bb.1:1445; AVX1-64-NEXT: vaddsd %xmm1, %xmm1, %xmm11446; AVX1-64-NEXT: .LBB21_2:1447; AVX1-64-NEXT: vmovq %xmm0, %rax1448; AVX1-64-NEXT: movq %rax, %rcx1449; AVX1-64-NEXT: shrq %rcx1450; AVX1-64-NEXT: movl %eax, %edx1451; AVX1-64-NEXT: andl $1, %edx1452; AVX1-64-NEXT: orq %rcx, %rdx1453; AVX1-64-NEXT: testq %rax, %rax1454; AVX1-64-NEXT: cmovnsq %rax, %rdx1455; AVX1-64-NEXT: vcvtsi2sd %rdx, %xmm15, %xmm01456; AVX1-64-NEXT: jns .LBB21_41457; AVX1-64-NEXT: # %bb.3:1458; AVX1-64-NEXT: vaddsd %xmm0, %xmm0, %xmm01459; AVX1-64-NEXT: .LBB21_4:1460; AVX1-64-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]1461; AVX1-64-NEXT: retq1462;1463; AVX512F-64-LABEL: uitofp_v2i64_v2f64:1464; AVX512F-64: # %bb.0:1465; AVX512F-64-NEXT: vpextrq $1, %xmm0, %rax1466; AVX512F-64-NEXT: vcvtusi2sd %rax, %xmm15, %xmm11467; AVX512F-64-NEXT: vmovq %xmm0, %rax1468; AVX512F-64-NEXT: vcvtusi2sd %rax, %xmm15, %xmm01469; AVX512F-64-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]1470; AVX512F-64-NEXT: retq1471;1472; AVX512VL-64-LABEL: uitofp_v2i64_v2f64:1473; AVX512VL-64: # %bb.0:1474; AVX512VL-64-NEXT: vpextrq $1, %xmm0, %rax1475; AVX512VL-64-NEXT: vcvtusi2sd %rax, %xmm15, %xmm11476; AVX512VL-64-NEXT: vmovq %xmm0, %rax1477; AVX512VL-64-NEXT: vcvtusi2sd %rax, %xmm15, %xmm01478; AVX512VL-64-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]1479; AVX512VL-64-NEXT: retq1480;1481; AVX512DQ-LABEL: uitofp_v2i64_v2f64:1482; AVX512DQ: # %bb.0:1483; AVX512DQ-NEXT: vmovaps %xmm0, %xmm01484; AVX512DQ-NEXT: vcvtuqq2pd %zmm0, %zmm01485; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm01486; AVX512DQ-NEXT: vzeroupper1487; AVX512DQ-NEXT: ret{{[l|q]}}1488;1489; AVX512DQVL-LABEL: uitofp_v2i64_v2f64:1490; AVX512DQVL: # %bb.0:1491; AVX512DQVL-NEXT: vcvtuqq2pd %xmm0, %xmm01492; AVX512DQVL-NEXT: ret{{[l|q]}}1493 %result = call <2 x double> @llvm.experimental.constrained.uitofp.v2f64.v2i64(<2 x i64> %x,1494 metadata !"round.dynamic",1495 metadata !"fpexcept.strict") #01496 ret <2 x double> %result1497}1498 1499attributes #0 = { strictfp }1500