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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=i386-apple-darwin10 -mattr=+avx | FileCheck %s3 4define <2 x float> @cvt_v2i8_v2f32(<2 x i8> %src) {5; CHECK-LABEL: cvt_v2i8_v2f32:6; CHECK: ## %bb.0:7; CHECK-NEXT: vpmovsxbd %xmm0, %xmm08; CHECK-NEXT: vcvtdq2ps %xmm0, %xmm09; CHECK-NEXT: retl10 %res = sitofp <2 x i8> %src to <2 x float>11 ret <2 x float> %res12}13 14define <2 x float> @cvt_v2i16_v2f32(<2 x i16> %src) {15; CHECK-LABEL: cvt_v2i16_v2f32:16; CHECK: ## %bb.0:17; CHECK-NEXT: vpmovsxwd %xmm0, %xmm018; CHECK-NEXT: vcvtdq2ps %xmm0, %xmm019; CHECK-NEXT: retl20 %res = sitofp <2 x i16> %src to <2 x float>21 ret <2 x float> %res22}23 24define <2 x float> @cvt_v2i32_v2f32(<2 x i32> %src) {25; CHECK-LABEL: cvt_v2i32_v2f32:26; CHECK: ## %bb.0:27; CHECK-NEXT: vcvtdq2ps %xmm0, %xmm028; CHECK-NEXT: retl29 %res = sitofp <2 x i32> %src to <2 x float>30 ret <2 x float> %res31}32 33define <2 x float> @cvt_v2u8_v2f32(<2 x i8> %src) {34; CHECK-LABEL: cvt_v2u8_v2f32:35; CHECK: ## %bb.0:36; CHECK-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero37; CHECK-NEXT: vcvtdq2ps %xmm0, %xmm038; CHECK-NEXT: retl39 %res = uitofp <2 x i8> %src to <2 x float>40 ret <2 x float> %res41}42 43define <2 x float> @cvt_v2u16_v2f32(<2 x i16> %src) {44; CHECK-LABEL: cvt_v2u16_v2f32:45; CHECK: ## %bb.0:46; CHECK-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero47; CHECK-NEXT: vcvtdq2ps %xmm0, %xmm048; CHECK-NEXT: retl49 %res = uitofp <2 x i16> %src to <2 x float>50 ret <2 x float> %res51}52 53define <2 x float> @cvt_v2u32_v2f32(<2 x i32> %src) {54; CHECK-LABEL: cvt_v2u32_v2f32:55; CHECK: ## %bb.0:56; CHECK-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero57; CHECK-NEXT: vmovddup {{.*#+}} xmm1 = [4.503599627370496E+15,4.503599627370496E+15]58; CHECK-NEXT: ## xmm1 = mem[0,0]59; CHECK-NEXT: vpor %xmm1, %xmm0, %xmm060; CHECK-NEXT: vsubpd %xmm1, %xmm0, %xmm061; CHECK-NEXT: vcvtpd2ps %xmm0, %xmm062; CHECK-NEXT: retl63 %res = uitofp <2 x i32> %src to <2 x float>64 ret <2 x float> %res65}66 67define <2 x i8> @cvt_v2f32_v2i8(<2 x float> %src) {68; CHECK-LABEL: cvt_v2f32_v2i8:69; CHECK: ## %bb.0:70; CHECK-NEXT: vcvttps2dq %xmm0, %xmm071; CHECK-NEXT: vpackssdw %xmm0, %xmm0, %xmm072; CHECK-NEXT: vpacksswb %xmm0, %xmm0, %xmm073; CHECK-NEXT: retl74 %res = fptosi <2 x float> %src to <2 x i8>75 ret <2 x i8> %res76}77 78define <2 x i16> @cvt_v2f32_v2i16(<2 x float> %src) {79; CHECK-LABEL: cvt_v2f32_v2i16:80; CHECK: ## %bb.0:81; CHECK-NEXT: vcvttps2dq %xmm0, %xmm082; CHECK-NEXT: vpackssdw %xmm0, %xmm0, %xmm083; CHECK-NEXT: retl84 %res = fptosi <2 x float> %src to <2 x i16>85 ret <2 x i16> %res86}87 88define <2 x i32> @cvt_v2f32_v2i32(<2 x float> %src) {89; CHECK-LABEL: cvt_v2f32_v2i32:90; CHECK: ## %bb.0:91; CHECK-NEXT: vcvttps2dq %xmm0, %xmm092; CHECK-NEXT: retl93 %res = fptosi <2 x float> %src to <2 x i32>94 ret <2 x i32> %res95}96 97define <2 x i8> @cvt_v2f32_v2u8(<2 x float> %src) {98; CHECK-LABEL: cvt_v2f32_v2u8:99; CHECK: ## %bb.0:100; CHECK-NEXT: vcvttps2dq %xmm0, %xmm0101; CHECK-NEXT: vpackusdw %xmm0, %xmm0, %xmm0102; CHECK-NEXT: vpackuswb %xmm0, %xmm0, %xmm0103; CHECK-NEXT: retl104 %res = fptoui <2 x float> %src to <2 x i8>105 ret <2 x i8> %res106}107 108define <2 x i16> @cvt_v2f32_v2u16(<2 x float> %src) {109; CHECK-LABEL: cvt_v2f32_v2u16:110; CHECK: ## %bb.0:111; CHECK-NEXT: vcvttps2dq %xmm0, %xmm0112; CHECK-NEXT: vpackusdw %xmm0, %xmm0, %xmm0113; CHECK-NEXT: retl114 %res = fptoui <2 x float> %src to <2 x i16>115 ret <2 x i16> %res116}117 118define <2 x i32> @cvt_v2f32_v2u32(<2 x float> %src) {119; CHECK-LABEL: cvt_v2f32_v2u32:120; CHECK: ## %bb.0:121; CHECK-NEXT: vcvttps2dq %xmm0, %xmm1122; CHECK-NEXT: vpsrad $31, %xmm1, %xmm2123; CHECK-NEXT: vsubps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0124; CHECK-NEXT: vcvttps2dq %xmm0, %xmm0125; CHECK-NEXT: vpand %xmm2, %xmm0, %xmm0126; CHECK-NEXT: vpor %xmm0, %xmm1, %xmm0127; CHECK-NEXT: retl128 %res = fptoui <2 x float> %src to <2 x i32>129 ret <2 x i32> %res130}131 132define <32 x i8> @PR40146(<4 x i64> %x) {133; CHECK-LABEL: PR40146:134; CHECK: ## %bb.0:135; CHECK-NEXT: vpxor %xmm1, %xmm1, %xmm1136; CHECK-NEXT: vpunpckhbw {{.*#+}} xmm1 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15]137; CHECK-NEXT: vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero138; CHECK-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0139; CHECK-NEXT: retl140 %perm = shufflevector <4 x i64> %x, <4 x i64> undef, <4 x i32> <i32 0, i32 undef, i32 1, i32 undef>141 %t1 = bitcast <4 x i64> %perm to <32 x i8>142 %t2 = shufflevector <32 x i8> %t1, <32 x i8> <i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <32 x i32> <i32 0, i32 32, i32 1, i32 32, i32 2, i32 32, i32 3, i32 32, i32 4, i32 32, i32 5, i32 32, i32 6, i32 32, i32 7, i32 32, i32 16, i32 48, i32 17, i32 48, i32 18, i32 48, i32 19, i32 48, i32 20, i32 48, i32 21, i32 48, i32 22, i32 48, i32 23, i32 48>143 ret <32 x i8> %t2144}145 146