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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=ALL,SSE3; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefixes=ALL,AVX,AVX14; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=ALL,AVX,AVX25 6define <8 x i32> @a(<8 x i32> %a) nounwind {7; SSE-LABEL: a:8; SSE: # %bb.0:9; SSE-NEXT: pslld $16, %xmm010; SSE-NEXT: psrad $16, %xmm011; SSE-NEXT: pslld $16, %xmm112; SSE-NEXT: psrad $16, %xmm113; SSE-NEXT: retq14;15; AVX1-LABEL: a:16; AVX1: # %bb.0:17; AVX1-NEXT: vpslld $16, %xmm0, %xmm118; AVX1-NEXT: vpsrad $16, %xmm1, %xmm119; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm020; AVX1-NEXT: vpslld $16, %xmm0, %xmm021; AVX1-NEXT: vpsrad $16, %xmm0, %xmm022; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm023; AVX1-NEXT: retq24;25; AVX2-LABEL: a:26; AVX2: # %bb.0:27; AVX2-NEXT: vpslld $16, %ymm0, %ymm028; AVX2-NEXT: vpsrad $16, %ymm0, %ymm029; AVX2-NEXT: retq30 %b = trunc <8 x i32> %a to <8 x i16>31 %c = sext <8 x i16> %b to <8 x i32>32 ret <8 x i32> %c33}34 35define <3 x i32> @b(<3 x i32> %a) nounwind {36; SSE-LABEL: b:37; SSE: # %bb.0:38; SSE-NEXT: pslld $16, %xmm039; SSE-NEXT: psrad $16, %xmm040; SSE-NEXT: retq41;42; AVX-LABEL: b:43; AVX: # %bb.0:44; AVX-NEXT: vpslld $16, %xmm0, %xmm045; AVX-NEXT: vpsrad $16, %xmm0, %xmm046; AVX-NEXT: retq47 %b = trunc <3 x i32> %a to <3 x i16>48 %c = sext <3 x i16> %b to <3 x i32>49 ret <3 x i32> %c50}51 52define <1 x i32> @c(<1 x i32> %a) nounwind {53; ALL-LABEL: c:54; ALL: # %bb.0:55; ALL-NEXT: movswl %di, %eax56; ALL-NEXT: retq57 %b = trunc <1 x i32> %a to <1 x i16>58 %c = sext <1 x i16> %b to <1 x i32>59 ret <1 x i32> %c60}61 62define <8 x i32> @d(<8 x i32> %a) nounwind {63; SSE-LABEL: d:64; SSE: # %bb.0:65; SSE-NEXT: movaps {{.*#+}} xmm2 = [65535,0,65535,0,65535,0,65535,0]66; SSE-NEXT: andps %xmm2, %xmm067; SSE-NEXT: andps %xmm2, %xmm168; SSE-NEXT: retq69;70; AVX1-LABEL: d:71; AVX1: # %bb.0:72; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm073; AVX1-NEXT: retq74;75; AVX2-LABEL: d:76; AVX2: # %bb.0:77; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm178; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7],ymm0[8],ymm1[9],ymm0[10],ymm1[11],ymm0[12],ymm1[13],ymm0[14],ymm1[15]79; AVX2-NEXT: retq80 %b = trunc <8 x i32> %a to <8 x i16>81 %c = zext <8 x i16> %b to <8 x i32>82 ret <8 x i32> %c83}84 85define <3 x i32> @e(<3 x i32> %a) nounwind {86; SSE-LABEL: e:87; SSE: # %bb.0:88; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm089; SSE-NEXT: retq90;91; AVX-LABEL: e:92; AVX: # %bb.0:93; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm194; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6,7]95; AVX-NEXT: retq96 %b = trunc <3 x i32> %a to <3 x i16>97 %c = zext <3 x i16> %b to <3 x i32>98 ret <3 x i32> %c99}100 101define <1 x i32> @f(<1 x i32> %a) nounwind {102; ALL-LABEL: f:103; ALL: # %bb.0:104; ALL-NEXT: movzwl %di, %eax105; ALL-NEXT: retq106 %b = trunc <1 x i32> %a to <1 x i16>107 %c = zext <1 x i16> %b to <1 x i32>108 ret <1 x i32> %c109}110