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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=i386-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE3; RUN: llc < %s -mtriple=i386-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX4 5define void @t(<4 x float> %A) {6; SSE-LABEL: t:7; SSE: # %bb.0:8; SSE-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm09; SSE-NEXT: movaps %xmm0, 010; SSE-NEXT: retl11;12; AVX-LABEL: t:13; AVX: # %bb.0:14; AVX-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm015; AVX-NEXT: vmovaps %xmm0, 016; AVX-NEXT: retl17 %tmp1277 = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %A18 store <4 x float> %tmp1277, ptr null19 ret void20}21 22define <4 x float> @t1(<4 x float> %a, <4 x float> %b) {23; SSE-LABEL: t1:24; SSE: # %bb.0: # %entry25; SSE-NEXT: xorps %xmm1, %xmm026; SSE-NEXT: retl27;28; AVX-LABEL: t1:29; AVX: # %bb.0: # %entry30; AVX-NEXT: vxorps %xmm1, %xmm0, %xmm031; AVX-NEXT: retl32entry:33 %tmp9 = bitcast <4 x float> %a to <4 x i32>34 %tmp10 = bitcast <4 x float> %b to <4 x i32>35 %tmp11 = xor <4 x i32> %tmp9, %tmp1036 %tmp13 = bitcast <4 x i32> %tmp11 to <4 x float>37 ret <4 x float> %tmp1338}39 40define <2 x double> @t2(<2 x double> %a, <2 x double> %b) {41; SSE-LABEL: t2:42; SSE: # %bb.0: # %entry43; SSE-NEXT: andps %xmm1, %xmm044; SSE-NEXT: retl45;46; AVX-LABEL: t2:47; AVX: # %bb.0: # %entry48; AVX-NEXT: vandps %xmm1, %xmm0, %xmm049; AVX-NEXT: retl50entry:51 %tmp9 = bitcast <2 x double> %a to <2 x i64>52 %tmp10 = bitcast <2 x double> %b to <2 x i64>53 %tmp11 = and <2 x i64> %tmp9, %tmp1054 %tmp13 = bitcast <2 x i64> %tmp11 to <2 x double>55 ret <2 x double> %tmp1356}57 58define void @t3(<4 x float> %a, <4 x float> %b, ptr %c, ptr %d) {59; SSE-LABEL: t3:60; SSE: # %bb.0: # %entry61; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax62; SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx63; SSE-NEXT: andnps %xmm1, %xmm064; SSE-NEXT: orps (%ecx), %xmm065; SSE-NEXT: movaps %xmm0, (%eax)66; SSE-NEXT: retl67;68; AVX-LABEL: t3:69; AVX: # %bb.0: # %entry70; AVX-NEXT: movl {{[0-9]+}}(%esp), %eax71; AVX-NEXT: movl {{[0-9]+}}(%esp), %ecx72; AVX-NEXT: vandnps %xmm1, %xmm0, %xmm073; AVX-NEXT: vorps (%ecx), %xmm0, %xmm074; AVX-NEXT: vmovaps %xmm0, (%eax)75; AVX-NEXT: retl76entry:77 %tmp3 = load <4 x float>, ptr %c78 %tmp11 = bitcast <4 x float> %a to <4 x i32>79 %tmp12 = bitcast <4 x float> %b to <4 x i32>80 %tmp13 = xor <4 x i32> %tmp11, < i32 -1, i32 -1, i32 -1, i32 -1 >81 %tmp14 = and <4 x i32> %tmp12, %tmp1382 %tmp27 = bitcast <4 x float> %tmp3 to <4 x i32>83 %tmp28 = or <4 x i32> %tmp14, %tmp2784 %tmp30 = bitcast <4 x i32> %tmp28 to <4 x float>85 store <4 x float> %tmp30, ptr %d86 ret void87}88 89define <2 x i64> @andn_double_xor(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {90; SSE-LABEL: andn_double_xor:91; SSE: # %bb.0:92; SSE-NEXT: xorps %xmm2, %xmm193; SSE-NEXT: andnps %xmm1, %xmm094; SSE-NEXT: retl95;96; AVX-LABEL: andn_double_xor:97; AVX: # %bb.0:98; AVX-NEXT: vxorps %xmm2, %xmm1, %xmm199; AVX-NEXT: vandnps %xmm1, %xmm0, %xmm0100; AVX-NEXT: retl101 %1 = xor <2 x i64> %a, <i64 -1, i64 -1>102 %2 = xor <2 x i64> %b, %c103 %3 = and <2 x i64> %1, %2104 ret <2 x i64> %3105}106 107