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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s3 4; These are actually tests of ValueTracking, and so may have test coverage in InstCombine or other5; IR opt passes, but ValueTracking also affects the backend via SelectionDAGBuilder::visitSelect().6 7define <4 x i32> @smin_vec1(<4 x i32> %x) {8; CHECK-LABEL: smin_vec1:9; CHECK: # %bb.0:10; CHECK-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm111; CHECK-NEXT: vpxor %xmm1, %xmm0, %xmm012; CHECK-NEXT: vpminsd %xmm1, %xmm0, %xmm013; CHECK-NEXT: retq14 %not_x = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>15 %cmp = icmp sgt <4 x i32> %x, zeroinitializer16 %sel = select <4 x i1> %cmp, <4 x i32> %not_x, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>17 ret <4 x i32> %sel18}19 20define <4 x i32> @smin_vec2(<4 x i32> %x) {21; CHECK-LABEL: smin_vec2:22; CHECK: # %bb.0:23; CHECK-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm124; CHECK-NEXT: vpxor %xmm1, %xmm0, %xmm025; CHECK-NEXT: vpminsd %xmm1, %xmm0, %xmm026; CHECK-NEXT: retq27 %not_x = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>28 %cmp = icmp slt <4 x i32> %x, zeroinitializer29 %sel = select <4 x i1> %cmp, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %not_x30 ret <4 x i32> %sel31}32 33; TODO:34; This and the next test were intended to become smin,35; but that is not correct in general.36 37define <4 x i32> @smin_vec3(<4 x i32> %x, <4 x i32> %y) {38; CHECK-LABEL: smin_vec3:39; CHECK: # %bb.0:40; CHECK-NEXT: vpsubd %xmm1, %xmm0, %xmm241; CHECK-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm042; CHECK-NEXT: vpandn %xmm2, %xmm0, %xmm043; CHECK-NEXT: retq44 %sub = sub nsw <4 x i32> %x, %y45 %cmp = icmp sgt <4 x i32> %x, %y46 %sel = select <4 x i1> %cmp, <4 x i32> zeroinitializer, <4 x i32> %sub47 ret <4 x i32> %sel48}49 50define <4 x i32> @smin_vec4(<4 x i32> %x, <4 x i32> %y) {51; CHECK-LABEL: smin_vec4:52; CHECK: # %bb.0:53; CHECK-NEXT: vpsubd %xmm1, %xmm0, %xmm254; CHECK-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm055; CHECK-NEXT: vpand %xmm2, %xmm0, %xmm056; CHECK-NEXT: retq57 %sub = sub nsw <4 x i32> %x, %y58 %cmp = icmp slt <4 x i32> %x, %y59 %sel = select <4 x i1> %cmp, <4 x i32> %sub, <4 x i32> zeroinitializer60 ret <4 x i32> %sel61}62 63define <4 x i32> @smax_vec1(<4 x i32> %x) {64; CHECK-LABEL: smax_vec1:65; CHECK: # %bb.0:66; CHECK-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm167; CHECK-NEXT: vpxor %xmm1, %xmm0, %xmm068; CHECK-NEXT: vpmaxsd %xmm1, %xmm0, %xmm069; CHECK-NEXT: retq70 %not_x = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>71 %cmp = icmp slt <4 x i32> %x, zeroinitializer72 %sel = select <4 x i1> %cmp, <4 x i32> %not_x, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>73 ret <4 x i32> %sel74}75 76define <4 x i32> @smax_vec2(<4 x i32> %x) {77; CHECK-LABEL: smax_vec2:78; CHECK: # %bb.0:79; CHECK-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm180; CHECK-NEXT: vpxor %xmm1, %xmm0, %xmm081; CHECK-NEXT: vpmaxsd %xmm1, %xmm0, %xmm082; CHECK-NEXT: retq83 %not_x = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>84 %cmp = icmp sgt <4 x i32> %x, zeroinitializer85 %sel = select <4 x i1> %cmp, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %not_x86 ret <4 x i32> %sel87}88 89; TODO:90; This and the next test were intended to become smax,91; but that is not correct in general.92 93define <4 x i32> @smax_vec3(<4 x i32> %x, <4 x i32> %y) {94; CHECK-LABEL: smax_vec3:95; CHECK: # %bb.0:96; CHECK-NEXT: vpsubd %xmm1, %xmm0, %xmm297; CHECK-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm098; CHECK-NEXT: vpandn %xmm2, %xmm0, %xmm099; CHECK-NEXT: retq100 %sub = sub nsw <4 x i32> %x, %y101 %cmp = icmp slt <4 x i32> %x, %y102 %sel = select <4 x i1> %cmp, <4 x i32> zeroinitializer, <4 x i32> %sub103 ret <4 x i32> %sel104}105 106define <4 x i32> @smax_vec4(<4 x i32> %x, <4 x i32> %y) {107; CHECK-LABEL: smax_vec4:108; CHECK: # %bb.0:109; CHECK-NEXT: vpsubd %xmm1, %xmm0, %xmm2110; CHECK-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0111; CHECK-NEXT: vpand %xmm2, %xmm0, %xmm0112; CHECK-NEXT: retq113 %sub = sub nsw <4 x i32> %x, %y114 %cmp = icmp sgt <4 x i32> %x, %y115 %sel = select <4 x i1> %cmp, <4 x i32> %sub, <4 x i32> zeroinitializer116 ret <4 x i32> %sel117}118 119define <4 x i32> @umax_vec1(<4 x i32> %x) {120; CHECK-LABEL: umax_vec1:121; CHECK: # %bb.0:122; CHECK-NEXT: vpmaxud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0123; CHECK-NEXT: retq124 %cmp = icmp slt <4 x i32> %x, zeroinitializer125 %sel = select <4 x i1> %cmp, <4 x i32> %x, <4 x i32> <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>126 ret <4 x i32> %sel127}128 129define <4 x i32> @umax_vec2(<4 x i32> %x) {130; CHECK-LABEL: umax_vec2:131; CHECK: # %bb.0:132; CHECK-NEXT: vpmaxud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0133; CHECK-NEXT: retq134 %cmp = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>135 %sel = select <4 x i1> %cmp, <4 x i32> <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648>, <4 x i32> %x136 ret <4 x i32> %sel137}138 139define <4 x i32> @umin_vec1(<4 x i32> %x) {140; CHECK-LABEL: umin_vec1:141; CHECK: # %bb.0:142; CHECK-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0143; CHECK-NEXT: retq144 %cmp = icmp slt <4 x i32> %x, zeroinitializer145 %sel = select <4 x i1> %cmp, <4 x i32> <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>, <4 x i32> %x146 ret <4 x i32> %sel147}148 149define <4 x i32> @umin_vec2(<4 x i32> %x) {150; CHECK-LABEL: umin_vec2:151; CHECK: # %bb.0:152; CHECK-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0153; CHECK-NEXT: retq154 %cmp = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>155 %sel = select <4 x i1> %cmp, <4 x i32> %x, <4 x i32> <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648>156 ret <4 x i32> %sel157}158 159; The next 4 tests are value clamping with constants:160; https://llvm.org/bugs/show_bug.cgi?id=31693161 162; (X <s C1) ? C1 : SMIN(X, C2) ==> SMAX(SMIN(X, C2), C1)163 164define <4 x i32> @clamp_signed1(<4 x i32> %x) {165; CHECK-LABEL: clamp_signed1:166; CHECK: # %bb.0:167; CHECK-NEXT: vpminsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0168; CHECK-NEXT: vpmaxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0169; CHECK-NEXT: retq170 %cmp2 = icmp slt <4 x i32> %x, <i32 255, i32 255, i32 255, i32 255>171 %min = select <4 x i1> %cmp2, <4 x i32> %x, <4 x i32><i32 255, i32 255, i32 255, i32 255>172 %cmp1 = icmp slt <4 x i32> %x, <i32 15, i32 15, i32 15, i32 15>173 %r = select <4 x i1> %cmp1, <4 x i32><i32 15, i32 15, i32 15, i32 15>, <4 x i32> %min174 ret <4 x i32> %r175}176 177; (X >s C1) ? C1 : SMAX(X, C2) ==> SMIN(SMAX(X, C2), C1)178 179define <4 x i32> @clamp_signed2(<4 x i32> %x) {180; CHECK-LABEL: clamp_signed2:181; CHECK: # %bb.0:182; CHECK-NEXT: vpmaxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0183; CHECK-NEXT: vpminsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0184; CHECK-NEXT: retq185 %cmp2 = icmp sgt <4 x i32> %x, <i32 15, i32 15, i32 15, i32 15>186 %max = select <4 x i1> %cmp2, <4 x i32> %x, <4 x i32><i32 15, i32 15, i32 15, i32 15>187 %cmp1 = icmp sgt <4 x i32> %x, <i32 255, i32 255, i32 255, i32 255>188 %r = select <4 x i1> %cmp1, <4 x i32><i32 255, i32 255, i32 255, i32 255>, <4 x i32> %max189 ret <4 x i32> %r190}191 192; (X <u C1) ? C1 : UMIN(X, C2) ==> UMAX(UMIN(X, C2), C1)193 194define <4 x i32> @clamp_unsigned1(<4 x i32> %x) {195; CHECK-LABEL: clamp_unsigned1:196; CHECK: # %bb.0:197; CHECK-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0198; CHECK-NEXT: vpmaxud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0199; CHECK-NEXT: retq200 %cmp2 = icmp ult <4 x i32> %x, <i32 255, i32 255, i32 255, i32 255>201 %min = select <4 x i1> %cmp2, <4 x i32> %x, <4 x i32><i32 255, i32 255, i32 255, i32 255>202 %cmp1 = icmp ult <4 x i32> %x, <i32 15, i32 15, i32 15, i32 15>203 %r = select <4 x i1> %cmp1, <4 x i32><i32 15, i32 15, i32 15, i32 15>, <4 x i32> %min204 ret <4 x i32> %r205}206 207; (X >u C1) ? C1 : UMAX(X, C2) ==> UMIN(UMAX(X, C2), C1)208 209define <4 x i32> @clamp_unsigned2(<4 x i32> %x) {210; CHECK-LABEL: clamp_unsigned2:211; CHECK: # %bb.0:212; CHECK-NEXT: vpmaxud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0213; CHECK-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0214; CHECK-NEXT: retq215 %cmp2 = icmp ugt <4 x i32> %x, <i32 15, i32 15, i32 15, i32 15>216 %max = select <4 x i1> %cmp2, <4 x i32> %x, <4 x i32><i32 15, i32 15, i32 15, i32 15>217 %cmp1 = icmp ugt <4 x i32> %x, <i32 255, i32 255, i32 255, i32 255>218 %r = select <4 x i1> %cmp1, <4 x i32><i32 255, i32 255, i32 255, i32 255>, <4 x i32> %max219 ret <4 x i32> %r220}221 222define <4 x i32> @umin_not_ops(<4 x i32> %x) {223; CHECK-LABEL: umin_not_ops:224; CHECK: # %bb.0:225; CHECK-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1226; CHECK-NEXT: vpxor %xmm1, %xmm0, %xmm0227; CHECK-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0228; CHECK-NEXT: retq229 %not_x = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>230 %cmp = icmp ugt <4 x i32> %x, <i32 4, i32 4, i32 4, i32 4>231 %sel = select <4 x i1> %cmp, <4 x i32> %not_x, <4 x i32> <i32 -5, i32 -5, i32 -5, i32 -5>232 ret <4 x i32> %sel233}234 235define <4 x i32> @wrong_pred_for_smin_with_subnsw(<4 x i32> %x, <4 x i32> %y) {236; CHECK-LABEL: wrong_pred_for_smin_with_subnsw:237; CHECK: # %bb.0:238; CHECK-NEXT: vpsubd %xmm1, %xmm0, %xmm2239; CHECK-NEXT: vpminud %xmm1, %xmm0, %xmm1240; CHECK-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0241; CHECK-NEXT: vpand %xmm2, %xmm0, %xmm0242; CHECK-NEXT: retq243 %sub = sub nsw <4 x i32> %x, %y244 %cmp = icmp ugt <4 x i32> %x, %y245 %sel = select <4 x i1> %cmp, <4 x i32> zeroinitializer, <4 x i32> %sub246 ret <4 x i32> %sel247}248 249