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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK3 4; In the following patterns, lhs and rhs of the or instruction have no common bits.5; Therefore, "add" and "or" instructions are equal.6 7define <2 x i32> @or_and_and_rhs_neg_vec_i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %z) {8; CHECK-LABEL: or_and_and_rhs_neg_vec_i32:9; CHECK: # %bb.0:10; CHECK-NEXT: xorps %xmm0, %xmm011; CHECK-NEXT: retq12 %and1 = and <2 x i32> %z, %y13 %xor = xor <2 x i32> %y, <i32 -1, i32 -1>14 %and2 = and <2 x i32> %x, %xor15 %or = or <2 x i32> %and1, %and216 %add = add <2 x i32> %and1, %and217 %sub = sub <2 x i32> %or, %add18 ret <2 x i32> %sub19}20 21define <2 x i32> @or_and_and_lhs_neg_vec_i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %z) {22; CHECK-LABEL: or_and_and_lhs_neg_vec_i32:23; CHECK: # %bb.0:24; CHECK-NEXT: xorps %xmm0, %xmm025; CHECK-NEXT: retq26 %and1 = and <2 x i32> %z, %y27 %xor = xor <2 x i32> %y, <i32 -1, i32 -1>28 %and2 = and <2 x i32> %xor, %x29 %or = or <2 x i32> %and1, %and230 %add = add <2 x i32> %and1, %and231 %sub = sub <2 x i32> %or, %add32 ret <2 x i32> %sub33}34 35define <2 x i32> @or_and_rhs_neg_and_vec_i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %z) {36; CHECK-LABEL: or_and_rhs_neg_and_vec_i32:37; CHECK: # %bb.0:38; CHECK-NEXT: xorps %xmm0, %xmm039; CHECK-NEXT: retq40 %xor = xor <2 x i32> %y, <i32 -1, i32 -1>41 %and1 = and <2 x i32> %z, %xor42 %and2 = and <2 x i32> %x, %y43 %or = or <2 x i32> %and1, %and244 %add = add <2 x i32> %and1, %and245 %sub = sub <2 x i32> %or, %add46 ret <2 x i32> %sub47}48 49define <2 x i32> @or_and_lhs_neg_and_vec_i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %z) {50; CHECK-LABEL: or_and_lhs_neg_and_vec_i32:51; CHECK: # %bb.0:52; CHECK-NEXT: xorps %xmm0, %xmm053; CHECK-NEXT: retq54 %xor = xor <2 x i32> %y, <i32 -1, i32 -1>55 %and1 = and <2 x i32> %xor, %z56 %and2 = and <2 x i32> %x, %y57 %or = or <2 x i32> %and1, %and258 %add = add <2 x i32> %and1, %and259 %sub = sub <2 x i32> %or, %add60 ret <2 x i32> %sub61}62 63define <2 x i64> @or_and_and_rhs_neg_vec_i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %z) {64; CHECK-LABEL: or_and_and_rhs_neg_vec_i64:65; CHECK: # %bb.0:66; CHECK-NEXT: xorps %xmm0, %xmm067; CHECK-NEXT: retq68 %and1 = and <2 x i64> %z, %y69 %xor = xor <2 x i64> %y, <i64 -1, i64 -1>70 %and2 = and <2 x i64> %x, %xor71 %or = or <2 x i64> %and1, %and272 %add = add <2 x i64> %and1, %and273 %sub = sub <2 x i64> %or, %add74 ret <2 x i64> %sub75}76 77define <2 x i64> @or_and_and_lhs_neg_vec_i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %z) {78; CHECK-LABEL: or_and_and_lhs_neg_vec_i64:79; CHECK: # %bb.0:80; CHECK-NEXT: xorps %xmm0, %xmm081; CHECK-NEXT: retq82 %and1 = and <2 x i64> %z, %y83 %xor = xor <2 x i64> %y, <i64 -1, i64 -1>84 %and2 = and <2 x i64> %xor, %x85 %or = or <2 x i64> %and1, %and286 %add = add <2 x i64> %and1, %and287 %sub = sub <2 x i64> %or, %add88 ret <2 x i64> %sub89}90 91define <2 x i64> @or_and_rhs_neg_and_vec_i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %z) {92; CHECK-LABEL: or_and_rhs_neg_and_vec_i64:93; CHECK: # %bb.0:94; CHECK-NEXT: xorps %xmm0, %xmm095; CHECK-NEXT: retq96 %xor = xor <2 x i64> %y, <i64 -1, i64 -1>97 %and1 = and <2 x i64> %z, %xor98 %and2 = and <2 x i64> %x, %y99 %or = or <2 x i64> %and1, %and2100 %add = add <2 x i64> %and1, %and2101 %sub = sub <2 x i64> %or, %add102 ret <2 x i64> %sub103}104 105define <2 x i64> @or_and_lhs_neg_and_vec_i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %z) {106; CHECK-LABEL: or_and_lhs_neg_and_vec_i64:107; CHECK: # %bb.0:108; CHECK-NEXT: xorps %xmm0, %xmm0109; CHECK-NEXT: retq110 %xor = xor <2 x i64> %y, <i64 -1, i64 -1>111 %and1 = and <2 x i64> %xor, %z112 %and2 = and <2 x i64> %x, %y113 %or = or <2 x i64> %and1, %and2114 %add = add <2 x i64> %and1, %and2115 %sub = sub <2 x i64> %or, %add116 ret <2 x i64> %sub117}118