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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE3; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX14; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX25 6define <8 x i16> @sdiv_vec8x16(<8 x i16> %var) {7; SSE-LABEL: sdiv_vec8x16:8; SSE: # %bb.0: # %entry9; SSE-NEXT: movdqa %xmm0, %xmm110; SSE-NEXT: psraw $15, %xmm111; SSE-NEXT: psrlw $11, %xmm112; SSE-NEXT: paddw %xmm1, %xmm013; SSE-NEXT: psraw $5, %xmm014; SSE-NEXT: retq15;16; AVX-LABEL: sdiv_vec8x16:17; AVX: # %bb.0: # %entry18; AVX-NEXT: vpsraw $15, %xmm0, %xmm119; AVX-NEXT: vpsrlw $11, %xmm1, %xmm120; AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm021; AVX-NEXT: vpsraw $5, %xmm0, %xmm022; AVX-NEXT: retq23entry:24 %0 = sdiv <8 x i16> %var, <i16 32, i16 32, i16 32, i16 32, i16 32, i16 32, i16 32, i16 32>25 ret <8 x i16> %026}27 28define <8 x i16> @sdiv_vec8x16_minsize(<8 x i16> %var) minsize {29; SSE-LABEL: sdiv_vec8x16_minsize:30; SSE: # %bb.0: # %entry31; SSE-NEXT: movdqa %xmm0, %xmm132; SSE-NEXT: psraw $15, %xmm133; SSE-NEXT: psrlw $11, %xmm134; SSE-NEXT: paddw %xmm1, %xmm035; SSE-NEXT: psraw $5, %xmm036; SSE-NEXT: retq37;38; AVX-LABEL: sdiv_vec8x16_minsize:39; AVX: # %bb.0: # %entry40; AVX-NEXT: vpsraw $15, %xmm0, %xmm141; AVX-NEXT: vpsrlw $11, %xmm1, %xmm142; AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm043; AVX-NEXT: vpsraw $5, %xmm0, %xmm044; AVX-NEXT: retq45entry:46 %0 = sdiv <8 x i16> %var, <i16 32, i16 32, i16 32, i16 32, i16 32, i16 32, i16 32, i16 32>47 ret <8 x i16> %048}49 50define <4 x i32> @sdiv_vec4x32(<4 x i32> %var) {51; SSE-LABEL: sdiv_vec4x32:52; SSE: # %bb.0: # %entry53; SSE-NEXT: movdqa %xmm0, %xmm154; SSE-NEXT: psrad $31, %xmm155; SSE-NEXT: psrld $28, %xmm156; SSE-NEXT: paddd %xmm1, %xmm057; SSE-NEXT: psrad $4, %xmm058; SSE-NEXT: retq59;60; AVX-LABEL: sdiv_vec4x32:61; AVX: # %bb.0: # %entry62; AVX-NEXT: vpsrad $31, %xmm0, %xmm163; AVX-NEXT: vpsrld $28, %xmm1, %xmm164; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm065; AVX-NEXT: vpsrad $4, %xmm0, %xmm066; AVX-NEXT: retq67entry:68%0 = sdiv <4 x i32> %var, <i32 16, i32 16, i32 16, i32 16>69ret <4 x i32> %070}71 72define <4 x i32> @sdiv_negative(<4 x i32> %var) {73; SSE-LABEL: sdiv_negative:74; SSE: # %bb.0: # %entry75; SSE-NEXT: movdqa %xmm0, %xmm176; SSE-NEXT: psrad $31, %xmm177; SSE-NEXT: psrld $28, %xmm178; SSE-NEXT: paddd %xmm0, %xmm179; SSE-NEXT: psrad $4, %xmm180; SSE-NEXT: pxor %xmm0, %xmm081; SSE-NEXT: psubd %xmm1, %xmm082; SSE-NEXT: retq83;84; AVX-LABEL: sdiv_negative:85; AVX: # %bb.0: # %entry86; AVX-NEXT: vpsrad $31, %xmm0, %xmm187; AVX-NEXT: vpsrld $28, %xmm1, %xmm188; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm089; AVX-NEXT: vpsrad $4, %xmm0, %xmm090; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm191; AVX-NEXT: vpsubd %xmm0, %xmm1, %xmm092; AVX-NEXT: retq93entry:94%0 = sdiv <4 x i32> %var, <i32 -16, i32 -16, i32 -16, i32 -16>95ret <4 x i32> %096}97 98define <8 x i32> @sdiv8x32(<8 x i32> %var) {99; SSE-LABEL: sdiv8x32:100; SSE: # %bb.0: # %entry101; SSE-NEXT: movdqa %xmm0, %xmm2102; SSE-NEXT: psrad $31, %xmm2103; SSE-NEXT: psrld $26, %xmm2104; SSE-NEXT: paddd %xmm2, %xmm0105; SSE-NEXT: psrad $6, %xmm0106; SSE-NEXT: movdqa %xmm1, %xmm2107; SSE-NEXT: psrad $31, %xmm2108; SSE-NEXT: psrld $26, %xmm2109; SSE-NEXT: paddd %xmm2, %xmm1110; SSE-NEXT: psrad $6, %xmm1111; SSE-NEXT: retq112;113; AVX1-LABEL: sdiv8x32:114; AVX1: # %bb.0: # %entry115; AVX1-NEXT: vpsrad $31, %xmm0, %xmm1116; AVX1-NEXT: vpsrld $26, %xmm1, %xmm1117; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm1118; AVX1-NEXT: vpsrad $6, %xmm1, %xmm1119; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0120; AVX1-NEXT: vpsrad $31, %xmm0, %xmm2121; AVX1-NEXT: vpsrld $26, %xmm2, %xmm2122; AVX1-NEXT: vpaddd %xmm2, %xmm0, %xmm0123; AVX1-NEXT: vpsrad $6, %xmm0, %xmm0124; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0125; AVX1-NEXT: retq126;127; AVX2-LABEL: sdiv8x32:128; AVX2: # %bb.0: # %entry129; AVX2-NEXT: vpsrad $31, %ymm0, %ymm1130; AVX2-NEXT: vpsrld $26, %ymm1, %ymm1131; AVX2-NEXT: vpaddd %ymm1, %ymm0, %ymm0132; AVX2-NEXT: vpsrad $6, %ymm0, %ymm0133; AVX2-NEXT: retq134entry:135%0 = sdiv <8 x i32> %var, <i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64>136ret <8 x i32> %0137}138 139define <16 x i16> @sdiv16x16(<16 x i16> %var) {140; SSE-LABEL: sdiv16x16:141; SSE: # %bb.0: # %entry142; SSE-NEXT: movdqa %xmm0, %xmm2143; SSE-NEXT: psraw $15, %xmm2144; SSE-NEXT: psrlw $14, %xmm2145; SSE-NEXT: paddw %xmm2, %xmm0146; SSE-NEXT: psraw $2, %xmm0147; SSE-NEXT: movdqa %xmm1, %xmm2148; SSE-NEXT: psraw $15, %xmm2149; SSE-NEXT: psrlw $14, %xmm2150; SSE-NEXT: paddw %xmm2, %xmm1151; SSE-NEXT: psraw $2, %xmm1152; SSE-NEXT: retq153;154; AVX1-LABEL: sdiv16x16:155; AVX1: # %bb.0: # %entry156; AVX1-NEXT: vpsraw $15, %xmm0, %xmm1157; AVX1-NEXT: vpsrlw $14, %xmm1, %xmm1158; AVX1-NEXT: vpaddw %xmm1, %xmm0, %xmm1159; AVX1-NEXT: vpsraw $2, %xmm1, %xmm1160; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0161; AVX1-NEXT: vpsraw $15, %xmm0, %xmm2162; AVX1-NEXT: vpsrlw $14, %xmm2, %xmm2163; AVX1-NEXT: vpaddw %xmm2, %xmm0, %xmm0164; AVX1-NEXT: vpsraw $2, %xmm0, %xmm0165; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0166; AVX1-NEXT: retq167;168; AVX2-LABEL: sdiv16x16:169; AVX2: # %bb.0: # %entry170; AVX2-NEXT: vpsraw $15, %ymm0, %ymm1171; AVX2-NEXT: vpsrlw $14, %ymm1, %ymm1172; AVX2-NEXT: vpaddw %ymm1, %ymm0, %ymm0173; AVX2-NEXT: vpsraw $2, %ymm0, %ymm0174; AVX2-NEXT: retq175entry:176 %a0 = sdiv <16 x i16> %var, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>177 ret <16 x i16> %a0178}179 180; Div-by-0 in any lane is UB.181 182define <4 x i32> @sdiv_non_splat(<4 x i32> %x) {183; SSE-LABEL: sdiv_non_splat:184; SSE: # %bb.0:185; SSE-NEXT: retq186;187; AVX-LABEL: sdiv_non_splat:188; AVX: # %bb.0:189; AVX-NEXT: retq190 %y = sdiv <4 x i32> %x, <i32 2, i32 0, i32 0, i32 0>191 ret <4 x i32> %y192}193