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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=x86_64-- -mattr=sse4.1 < %s | FileCheck %s -check-prefix=SSE43; RUN: llc -mtriple=x86_64-- -mattr=avx < %s | FileCheck %s -check-prefix=AVX14; RUN: llc -mtriple=x86_64-- -mattr=avx2 < %s | FileCheck %s -check-prefix=AVX25 6define <16 x i16> @split16(<16 x i16> %a, <16 x i16> %b, <16 x i8> %__mask) {7; SSE4-LABEL: split16:8; SSE4: # %bb.0:9; SSE4-NEXT: pminuw %xmm2, %xmm010; SSE4-NEXT: pminuw %xmm3, %xmm111; SSE4-NEXT: retq12;13; AVX1-LABEL: split16:14; AVX1: # %bb.0:15; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm216; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm317; AVX1-NEXT: vpminuw %xmm2, %xmm3, %xmm218; AVX1-NEXT: vpminuw %xmm1, %xmm0, %xmm019; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm020; AVX1-NEXT: retq21;22; AVX2-LABEL: split16:23; AVX2: # %bb.0:24; AVX2-NEXT: vpminuw %ymm1, %ymm0, %ymm025; AVX2-NEXT: retq26 %1 = icmp ult <16 x i16> %a, %b27 %2 = select <16 x i1> %1, <16 x i16> %a, <16 x i16> %b28 ret <16 x i16> %229}30 31define <32 x i16> @split32(<32 x i16> %a, <32 x i16> %b, <32 x i8> %__mask) {32; SSE4-LABEL: split32:33; SSE4: # %bb.0:34; SSE4-NEXT: pminuw %xmm4, %xmm035; SSE4-NEXT: pminuw %xmm5, %xmm136; SSE4-NEXT: pminuw %xmm6, %xmm237; SSE4-NEXT: pminuw %xmm7, %xmm338; SSE4-NEXT: retq39;40; AVX1-LABEL: split32:41; AVX1: # %bb.0:42; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm443; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm544; AVX1-NEXT: vpminuw %xmm4, %xmm5, %xmm445; AVX1-NEXT: vpminuw %xmm2, %xmm0, %xmm046; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm047; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm248; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm449; AVX1-NEXT: vpminuw %xmm2, %xmm4, %xmm250; AVX1-NEXT: vpminuw %xmm3, %xmm1, %xmm151; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm152; AVX1-NEXT: retq53;54; AVX2-LABEL: split32:55; AVX2: # %bb.0:56; AVX2-NEXT: vpminuw %ymm2, %ymm0, %ymm057; AVX2-NEXT: vpminuw %ymm3, %ymm1, %ymm158; AVX2-NEXT: retq59 %1 = icmp ult <32 x i16> %a, %b60 %2 = select <32 x i1> %1, <32 x i16> %a, <32 x i16> %b61 ret <32 x i16> %262}63 64; PR1949265define i128 @split128(<2 x i128> %a, <2 x i128> %b) {66; SSE4-LABEL: split128:67; SSE4: # %bb.0:68; SSE4-NEXT: movq %rdx, %rax69; SSE4-NEXT: addq %r8, %rdi70; SSE4-NEXT: adcq %r9, %rsi71; SSE4-NEXT: addq {{[0-9]+}}(%rsp), %rax72; SSE4-NEXT: adcq {{[0-9]+}}(%rsp), %rcx73; SSE4-NEXT: addq %rdi, %rax74; SSE4-NEXT: adcq %rsi, %rcx75; SSE4-NEXT: movq %rcx, %rdx76; SSE4-NEXT: retq77;78; AVX1-LABEL: split128:79; AVX1: # %bb.0:80; AVX1-NEXT: movq %rdx, %rax81; AVX1-NEXT: addq %r8, %rdi82; AVX1-NEXT: adcq %r9, %rsi83; AVX1-NEXT: addq {{[0-9]+}}(%rsp), %rax84; AVX1-NEXT: adcq {{[0-9]+}}(%rsp), %rcx85; AVX1-NEXT: addq %rdi, %rax86; AVX1-NEXT: adcq %rsi, %rcx87; AVX1-NEXT: movq %rcx, %rdx88; AVX1-NEXT: retq89;90; AVX2-LABEL: split128:91; AVX2: # %bb.0:92; AVX2-NEXT: movq %rdx, %rax93; AVX2-NEXT: addq %r8, %rdi94; AVX2-NEXT: adcq %r9, %rsi95; AVX2-NEXT: addq {{[0-9]+}}(%rsp), %rax96; AVX2-NEXT: adcq {{[0-9]+}}(%rsp), %rcx97; AVX2-NEXT: addq %rdi, %rax98; AVX2-NEXT: adcq %rsi, %rcx99; AVX2-NEXT: movq %rcx, %rdx100; AVX2-NEXT: retq101 %add = add nsw <2 x i128> %a, %b102 %rdx.shuf = shufflevector <2 x i128> %add, <2 x i128> undef, <2 x i32> <i32 undef, i32 0>103 %bin.rdx = add <2 x i128> %add, %rdx.shuf104 %e = extractelement <2 x i128> %bin.rdx, i32 1105 ret i128 %e106}107